JPH05176347A - Noise reducer - Google Patents

Abstract

PURPOSE:To improve picture quality by utilizing correlation between fields and executing noise reducing processing by means of a reproduced signal obtained from, the other channel. CONSTITUTION:A reproduced signal SAB of a channel A is delayed for a prescribed time by a delay circuit 61 and a reproduced signal SB of a channel B is similarly delayed by a delay circuit 41. The signal SA and a delay signal D2 are mutually subtracted by a subtractor 42 and the signal SB and a signal D1 are subtracted by a subtractor 62. The signal SA and an output signal S1 from the subtractor 42 are mutually subtracted 43 to obtain a noise-reduced reproduced signal SA'. Similarly the signal SB and a subtraction signal S2 are applied to a subtractor 63 and a reproduced signal SB' is obtained by noise reducing processing. Since noise reducing processing is executed while utilizing correlation between fields and using a reproduced signal from the other channel, dispersion between two channels can be effectively compensated, flickers on a reproduced picture can be reduced and an afterimage phenomenon can be reduced to improve the picture quality of the reproduced image.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise reducer suitable for application to a VTR adopting line-sequential color difference 2-channel simultaneous recording such as an analog VTR for high definition.

[0002]

2. Description of the Related Art A magnetic recording / reproducing apparatus such as an analog VTR for high definition uses a rotary magnetic head apparatus 80 as shown in FIG.

In the figure, reference numeral 81 is a rotary drum (or rotary disk), and on the rotary drum 81, magnetic heads (Ha, Hb) for recording and reproducing are arranged in proximity so that two channels can be simultaneously recorded. ) And (Hc,
Hd) are arranged so as to maintain respective intervals of approximately 180 °.

By rotating the rotary drum 81 at a double speed, the magnetic tape 82 shown in FIG. 15 has 1125/2 video signals in one field in four tracks 82a-8.
Division recording (2 segment recording) is performed over 2d.
Therefore, for example, the track 82a is recorded by the magnetic head Ha and the track 82b is recorded by the magnetic head Hb. In other words, this magnetic recording / reproducing apparatus employs 1-field 2-segment 2-channel simultaneous recording in which a compressed color difference signal is recorded together with a luminance signal in a color difference line sequential manner as described later.

[0005]

In the VTR adopting such a two-channel simultaneous recording system, the channel output level varies due to variations in reproduction characteristics of the magnetic heads Ha to Hd which perform channel recording and variations in secular change due to wear. Or the noise mixed in each channel is different, the S / N of each channel output is different.
There is a case that does not match.

In such a case, flicker occurs on the reproduced screen, afterimages occur, and S / N deteriorates, which are all causes of deterioration of the image quality of the reproduced screen.

The present invention proposes a noise reducer capable of reducing the image quality deterioration caused by the difference in characteristics between channels.

[0008]

To solve the above problems, in the first invention, a first delay circuit delays a first input signal for a predetermined time and a second input signal delays for a predetermined time. A first delay circuit for subtracting the output of the second delay circuit from the first input signal, and a second delay circuit for subtracting the output of the first delay circuit from the second input signal Second subtraction circuit, a third subtraction circuit that subtracts the output of the first subtraction circuit from the first input signal, and a fourth subtraction circuit that subtracts the output of the second subtraction circuit from the second input signal. A subtraction circuit, and output signals are taken out from the third and fourth subtraction circuits, respectively.

A second aspect of the present invention includes first and second delay circuits having a predetermined delay time, a first subtraction circuit for subtracting an output of the second delay circuit from a first input signal, and a second subtraction circuit. A second subtraction circuit for subtracting the output of the first delay circuit from the input signal, a third subtraction circuit for subtracting the output of the first subtraction circuit from the first input signal, and the second input A fourth subtraction circuit for subtracting the output of the second subtraction circuit from the signal, inputting the output of the third subtraction circuit to the first delay circuit, and outputting the output of the fourth subtraction circuit to the above It is characterized in that it is inputted to the second delay circuit and output signals are respectively taken out from the third subtraction circuit and the fourth subtraction circuit.

[0010]

The operation of the noise reducer according to the first aspect of the invention will be described. FIG. 3 shows an example of the noise reducer 40.
The reproduction signal (first input signal) SA of the A channel is delayed by a first delay circuit 61 for a predetermined time (approximately one field or approximately one horizontal line). The B channel reproduction signal (second input signal) SB is supplied to the second delay circuit 41.
Is delayed by the same time as above.

The reproduction signal SA and the second delay signal D2 are the first
Of the reproduction signal SB and the first delay signal D1 which is the delay output of the first delay circuit 61.
Is subtracted by the second subtraction circuit 62. Next, the reproduction signal SA and the first subtraction signal S1 which is the output of the first subtraction circuit 42 are subtracted by the third subtraction circuit 43 to obtain a reproduction signal SA 'which has been subjected to noise reduction processing.

Similarly, the reproduction signal SB and the second subtraction signal S2, which is the output of the second subtraction circuit 62, are supplied to the fourth subtraction circuit 63, and the reproduction signal SB 'which has been subjected to noise reduction processing from this is supplied. Is obtained.

As described above, the output reproduced signal in which the variation between the channels is corrected can be obtained by performing the noise reduction process while using the reproduced signal from another channel by utilizing the correlation between the fields.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a case where the noise reducer according to the present invention is applied to a VTR for recording / reproducing a high-definition signal adopting the color difference line sequential two-channel simultaneous recording system will be described in detail with reference to the drawings.

FIG. 1 shows an example of a recording system 10R of an analog VTR configured so that the high-definition signal HD can be recorded and reproduced, and FIG. 2 shows an example of the reproducing system 10P. The recording system 10R of FIG. 1 will be described.

In FIG. 1, the luminance signal Y and the pair of color difference signals PB (= BY) and PR (= RY) are band-limited by low-pass filters 1, 2 and 3, respectively, and then A / D converter. It is converted into a digital signal by 4, 5, 6. The pair of digitized color difference signals PB and PR are converted into line-sequential signals by the line-sequentializing circuit 7, and in this state, they are supplied to the time-division multiplexing circuit (TCI encoder) 8 together with the digitized luminance signal Y. A video signal (TCI signal) which has been subjected to time division compression multiplexing processing is formed in the color difference line order as shown in 8A.

That is, when the video signal is recorded in two channels, for example, in the A channel, the compressed color difference signal PB 'is used.
And luminance signal Y time-division multiplexed video signal (FIG. 8A)
Is generated. Therefore, in the B channel, a video signal in which the compressed color difference signal PR 'and the luminance signal Y are time division multiplexed is generated. Then, the shuffling circuit 9 performs shuffling processing on each channel.

The video signals SA and SB which have been subjected to the time division multiplexing process and the shuffling process are D / A converters 11 and 12.
After being converted into an analog signal in, the band is limited by the low pass filters 13 and 14. Then, after being supplied to the FM modulators 15 and 16 of the next stage and subjected to FM modulation so as to be suitable for recording, dedicated magnetic heads Ha and Hb (Hc and Hd) are used via recording amplifiers 17 and 18. 2 channels are recorded (A channel and B channel).

FIG. 2 shows a reproducing system 10P. The video signals reproduced by the magnetic heads Ha to Hd described above are supplied to the FM demodulators 23 and 24 via the preamplifiers 21 and 22, and the video signals are FM demodulated, and the A / D conversion is performed via the low pass filters 25 and 26. After being supplied to the devices 27 and 28 and converted into digital signals, the deshuffling circuit 29 performs deshuffling processing.

The deshuffled video signal is a noise reducer 40 utilizing field correlation according to the present invention.
To the noise reduction processing, and then supplied to the time division separation circuit (TCI decoder) 31 to be separated into the luminance signal Y and the pair of color difference signals PB and PR. Then, each is converted into an analog signal by the D / A converters 32-34, and then the low-pass filters 35-35.
At 37, only the required band is extracted and the final luminance signal Y and the pair of color difference signals PB and PR are output.

The noise reducer 40 provided in the reproducing system 10P is intended to interpolate and correct variations between channels by utilizing field correlation.

FIG. 3 is a system diagram showing the basic concept thereof. The reproduction signal SA of the A channel is delayed by a first delay circuit 61 for a predetermined time (approximately one field or approximately one horizontal line). The reproduction signal SB of the B channel is delayed by the second delay circuit 41 for the same time as described above.

The reproduction signal SA and the second delay signal D2, which is the output of the second delay circuit 41, are subtracted by the first subtraction circuit 42. Also, the reproduction signal SB and the first delay signal D1 which is the delay output of the first delay circuit 61 are the second subtraction circuit 6
Subtraction processing is performed at 2. Next, the reproduction signal SA and the first subtraction signal S1 which is the output of the first subtraction circuit 42 are subtracted by the third subtraction circuit 43 to obtain a reproduction signal SA 'which has been subjected to noise reduction processing. Here, the first subtraction signal S1 corresponds to the difference between the reproduction signals obtained from the channels A and B.

Similarly, the reproduction signal SB and the second subtraction signal S2, which is the output of the second subtraction circuit 62, are supplied to the fourth subtraction circuit 63, and the reproduction signal SB ', which has been subjected to noise reduction processing, is supplied from this. Is obtained.

As described above, it is possible to obtain the output reproduction signal in which the variation between the channels is corrected by performing the noise reduction process while using the reproduction signal from another channel by utilizing the correlation between the fields.

A specific example of the interpolation operation will be described with reference to FIG. In the figure, CH indicates channels A and B. First
Although the field is from the 1st line to the 562nd line, the effective line is considered to be from the 41st line,
Shown from the line. The line of the first field is represented by a solid line. A broken line indicates a line of the second field (563 lines to 1125 lines, and the effective line is shown as 603 lines as above) in interlaced relation with the first field.

For 605 lines in the second field, 563 lines before it are 42 lines (first field), which is 5
The line before 62 hits line 43. Current line is 605
If it is a line, the 605th line is a reproduction signal of A channel, the reproduction signal of 42th line is a signal of B channel, and the reproduction signal of 43th line is A channel.

In order to interpolate the variation between channels using the field correlation, it is necessary to utilize the reproduced signals between different channels. Therefore, considering the luminance signal, as shown by the circle in FIG. 4, if the 605 line of the second field is interpolated by the signal of the difference from the reproduced signal of 42 lines before 563 lines, the field correlation is used. You can do the interpolation.

For the reproduction signal obtained from the 42nd line of the first field, 6 lines before the 562th line of the 42th line
The reproduction signal of the 05th line may be used as an interpolation signal.

As for the color signal, the A channel is the blue color difference signal PB and the B channel is the red color difference signal PR as shown in FIG. The signal may be used for interpolation.

Therefore, it can be seen that when these interpolation relationships are arranged in field units and signal units, the result is as shown in FIG. The noise reducer 40 has a processing circuit configured so as to satisfy the relationship shown in FIG. FIG. 6 shows an example thereof.

The configuration of the A channel system will be described. Since the field memories 41 and 61 forming the delay circuit described above have a field correlation, the delay time is set to (1 field-1 horizontal period (1H)) as described later.

The delay signals D1 and D2 of the field memories 41 and 61 are selected by the first switch 44. The switching signal SW shown in FIG. 8B is supplied to the first switch 44, and the terminal Y is used when the luminance signal Y is interpolated.
To the terminal C side when the color signal is interpolated.

The selected delayed signal itself and the signal delayed by 1H by the delay circuit 45 are the second switch 4
At 6, either one is selected. The second switch 46 is a switch that can be switched for each field, and F1 is the first switch.
In the field, F2 indicates a terminal selected in the second field.

The signal selected by the second switch 46 is further delayed by 1H by the delay circuit 47, and then the third switch 48.
Is supplied to. Since the third switch 48 is a switch selected depending on which of the luminance signal Y and the color signal C is to be interpolated, it is controlled in conjunction with the first switch 44.

Therefore, the following signals are supplied to the terminal C side. The input and output ends of the delay circuit 47 are 1 /
Two coefficient units 51 and 52 are provided, and when the color signals are interpolated, the output color difference signals are combined by the adder 53 to obtain the interpolated color difference signals. This interpolated color difference signal is supplied to the terminal C.

The signal selected by the third switch 48 is supplied to the current reproduction signal SA and the subtractor 42, the inter-field difference signal (interpolation signal) is obtained for the luminance signal Y, and the color signal C is obtained. Interpolation signals in the same field are obtained. A non-linear characteristic is given to the interpolated signal S1 by the limiter 54, and a coefficient k is multiplied by a coefficient unit 55 to correct the output level thereof. The current reproduction signal SA is interpolated by supplying the corrected interpolation signal S1 to the subtractor 43.

Since the B channel system is also configured in the same manner, detailed description thereof will be omitted, and 64, 66, 68 will be described.
Are first to third switches, 65 and 67 are 1H delay circuits, 71 and 72 are 1/2 coefficient units, 73 is an adder, and 62.
Is a subtractor for obtaining the interpolation signal S2. And 7
4 is a limiter and 75 is a coefficient unit.

The difference from the configuration of the A channel system is that the output is supplied to the Y terminal of the third switch 48 via the delay circuit 47, but in the B channel system, the delay circuit of 1H. It is only configured so that it is supplied to the Y terminal of the third switch 68 without passing through 67. This is also clear from the processing content shown in FIG.

First to third switches (44, 46, 4)
8) and (64, 66, 68) are switched in synchronization. Corresponding switching signals including the switching signal SW for that purpose are controlled by a system controller (not shown).

Next, the specific processing operation of the noise reducer 40 thus configured will be described with reference to FIG. 7A and 7B show reproduced signals from the A and B channels, which are shuffled and outputted to the respective segments 1 to 4. Since these are deshuffled by passing through the deshuffling circuit 29, FIG.
The reproduced signals SA and SB shown in d are obtained. These are stored in the field memories 41 and 61 (1 field-1
H), the delay signal D shown in e and f in FIG.
1 and D2 are obtained.

The interpolation processing of the luminance signal will be described. Now the first
When the field is being reproduced, the switch is selected in the state shown in FIG. Line numbers are shown in parentheses in FIG. The same applies to the subsequent figures.

Then, when the current line is 41 lines (A channel) and 42 lines (B channel),
Since the reproduction signal (that is, the delay signal D2) of 606 lines is output to the field memory 41, this is delayed by 1H by the delay circuit 47 and supplied to the subtractor 42. Therefore, the subtraction output S1 becomes S1 = (41)-(604) (line), which is subtracted from the current reproduction signal of 41 lines as an interpolation signal. As is clear from the explanation of FIG.
One line is a reproduced signal of A channel, and 604 line is a reproduced signal of B channel.

Similarly, in the B channel, the reproduction signal of the 605 line output from the field memory 61 is B
As a result of being input to the channel side and being supplied straight to the subtractor 62, an interpolation signal of S2 = (42)-(605) (line) is obtained. This is subtracted from the current line. Here, 42 lines are B channels as shown in FIG. 4, while 605 lines are A channel reproduction signals.

Next, the second field will be described. In the second field, the switches are switched as shown in FIG.

A reproduction signal S of 605 lines is provided in the A channel.
A signal is input and a reproduction signal S of 606 lines is input to B channel
B is typing. Therefore, the field memory 41
Since a reproduction signal of 46 lines (B channel) is output from the circuit, this is further delayed by 2H by the delay circuits 45 and 47.
It is delayed and output. As a result, the subtractor 42 generates an interpolation signal of S1 = (605)-(42) (line), and the reproduction signal of the current 605 line is interpolated by this.

Similarly, in the B channel, the reproduction signal of the 605 line (A channel) which is the output of the field memory 61 is supplied, but since only the delay circuit 65 works on the B channel side, the subtracter 62 eventually outputs S2. = (42)-(605) (line) is obtained, and the reproduction signal SB of 606 lines is interpolated.

Next, co-channel interpolation of color signals will be described. FIG. 10 shows the interpolation processing in the first field, and the switches are switched as shown. As a result, in the A channel system, since the delay circuit 47 is connected in the processing path, the interpolation color signal C1 output from the adder 53 is C1 = {(603) + (605). } / 2, and the final interpolation signal S1 becomes S1 = (41) + C1. As a result, the interpolation processing (solid arrow) from the same channel as described in FIG. 4 is realized.

In the first field, since the B channel system has 42 input lines, C2 = {(604) + (606)} / 2, and the final interpolation signal S2 is S2 = (42) + C2. An interpolated signal is obtained. As a result, the interpolation processing (broken line arrow) from the same channel as described in FIG. 4 is realized.

In the second field, the switch switching state is as shown in FIG. 11, so that in the A channel system, S1 = (605) -C3 = (605)-{(41) + (43)} / 2 Is obtained. In the B channel system, an interpolation signal of S2 = (606) -C4 = (606)-{(42) + (44)} / 2 is obtained. In any case, interpolation is performed using the color difference signals of the same channel.

FIG. 12 shows another example of FIG. This example is a case where the interpolation processing of the color signals is simplified as compared with the case of FIG. 6, and the interpolation processing is realized by using only the adjacent color difference signals.

Therefore, the coefficient units 51, 52, 71, 72
Further, the adders 53 and 73 are not necessary, and the processing path thereof is slightly different accordingly, but the explanation of the interpolation operation is omitted because it is the same as the above case.

FIG. 13 shows the basic configuration of the second invention. In the second invention, the output of the third subtraction circuit 43 is input to the first delay circuit 61, and the output of the fourth subtraction circuit 63 is input to the second delay circuit 41 to perform the third subtraction. Circuit 43
The output signal is extracted from the fourth subtraction circuit 63, and the interpolation operation is the same as the basic configuration of FIG. 3, so the description thereof will be omitted.

[0054]

As described above, according to the present invention, the noise reducer is constructed by utilizing the field correlation for the luminance signal.

According to this, even if there is a variation in the output level between channels, the interpolating process utilizing the field correlation is performed, so that the variation between the two channels can be effectively corrected. Since the flicker appearing on the reproduction screen is reduced and the afterimage phenomenon is reduced, the image quality of the reproduced image can be improved.

Since the color difference signals are also interpolated between the same channels, there is an effect that the deterioration of the vertical resolution can be suppressed and the S / N ratio of the line sequential color difference signals can be improved.

Therefore, the present invention is suitable for application to a VTR or the like for simultaneously recording line-sequential color difference signals for recording / reproducing high-definition signals or the like on two channels.

[Brief description of drawings]

FIG. 1 is a system diagram of a recording system showing an example in which a noise reducer according to the present invention is applied to a high definition analog VTR.

FIG. 2 is a system diagram showing an example of a reproduction system when the noise reducer according to the present invention is applied to a high-definition analog VTR.

FIG. 3 is a system diagram of essential parts showing a basic configuration of a noise reducer according to the first invention.

FIG. 4 is a principle explanatory diagram of a noise reducer.

FIG. 5 is a diagram summarizing a noise reducer operation.

FIG. 6 is a diagram showing a specific operation example in a first field regarding a luminance signal.

FIG. 7 is a diagram for explaining the operation of the noise reducer.

FIG. 8 is a diagram showing a relationship between a TCI signal and a switching signal.

FIG. 9 is a diagram showing a specific operation example in a second field regarding a luminance signal.

FIG. 10 is a diagram showing a specific operation example in the first field regarding a color signal.

FIG. 11 is a diagram illustrating a specific operation example in a second field regarding a color signal.

FIG. 12 is a system diagram showing another embodiment of the first invention.

FIG. 13 is a system diagram showing a basic configuration of a second invention.

FIG. 14 is a diagram of a rotary magnetic head device.

FIG. 15 is a diagram showing an example of a track pattern.

[Explanation of symbols]

 10R recording system 10P reproducing system 40 noise reducer 61 first delay circuit 41 second delay circuit 42 first subtractor 62 second subtractor 43 third subtractor 63 fourth subtractor

Claims (2)

[Claims] 1. A first delaying a first input signal for a predetermined time.
And a second delay circuit for delaying the second input signal by a predetermined time.
Delay circuit, a first subtraction circuit that subtracts the output of the second delay circuit from the first input signal, and a second subtraction circuit that subtracts the output of the first delay circuit from the second input signal A circuit, a third subtraction circuit that subtracts the output of the first subtraction circuit from the first input signal, and a fourth subtraction circuit that subtracts the output of the second subtraction circuit from the second input signal And a noise reducer characterized in that output signals are respectively taken out from the third and fourth subtraction circuits. 2. A first and a second having a predetermined delay time.
Delay circuit, a first subtraction circuit that subtracts the output of the second delay circuit from the first input signal, and a second subtraction circuit that subtracts the output of the first delay circuit from the second input signal. A third subtraction circuit that subtracts the output of the first subtraction circuit from the first input signal, and a fourth subtraction circuit that subtracts the output of the second subtraction circuit from the second input signal The output of the third subtraction circuit is input to the first delay circuit, the output of the fourth subtraction circuit is input to the second delay circuit, and the third subtraction circuit and the fourth subtraction circuit are input. A noise reducer characterized in that each output signal is taken out from a subtraction circuit.