JPH05176187A - Data compression decoding device - Google Patents

Abstract

PURPOSE:To improve the compression and decoding processing speed for the entire device. CONSTITUTION:The data compression decoding device is made up of a data compression circuit consisting of an intermediate data conversion means 1, a coding means 2, and a buffer memory B1, and up of a data decoding circuit consisting of a decoding means 3, an intermediate data inverse conversion means 4 and a buffer memory B2. The intermediate data conversion means 1 in the data compression circuit converts input data into intermediate data and stores the data tentatively into the buffer memory B1. The coding means 2 codes the intermediate data stored in the buffer memory B1 into an output code. The decoding means 3 in the data decoding circuit converts the input code into intermediate data and stores the data tentatively to the buffer memory B2. The intermediate data inverse conversion means 4 inverts the intermediate data stored in the buffer memory B2 into output data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data compression / decompression device, and more particularly to a data compression / decompression device for compressing and decompressing data by using a run length conversion method.

Recently, due to remarkable technological development, various O
Equipment A is undergoing dramatic development. However, like facsimiles and optical disk file systems,
When the device A handles the document information, the data amount of the black-and-white binary image is much larger than that of the character information, and is several ten times to several tens times. Further, in the facsimile, which is one of the OA devices, in order to improve the image quality, the conventional G3 machine (resolution 200 dpi) is shifting to the G4 machine (resolution 400 dpi). Therefore, the data amount is increasing more than the conventional increase in the data amount. In order to cope with such a large increase in the amount of data, a method of reducing the total amount of data without damaging the contents of the data, that is, a data compression method has been proposed.

The definitions of “character” and “character string” are defined in JIS-C6230.
In addition to obeying the name used in information theory,
Data composed of one word unit is called "character", and data composed of arbitrary word unit is called "character string".

[0004]

2. Description of the Related Art Conventionally, an MMR (Modified Modified READ) method and a predictive coding method have been known as compression methods for monochrome binary images. As an example of this, there is Japanese Patent Laid-Open No. 3-58574 by the present applicant, which discloses a data compression method that efficiently compresses by a simple method without depending on the property of data. This data compression method takes in two-dimensional black-and-white binary image information by pre-processing, and performs run-length conversion on the two-dimensional black-and-white binary image information by this pre-processing.
Further, the encoding is performed by the universal encoding method.

The universal encoding system does not assume the statistical properties of the information source in advance at the time of data compression, and therefore can be applied to various data types such as character codes and object codes. Then, as a typical example of the universal coding method, there are an LZ (Lempel-Ziv) coding method and an arithmetic coding method. Further, as the LZ encoding method, universal type and incremental decomposition type (Incremental persing) algorithms have been proposed. Furthermore, as an improved coding method of these algorithms, the LZSS coding method belonging to the universal type and the LZW (Le
mpel-Ziv-Welch) coding method.

The LZ coding method is described in, for example, “Lempel-Ziv data compression method” by Seiji Munakata, Information Processing, pp.2-6, V.
See ol.26, No.1, 1985 for details. Also, L
The ZSS encoding method is TC Bell, "Better OPM / L Text Co.
mpression ", IEEETrans.onCommu., Vol.COM-34, No.12,
It is published in detail in Dec.1986. Furthermore, the LZW encoding method is described in TA Welch, "A Technique for High-Perfor.
mance Data Compression ", Computer, Jun. 1984. The incremental decomposition type encoding method and the LZW encoding method are described in Japanese Patent Laid-Open No. 59-231683 and US Pat.
No. 4,558,302.

Among these encoding methods, the LZW encoding method has been generally used because of its advantages of high-speed processing and simple algorithm. The LZW encoding method is a method that has a rewritable dictionary and performs encoding by the processing described below. First, a new input character string is divided into different partial character strings, and if this partial character string is not registered in the dictionary, all are registered in the dictionary with an identification number in the order of appearance. At the same time, of the currently input partial character strings, a partial character string that matches the longest partial character string is selected from the dictionary and encoded with the identification number attached to the selected partial character string.

A data compression circuit and a data decompression circuit using the LZW encoding method will be described below. FIG. 27
FIG. 6 is a schematic block diagram of a conventional processing circuit. FIG. 27
27A is a schematic block diagram of a conventional data compression circuit, and FIG. 27B is a schematic block diagram of a conventional data decompression circuit.

In FIG. 27 (A), the input speed from another device to the data compression circuit is L, the intermediate data conversion means 12
The input speed of 1 is Mi, the output speed of the intermediate data conversion means 121 is Mo, the input speed of the universal coding means 122 is Ni, and the output speed of the universal coding means 122 is N.
o, and the output speed from the data compression circuit to another device is P
And Here, the input speed Mi and the output speed Mo of the intermediate data converting means 121, and the input speed Ni and the output speed No of the universal encoding means 122 all have different processing speeds depending on the nature of the data to be encoded. The unit of speed is [bytes / sec].

In this case, the input speed L to the data compression circuit
And the input speed Mi of the intermediate data conversion means 121, if the input speed L> input speed Mi, another device for inputting data to the compression circuit is put on standby. Similarly, the output speed Mo of the intermediate data conversion means 121 and the input speed Ni of the universal encoding means 122.
If the output speed Mo is greater than the input speed Ni, the output side of the intermediate data conversion means 121 is put on standby. In particular, the input speed M of the intermediate data conversion means 121
For i and output speed Mo, there is a relation that average: Mo = Mi / 2, minimum: Mo = Mi / 8, maximum: Mo = 2Mi, so when output speed Mo <input speed Ni, universal encoding means Since the input side of 122 is put on standby, the overall processing speed also decreases.

Similarly, in FIG. 27B, the input speed from the other device to the data recovery circuit is Q, the input speed of the universal decoding means 123 is Ri, the output speed of the universal decoding means 123 is Ro, and the intermediate speed is Ro. Data inversion means 1
It is assumed that the input speed of 24 is Si, the output speed of the intermediate data inverse conversion means 124 is So, and the output speed from the data restoration circuit to another device is T. Here, the intermediate data reverse conversion means 1
The input speed Si and output speed So of 24, and the input speed Ri and output speed Ro of the universal decoding means 123 are all different depending on the nature of the data to be decoded. The unit of speed is [bytes / sec].

In this case, the input speed Q to the data recovery circuit
In the relationship between the input speed Ri of the universal decoding means 123 and the input speed Q> input speed Si, another device for inputting data to the restoration circuit is put on standby. Similarly, the output speed Ro of the universal decoding means 123 and the input speed S of the intermediate data inverse conversion means 124.
In the relationship with i, if the output speed Ro> the input speed Si, the output side of the intermediate data inverse conversion means 124 is put on standby. In particular, for the input / output speeds Si and So of the intermediate data inverse conversion means 124, the average: So = 2Si, the minimum: So = 8Si, the maximum:
Since there is a relation of So = Si / 2, when the output speed Ro> the input speed Si, the output side of the universal decoding means 123 is put on standby, and the overall processing speed also decreases.

[0013]

However, in the conventional data compression circuit and data decompression circuit, when the data compression processing and the data decompression processing are performed, the processing speed of the intermediate data conversion means and the universal coding means depends on the nature of the data. Greatly affected. Therefore, the processing speed is different before and after each means, and the other means must wait because the processed data does not arrive.

As described above, when any one of the means is put on standby, the waiting time is accumulated, and it becomes impossible to perform the processing of converting the intermediate data and the processing of universal encoding in parallel. Therefore, there is a problem that the processing speed of the entire circuit of the data compression circuit and the data decompression circuit is reduced.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a data compression / decompression device that improves the processing speed of the entire data compression circuit and data decompression circuit.

[0016]

In the present invention, in order to achieve the above object, as shown in FIG. 1, a data compression circuit comprises an intermediate data conversion means 1, an encoding means 2 and a buffer memory B1. The intermediate data conversion means 1 converts the input data that has been input into intermediate data. Buffer memory B
1 is connected in series with the intermediate data conversion means 1 and the encoding means 2 and temporarily stores the intermediate data output from the intermediate data conversion means 1. The encoding means 2 encodes the intermediate data stored in the buffer memory B1 into an output code.

Further, as shown in FIG. 5, the data compression circuit comprises an intermediate data conversion means 1, an encoding means 2 and at least two or more buffer memories B1. The intermediate data conversion means 1 converts the input data that has been input into intermediate data. The buffer memory B1 is connected in series with the intermediate data converting means 1 and the encoding means 2, and temporarily stores at least two or more of the input data, the intermediate data output from the intermediate data converting means 1 or the output code. Store. The encoding means 2 encodes the intermediate data into an output code.

Further, as shown in FIG. 7, the data compression circuit comprises a plurality of intermediate data converting means 1, a plurality of buffer memories B1, an encoding means 2, a selecting means 11 and a run length integrating means 12. The intermediate data conversion means 1 converts the input data that has been input into intermediate data. The buffer memory B1 is provided corresponding to the intermediate data converting means 1 and temporarily stores the intermediate data. The encoding means 2 encodes the intermediate data into an output code. The selection unit 11 selects any of the intermediate data output from the intermediate data conversion unit 1 based on the integration result from the run length integration unit 12. The run length integrating means 12 is the selecting means 1
The intermediate data selected by 1 is input and integrated, and the integrated result is output to the selection means 11.

As shown in FIG. 9, the data restoration circuit comprises a decoding means 3, an intermediate data inverse conversion means 4 and a buffer memory B2. The decoding means 3 converts the inputted input code into intermediate data. Buffer memory B
Reference numeral 2 is connected in series with the decoding means 3 and the intermediate data inverse conversion means 4, and temporarily stores the intermediate data output from the decoding means 3. The intermediate data inverse conversion means 4 inversely converts the intermediate data stored in the buffer memory B1 into output data.

Then, as shown in FIG. 13, the data restoration circuit comprises a decoding means 3, an intermediate data inverse conversion means 4 and at least two or more buffer memories B2. The decoding means 3 decodes the input code into intermediate data. The buffer memory B2 is connected in series with the decoding means 3 and the intermediate data inverse conversion means 4, and temporarily stores at least two or more of the input code, the intermediate data output from the decoding means 3 and the output data. Store. The intermediate data inverse conversion means 4 inversely converts the intermediate data into output data.

Moreover, as shown in FIG. 15, the data recovery circuit comprises a decoding means 3, a plurality of intermediate data inverse conversion means 4, a plurality of buffer memories B2, a selection means 13 and a run length integration means 14. The decoding means 3 decodes the input code into intermediate data. Buffer memory B2
Is provided corresponding to the intermediate data inverse conversion means 4 and temporarily stores the intermediate data output from the decoding means 3.
The intermediate data inverse conversion means 4 inversely converts the intermediate data into output data. The selection means 13 is a run length integration means 14
Any of the output data output from the intermediate data inverse conversion means 4 is selected based on the integration result from. The run length integrating means 14 inputs the intermediate data output from the decoding means 3 and integrates the intermediate data, and the integration result is selected by the selecting means 13
Output to.

Then, as shown in FIG. 17, the data compression / decompression device comprises a data compression circuit and a data decompression circuit. The data compression circuit comprises an intermediate data conversion means 1, an encoding means 2 and a buffer memory B1. The intermediate data conversion means 1 converts the input data that has been input into intermediate data. The buffer memory B1 is connected in series with the intermediate data converting means 1 and the encoding means 2 and temporarily stores the intermediate data output from the intermediate data converting means 1.
The encoding means 2 encodes the intermediate data stored in the buffer memory B1 into an output code. Further, the data restoration circuit comprises a decoding means 3, an intermediate data inverse conversion means 4 and a buffer memory B2. The decoding means 3 converts the inputted input code into intermediate data. The buffer memory B2 is connected in series with the decoding means 3 and the intermediate data inverse conversion means 4, and temporarily stores the intermediate data output from the decoding means 3. The intermediate data inverse conversion means 4 inversely converts the intermediate data stored in the buffer memory B1 into output data.

[0023]

In the data compression circuit, the intermediate data converting means 1 converts the input data inputted into intermediate data and temporarily stores it in the buffer memory B1. The encoding means 2 is
The intermediate data stored in the buffer memory B1 is encoded into an output code.

In the data compression circuit, the input data that has been input is temporarily stored in the buffer memory B1. The intermediate data converting means 1 converts the input data into intermediate data and temporarily stores it in the buffer memory B1. The encoding means 2 encodes the intermediate data stored in the buffer memory B1 into an output code and temporarily stores it in the buffer memory B1.

Further, in the data compression circuit, the plurality of intermediate data converting means 1 convert the input data inputted into the intermediate data by the predetermined amount, and the corresponding buffer memory B is converted.
It is temporarily stored in 1. The selection means 11 selects the intermediate data stored in the plurality of buffer memories B1 based on the integration result of the run length integration means 12, and the encoding means 2 encodes the selected intermediate data into an output code.

Then, in the data restoration circuit, the decoding means 3 converts the inputted input code into intermediate data and temporarily stores it in the buffer memory B2. The intermediate data inverse conversion means 4 inversely converts the intermediate data stored in the buffer memory B2 into output data.

Then, in the data restoration circuit, the inputted input code is temporarily stored in the buffer memory B2. The decoding means 3 converts the input code into intermediate data and temporarily stores it in the buffer memory B2. The intermediate data inverse conversion means 4 inversely converts the intermediate data stored in the buffer memory B2 into output data, and temporarily stores the output data in the buffer memory B2.

Moreover, in the data restoration circuit, the decoding means 3 converts the input code inputted into intermediate data. The intermediate data is temporarily stored in the selected buffer memory B2 by the selection unit 13 based on the integration result of the run length integration unit 14. The intermediate data inverse conversion means 4 inversely converts the intermediate data stored in the corresponding buffer memory B2 into output data and outputs the output data.

In the data compression / decompression device,
In the data compression circuit, the intermediate data conversion means 1 converts the input data input thereto into intermediate data, and the buffer memory B
It is temporarily stored in 1. The encoding means 2 encodes the intermediate data stored in the buffer memory B1 into an output code. In the data restoration circuit, the decoding means 3 converts the inputted input code into intermediate data and temporarily stores it in the buffer memory B2. The intermediate data inverse conversion means 4 inversely converts the intermediate data stored in the buffer memory B2 into output data.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a first embodiment of the data compression circuit of the present invention. In the figure, the data compression circuit includes a buffer memory B1a, run length conversion means 1a and LZ.
It is composed of W encoding means 2a.

The buffer memory B1a temporarily stores input data input from another device. The run length conversion means 1a converts the input data into run length which is intermediate data. The LZW encoding means 2a encodes the run length into an output code. The run length conversion means 1a corresponds to the intermediate data conversion means 1 of FIG. 1, and the LZW coding means 2a corresponds to the coding means 2 of FIG.

Therefore, by providing the buffer memory B1a, another device and the run length conversion means 1a are provided.
Can perform each processing without being affected by the processing speed of each other. Therefore, the processing speed of the entire data compression circuit is improved.

FIG. 3 is a diagram showing a second embodiment of the data compression circuit of the present invention. In the figure, the data compression circuit comprises a run length conversion means 1a, a buffer memory B1b and an LZW encoding means 2a. Here, the same elements as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

The buffer memory B1b temporarily stores the run length output by the run length conversion means 1a. Therefore, by providing the buffer memory B1b, the run length conversion means 1a and the LZW encoding means 2a can perform the processing of each means without being affected by the processing speed of the other means. Therefore, the processing speed of the entire data compression circuit is improved.

FIG. 4 is a diagram showing a third embodiment of the data compression circuit of the present invention. In the figure, the data compression circuit is composed of a run length conversion means 1a, a buffer memory B1c and an LZW encoding means 2a. Here, the same elements as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

The buffer memory B1c temporarily stores the output code output by the LZW encoding means 2a. Therefore, by providing the buffer memory B1c, the LZW encoding means 2a and other devices can perform their respective processing without being affected by their processing speeds. Therefore, the processing speed of the entire data compression circuit is improved.

FIG. 6 is a diagram showing a fourth embodiment of the data compression circuit of the present invention. In the figure, the data compression circuit includes run length conversion means 1a and buffer memories B1a and B1.
1b, B1c and LZW encoding means 2a. Here, the same elements as those in FIG. 2, FIG. 3 and FIG.

Therefore, the buffer memories B1a and B1
By providing b and B1c, any means and other device can perform each processing without being influenced by the processing speed of each other. Therefore, the processing speed of the entire data compression circuit is improved.

The buffer memories B1a, B1b, B
The buffer 1c may or may not have any buffer memory depending on the nature and cost of the input data to be input. This makes it possible to configure a data compression circuit that is optimal for input data.

FIG. 8 is a diagram showing a fifth embodiment of the data compression circuit of the present invention. In the figure, the data compression circuit includes run length conversion means 1a and 1b and a buffer memory B1.
a, B1b, selecting means 11, run length integrating means 12
And LZW encoding means 2a.

The run length conversion means 1a and 1b convert the input data that has been input into run lengths that are intermediate data. The buffer memories B1a and B1b temporarily store the run lengths output by the run length converting means 1a and 1b, respectively. The selection means 11 switches to input the data stored in either the buffer memory B1a or the buffer memory B1b based on the calculation result of the run length integration means 12. The run length accumulating means 12 accumulates the number of processing data in the buffer memory selected by the selecting means 11 and outputs the result of the integration to the selecting means 11. The LZW encoding means 2a encodes the run length stored in the buffer memory selected by the selection means 11 into an output code.

Therefore, by providing the buffer memory B1a between the run length conversion means 1a and the selection means 11 and the buffer memory B1b between the run length conversion means 1b and the selection means 11, the run length conversion means is provided. The 1a, 1b and the LZW encoding means 2a can perform the processing of each means without being affected by the processing speed of the other means.

Further, even when input data that greatly exceeds the processing speed of the run-length converting means 1a, 1b is input, the selecting means 11 can switch to one of the run-length converting means for conversion processing. Therefore, the processing speed of the entire data compression circuit is further improved.

The run length conversion means 1a and 1b are the same as the intermediate data conversion means 1 of FIG.
a and B1b correspond to the buffer memory B1 in FIG. 1, and the LZW encoding means 2a corresponds to the encoding means 2 in FIG.

Further, in the fifth embodiment of the data compression circuit, two sets of run length conversion means and buffer memories are provided, but three or more sets of run length conversion means and buffer memories are provided according to the speed of input data. May be. As a result, a data compression circuit that is optimal for the speed of input data can be configured, and the processing speed of the entire data compression circuit is further improved.

Although only one LZW encoding means 2a is provided, it may be provided corresponding to the run length conversion means and the buffer memory. Then, the buffer memory B is provided between the run length conversion means 1a and the selection means 11.
1a is provided, and the run length conversion means 1b and the selection means 11 are provided.
Although a buffer memory B1b is provided between the run length conversion means 1a and 1b and an input from another device,
A buffer memory may be provided between the ZW encoding means 2a and the output to another device. Alternatively, at least one or more buffer memories may be provided between any of these.

FIG. 10 shows the first embodiment of the data restoration circuit of the present invention.
It is a figure which shows the Example of. In the figure, the data restoration circuit is composed of a buffer memory B2a, an LZW decoding means 3a and a run length inverse transformation means 4a.

The buffer memory B2a temporarily stores an input code input from another device. The LZW decoding means 3a decodes the input code into a run length which is intermediate data. The run length inverse conversion means 4a inversely converts the run length into output data. The LZW decoding means 3a corresponds to the decoding means 3 in FIG. 9, and the run length inverse conversion means 4a corresponds to the intermediate data inverse conversion means 4 in FIG.

Therefore, by providing the buffer memory B2a, the other device and the LZW decoding means 3a are
Each processing can be performed without being affected by the processing speed of each other. Therefore, the processing speed of the entire data restoration circuit is improved.

FIG. 11 shows the second data restoration circuit of the present invention.
It is a figure which shows the Example of. In the figure, the data restoration circuit is composed of an LZW decoding means 3a, a buffer memory B2b and a run length inverse transformation means 4a. Here, the same elements as those of FIG. 10 are denoted by the same reference numerals, and description thereof will be omitted.

The buffer memory B2b temporarily stores the run length output by the LZW decoding means 3a. Therefore, by providing the buffer memory B2b, the LZW decoding means 3a and the run length inverse transformation means 4a can perform the processing of each means without being affected by the processing speed of the other means. Therefore, the processing speed of the entire data restoration circuit is improved.

FIG. 12 shows the third embodiment of the data restoration circuit of the present invention.
It is a figure which shows the Example of. In the figure, the data restoration circuit is composed of an LZW decoding means 3a, a buffer memory B2c, and a run length inverse transformation means 4a. Here, the same elements as those of FIG. 10 are denoted by the same reference numerals, and description thereof will be omitted.

The buffer memory B2c temporarily stores the output data output by the run length inverse conversion means 4a. Therefore, by providing the buffer memory B2c, the run-length inverse conversion means 4a and other devices can perform their respective processing without being affected by their processing speeds. Therefore, the processing speed of the entire data restoration circuit is improved.

FIG. 14 shows a fourth embodiment of the data restoration circuit of the present invention.
It is a figure which shows the Example of. In the figure, the data restoration circuit includes LZW decoding means 3a and buffer memories B2a and B2.
b, B2c and run length inverse transforming means 4a. Here, the same elements as those in FIGS. 10, 11 and 12 are designated by the same reference numerals, and the description thereof will be omitted.

Therefore, the buffer memories B2a and B2
By providing b and B2c, any means and other device can perform each processing without being influenced by the processing speed of each other. Therefore, the processing speed of the entire data restoration circuit is improved.

The buffer memories B2a, B2b, B
The buffer 2c may or may not be installed with any buffer memory depending on the nature and cost of the input code to be input. This makes it possible to configure a data restoration circuit that is optimal for input data.

FIG. 16 shows the fifth embodiment of the data restoration circuit of the present invention.
It is a figure which shows the Example of. In the figure, the data restoration circuit includes LZW decoding means 3a and buffer memories B2a and B2.
b, run length inverse transforming means 4a, 4b, selecting means 11
And a run length integrating means 12.

The LZW decoding means 3a decodes the inputted input code into run length which is intermediate data. The buffer memories B2a and B2b each temporarily store the run length output by the LZW decoding means 3a. The run length inverse conversion means 4a, 4b inversely convert the run lengths stored in the buffer memories B2a, B2b into output data. The selection means 11 switches to select the output data of the run-length inverse conversion means 4a or the run-length inverse conversion means 4b based on the integration result of the run-length integration means 12. At the same time, the selecting means 11 uses the buffer memories B2a and B2b to be used.
Also switch. The run length integrating means 12 is LZW.
According to the number of processed data output by the decryption means 3a, integration is performed, and the integration result is output to the selection means 11.

Therefore, the buffer memories B2a and B2
By providing b, the LZW decoding means 3a and the run length inverse transformation means 4a, 4b can perform the processing of each means without being affected by the processing speed of the other means. Therefore, the processing speed of the entire data restoration circuit is improved.

The LZW decoding means 3a is the same as the decoding means 3 of FIG. 15, and the buffer memories B2a and B2b are the same as those of FIG.
In the buffer memory B2 of the
Reference numerals a and 4b respectively correspond to the intermediate data inverse conversion means 4 of FIG.

Further, in the fifth embodiment of the data restoration circuit, two sets of run length inverse conversion means and buffer memories are provided, but three or more sets of run length inverse conversion means and buffer memories are provided according to the speed of input data. May be provided.
As a result, a data restoration circuit that is optimal for the speed of the input code can be configured, and the processing speed of the entire data restoration circuit is further improved.

Although only one LZW decoding means 3a is provided, it may be provided corresponding to the run length inverse conversion means and the buffer memory. Then, even when the input data that greatly exceeds the processing speed of the run-length inverse transforming means 4a and 4b is output from the LZW decoding means 3a, the selecting means 11 switches to one of the run-length inverse transforming means for conversion processing. be able to. LZW
Although the buffer memories B2a and B2b are provided between the decoding means 3a and the run length inverse conversion means 4a and 4b, the selection means 11 and the other devices are provided between the input from another device and the LZW decoding means 3a. A buffer memory may be provided between the outputs to. Alternatively, at least one or more buffer memories may be provided between any of these.

FIG. 17 is a diagram showing an embodiment of the data compression / decompression device of the present invention. In the figure, the data compression / decompression device comprises a data compression circuit and a data decompression circuit. The data compression circuit comprises an intermediate data conversion means 1, a buffer memory B1 and an encoding means 2. The intermediate data conversion means 1 converts the input data into intermediate data.
The buffer memory B1 temporarily stores the intermediate data output from the intermediate data converting means 1. Encoding means 2
Encodes the intermediate data into an output code.

The data restoration circuit comprises a decoding means 3, a buffer memory B2 and an intermediate data inverse conversion means 4. The decoding means 3 converts the input code into intermediate data. The buffer memory B1 temporarily stores the intermediate data output from the decoding means 3. The intermediate data inverse conversion means 4 inversely converts the intermediate data into output data.

With this device, the processing speed of data compression processing and data decompression processing is improved. It should be noted that, as in the embodiment shown in FIGS. 8 and 16, by providing a plurality of sets of intermediate data conversion means and buffer memory in the data compression circuit and buffer memory and intermediate data inverse conversion means in the data decompression circuit, it is possible to further improve the apparatus. The overall processing speed can be improved. Further, the buffer memory is not limited to the position shown in FIG. 17, but may be provided at the positions shown in FIGS. 2, 4, 10, and 12 according to the characteristics of the data to be processed, so that the optimum data compression A restoration device can be configured.

Next, the run length transform / inverse transform, the run length transforming means and the run length inverse transforming means shown in the above embodiment will be explained. FIG. 18 is a diagram for explaining the run length conversion / inverse conversion. The image data 21 optically obtained by a facsimile or the like is composed of a bit stream of a plurality of lines (here, 4 lines), and each bit is represented by monochrome binary data. This image data 21
Is converted into a black-and-white pattern of bits forming each column and a number in which the pattern is two-dimensionally continuous, that is, a run length.

In the figure, for example, the bits forming the leftmost column 21A are white, white and black in order from the top. Since this white-white-black-and-white pattern is continuous for two columns, its run length is 2. The data for these two columns becomes the pattern and run length data shown in the leftmost column 22A of the converted data 22. If each of the pattern data and the run length data is represented by 4 bits, the run length data is composed of 8 bits.

FIG. 19 is a diagram for explaining the principle of the run length conversion means. In the figure, the run length conversion means comprises a data input means 31, a parallel / serial conversion means 32, a run length detection means 33 and a run length output means 34.

The data input means 31 inputs input data composed of a bit stream of a plurality of lines from an information source. The parallel-serial conversion means 32 converts the input data that has been input from parallel to serial. That is, as shown in FIG. 18, input data input for each column is converted into data for each row. The run length detecting means 33 shifts the serially converted input data bit by bit, and determines whether the input data matches the preceding bit, thereby determining whether the bits constituting the same column of a plurality of lines have the same length. The pattern and run length of the input data are detected. The run length output means 34 outputs the run length data detected by the run length detection means 33.

FIG. 20 is an explanatory view of the principle of the run length inverse transforming means. In the figure, the run length inverse conversion means is
It comprises a run length data input means 41, a serial inverse conversion means 42 and a data output means 43.

The run length data input means 41 inputs run length data from an information source. Based on the run length data, the serial inverse conversion means 42 inversely converts the run length data into serial data for each line formed of a bit stream. The data output means 43 outputs the serial data for each line as parallel output data for a plurality of lines.

Next, with respect to the LZW encoding means and the LZW decoding means shown in the above embodiment, a concrete processing procedure will be described. FIG. 21 is a diagram showing a specific example of the case where an input character string is encoded by an encoding algorithm of LZW code. This input character string is a character string consisting of a combination of only three characters a, b, and c. First, in the dictionary, only one character a, b, c is coded 1, 2, 3 respectively in advance.
Initialize to register in association with.

First, the input character string 71 is read character by character from left to right. The first letter a is read and this a is used as the prefix (string). Next, the second character b is read, and ab obtained by adding this b to the preceding letter a is collated with the registered character string in the dictionary. At this time, since there is no character string matching ab in the dictionary, the corresponding code 1 of the preceding letter a is output as the encoded output. The output code is shown in the output code column 72. At the same time, the character string ab is registered in the dictionary in association with the code 4. The contents registered in this dictionary are shown in the registration contents column 73. Here, let the second input character b be the initial letter again.

Next, the third character a of the input character string 71 is read, and ba, which is the initial character b plus this a, is collated with the registered character string in the dictionary. At this time, since the character string matching ba is not in the dictionary, the corresponding code 2 of the initial letter b is output as the encoded output, and the character string ba is registered in the dictionary in correspondence with the code 5. In addition, the third input character a is defined as the initial letter.

Further, the fourth character b is read, and ab which is the initial character a plus this b is collated with the registered character string in the dictionary. At this time, since the character string matching ab is registered in the dictionary, ab is the initial character string at this time.
Furthermore, the fifth input character c is read and the initial character string a
The abc obtained by adding the c to the b is collated with the registered character string in the dictionary. At this time, since there is no character string matching abc in the dictionary, the corresponding code 4 of the initial character string ab is output as an encoded output, and the character string abc is registered in the dictionary in correspondence with the code 6. Then, the fifth input character c is set as the initial letter again.

Thereafter, encoding and dictionary registration are continued by the same algorithm. With this algorithm, the input character strings a, b, a, b, c, ... Are encoded,
Codes 1, 2, 4, as shown in the output code column 72 of FIG.
3, ... Are output as encoded outputs. Then, the registration character string 91 and the corresponding code 92 as shown in FIG.
The correspondence relationship with is registered in the dictionary.

FIG. 22 is a flow chart showing the processing procedure of the encoding shown in FIG. In the figure, the number following S indicates a step number. [S101] By initializing, all the one characters that may be input are registered in the dictionary in correspondence with the codes. The address n to be registered next in the dictionary
Is set to 256, for example. Here, n corresponds to the total number of registered character strings, when the codes are assigned 0, 1, 2, ... Corresponding to the character strings registered in the dictionary. Furthermore, the input character string is read, and the first character input is used as a prefix string ω.

[S102] The next input character K is read. [S103] In step S102, it is determined whether or not there is input character data. If the input character data exists, the process proceeds to step S105, and if not, the process proceeds to step S104.

[S104] The initial character string ω is collated with the dictionary, and the corresponding code code (ω) is read out and output as an encoded output. At this time, the code code (ω) is converted into a binary code having a bit number of [log ₂ n] and output. here,
The symbol [x] represents the smallest integer among the integers of the numerical value x or more. Hereinafter, the symbol [x] will be used in this sense. Since there is no character string to be processed in this step, this step is terminated after this step is executed.

[S105] Step S is added to the initial character string ω.
The character string ωK added with the character K read in 102 is collated with the dictionary to determine whether the character string ωK is registered in the dictionary. If registered, the process proceeds to step S106, and if not registered, the process proceeds to step S107.

[S106] The character string ωK is set again as the initial character string ω. Then, the process returns to step S102 again. In this way, by repeating steps S102 to S106, as a character string that matches the input character string,
The maximum length character string of the character strings registered in the dictionary is searched.

[S107] The initial character string ω is collated with the dictionary, and the corresponding code code (ω) is read and output as a coded output. The number of bits of the code code (ω) at this time is [log ₂ n]. Further, the value of n is associated with the character string ωK and registered in the dictionary. That is, the address n of the dictionary
The character string ωK is stored in. Further, the character K read in step S102 is used as the initial character string ω, and the dictionary address n is incremented to prepare for execution of step S102 and subsequent steps for the next new input character string.

FIG. 24 is a diagram showing a specific example of the case where the encoded output shown in FIG. 21 is restored. Only the codes 1, 2, and 3 are registered in advance in the dictionary on the restoration side by initialization so as to be associated with the characters a, b, and c, respectively.

First, the input code 81 is read from left to right one by one. The first code 1 is read and the character string a is restored by referring to the dictionary. The character string restored at this time is shown in the restored character string column 821. The first code is always registered in the dictionary by initialization. Then, the second code 2 is read, and the character string b is restored by referring to the dictionary. At this time, the last input code 1 and the first character b of the character string decoded this time
The reference numeral 4 is associated with “1b” that is a combination of and and registered in the dictionary. The registered contents at this time are displayed in the registered contents column 8
3 shows.

Next, the third code 4 of the input character string 81 is read, and the corresponding "1b" is read by referring to the dictionary. Further, the code 1 of "1b" is referenced to read the corresponding character a. Such a series of repeated read operations is called "recursive decoding". This is the recursive decoding field 8
2 shows. As a result, the character string ab is restored and output as a restored character string. The output character string is shown in the restored character string column 831. At the same time, a combination of the previous input code 2 and the first character a of the character string restored this time, "2
"5" is associated with "a" and registered in the dictionary.

Thereafter, character string restoration and dictionary registration are continued by the same algorithm. In this way, the input code 1,
Restoration is performed for 2, 4, 3, 5, ...
Character strings a, b, a as shown in the restored character string column 821
b, c, ba, ... Are output as a restored character string.
Then, the correspondence relationship between the registration code 93 and the corresponding character string 94 as shown in FIG. 23B is registered in the dictionary.

FIG. 25 is a flow chart showing the decoding processing procedure shown in FIG. In the figure, the number following S indicates a step number. [S111] By initializing, the characters are registered in the dictionary in correspondence with the characters that may be input. Also, the address n to be registered next in the dictionary is
For example, it is set to 256. Here, n corresponds to the total number of registered character strings, when the codes are assigned 0, 1, 2, ... Corresponding to the character strings registered in the dictionary. Next, read the input code and set the first input code CODE (binary code) to 1
The input code ω is converted to a 0-ary number. In this case, ω was the input character string in the encoding of FIG. 22, but in this decoding ω
Note that is the input code. And this ω
OLD ω. At the same time, since the code to be input first is already registered in the dictionary, the character D corresponding to the input code ω
(Ω) is searched from the dictionary and output as the restored character. The output character is set in FINchar for exception processing in step S116 described later.

[S112] The next input code CODE is read. [S113] It is determined whether or not there is input code data in step S112. If it exists, the process proceeds to step S115, and if it does not exist, this processing procedure ends.

[S114] The read input code CODE is converted into the input code ω, and this input code ω is changed to INω.
Set to. [S115] The input code ω is compared with n. That is, it is determined whether or not the input code is registered in the dictionary (ω ≧ n). If ω is smaller than n, step S11
7 and proceeds to step S116 when ω is n or more. Note that ω becomes n or more when, for example, the input code column 81 in FIG. 24 is “8”.

[S116] OLD ω and FINchar set in step S111 or the previous step S119
Replace the set (OLD ω, FINchar) with ωK. That is, the value set in OLD ω is set in ω, and the value set in FINchar is set in K. Then, K is pushed onto the stack (PUSH). Note that ω is in step S117
Is decrypted with.

[S117] Usually, since the input code ω is registered in the dictionary by the processing up to the previous time, the character string D (ω) corresponding to the input code ω is read from the dictionary. The read character string D (ω) is decomposed into ω _i K. ω _i is a code and K is a decoded character. Then, it is determined whether or not the character string D (ω) is one character that cannot be decomposed into ω _i K. D (ω)
Is decomposed into ω _i K, the process proceeds to step S118,
If D (ω) is one character, the process proceeds to step S119.

[S118] The letter K is temporarily pushed onto the stack, the code ω _{i is set} to a new ω, and the process returns to step S117. The execution of steps S117 and S118 is repeated until D (ω) reaches one character.

[S119] LIFO (Last In Fast Out) for each character pushed onto the stack in step S118
Pop (POP) in the format and output the restored character string. For example, if the input code column 81 in FIG. 24 is "5",
Pushed on the stack in the order of a and b, and the restored character string ba is output. At the same time, the first character of the character string restored this time is set to FINchar, and the previously set OLDω
A character string consisting of a combination with FINchar (OLDω, FINchar) is registered in the dictionary in correspondence with the value of n. That is, this character string is stored at address n of the dictionary. Further, n is incremented and IN set in step S114 is set.
ω is set to OLD ω to prepare for execution of the next step S112 and thereafter.

As described above, in the decoding process, the data before encoding is restored by repeating the steps S117 to S119 of FIG. That is, since the input code ω is registered in the dictionary by the processing up to the previous time,
The character string D (ω) corresponding to the input code ω is read from the dictionary. Further, the read character string D (ω) is decomposed into ω _i K, and this character K is temporarily saved in the stack. Then, using the code ω _i as a new input code ω, the character string D (ω) corresponding to the input code ω is read again from the dictionary. These procedures are recursively repeated until the new input code ω becomes one character. Then, the character saved in the stack is L
This is a method of popping and outputting in the IFO format.

FIG. 26 is a diagram showing an example of a tree structure of a dictionary used in the above processing procedure and the like. The tree structure of this dictionary is
It is the figure which shows the internal structure of the dictionary used at the time of encoding and decoding by the algorithm realized in the LZW encoding means and the LZW decoding means. In FIG. 26, the circled numbers indicate the identification numbers, and the places with the circled numbers are called “nodes”.

The dictionary 50 has a root 51 as a starting point. No characters are assigned to this route 51. Then, the first character is registered one level below the root 51, that is, in the first level 52. When registering the first character, different characters are registered.
It is done at the time of initialization. Although three characters “a”, “b”, and “c” are registered in the figure, actually 256 characters that can be represented by 8-bit data are registered.

The layers below the second layer 53 are characters registered by learning the character string input from the information source. A node having a layer one level below is called a "branch", and a node having a layer one level below is called a "leaf". Therefore, in the figure, circled numbers 25, 26, 13, 14, 27, 28, 16, 6, ...
.., 22, 23, and 24 are "leaf", and the other nodes are "branches".

Even if a certain node is currently a “leaf”, it may become a “branch” due to learning. For example,
When the character string "acd" is registered in the dictionary 50, the character string "ac" is registered as "a" (circle number 1) in the first layer 52 and "c" (circle number 6) in the second layer 53. Therefore, “d” is newly registered in the third layer 54 below “c” in the second layer 53. At this time, circle number 6
Node changes from "leaf" to "branch".

In the above description of the embodiments, the code is output by the data compression circuit as the output code having the smallest integer bit number of log ₂ n or more.
Bit fraction compensation, Phasin, as disclosed in No. 23
You may output with g in Binary Codes or the output code which consists of multi-valued arithmetic codes.

Although the dictionary used for encoding and decoding is constructed based on the tree structure, the dictionary may be constructed based on other construction methods such as constructing the dictionary based on the hash function. Good. For example, a dictionary may be constructed by a binary tree method and data such as character strings registered in the dictionary may be searched by a binary search.

The above embodiments are applied to compression and decompression of character codes, vector information, image data, etc. in workstations and the like, and the required storage capacity can be greatly reduced.

It can also be applied to data transmission / reception using a communication line, and the communication time can be shortened. For example, it can be applied to communication devices such as a modem and a facsimile.

[0103]

As described above, in the present invention, in the data compression circuit, since the buffer memory is provided between the other device and the intermediate data converting means, in each case, the mutual processing speeds vary depending on the nature of the data. The conversion process can be performed without being affected.

Further, since the buffer memory is provided between the intermediate data converting means and the encoding means in the data compression circuit, neither means is affected by the fluctuation of the processing speed of the other means due to the nature of the data. Can be converted.

Further, in the data compression circuit, since the buffer memory is provided between the encoding means and the other device, both can perform the conversion processing without being affected by the mutual fluctuation of the processing speed due to the nature of the data. it can.

Since the buffer memory is provided between the other device and the decoding means in the data restoration circuit,
In either case, the inverse conversion processing can be performed without being affected by the mutual fluctuations in processing speed due to the nature of the data.

Then, in the data restoration circuit, since the buffer memory is provided between the decoding means and the intermediate data inverse conversion means, both means are affected by the fluctuation of the processing speed of the other means due to the nature of the data. Inverse conversion processing can be performed without.

In addition, since the buffer memory is provided between the intermediate data inverse conversion means and the other device in the data restoration circuit, in each case, the inverse conversion is performed without being affected by the mutual fluctuation of the processing speed due to the nature of the data. Can be processed.

Then, in the data compression / decompression device,
Since the buffer memory is provided between the intermediate data conversion means and the encoding means in the data compression circuit, and between the decoding means and the intermediate data reverse conversion means in the data decompression circuit, both means store the data. The conversion process and the inverse conversion process can be performed without being affected by the fluctuation of the processing speed of other means depending on the property.

Therefore, the processing speed of each circuit and the entire device can be improved.

[Brief description of drawings]

FIG. 1 is a first principle explanatory diagram of a data compression circuit of the present invention.

FIG. 2 is a diagram showing a first embodiment of a data compression circuit of the present invention.

FIG. 3 is a diagram showing a second embodiment of the data compression circuit of the present invention.

FIG. 4 is a diagram showing a third embodiment of the data compression circuit of the present invention.

FIG. 5 is a second principle explanatory diagram of the data compression circuit of the present invention.

FIG. 6 is a diagram showing a fourth embodiment of the data compression circuit of the present invention.

FIG. 7 is a diagram illustrating a third principle of the data compression circuit of the present invention.

FIG. 8 is a diagram showing a fifth embodiment of the data compression circuit of the present invention.

FIG. 9 is a first principle explanatory diagram of the data restoration circuit of the present invention.

FIG. 10 is a diagram showing a first embodiment of a data restoration circuit of the present invention.

FIG. 11 is a diagram showing a second embodiment of the data restoration circuit of the present invention.

FIG. 12 is a diagram showing a third embodiment of the data restoration circuit of the present invention.

FIG. 13 is a second principle explanatory diagram of the data restoration circuit of the present invention.

FIG. 14 is a diagram showing a fourth embodiment of the data restoration circuit of the present invention.

FIG. 15 is a diagram illustrating a third principle of the data restoration circuit of the present invention.

FIG. 16 is a diagram showing a fifth embodiment of the data restoration circuit of the present invention.

FIG. 17 is an explanatory diagram of the principle of the data compression / decompression device of the present invention.

FIG. 18 is a diagram illustrating run-length conversion / inverse conversion.

FIG. 19 is a diagram illustrating the principle of run length conversion means.

FIG. 20 is a diagram illustrating the principle of run length inverse transforming means.

FIG. 21 is a diagram showing a specific example of encoding.

FIG. 22 is a diagram illustrating a coding processing procedure.

FIG. 23 is a correspondence diagram of character strings and codes.

FIG. 24 is a diagram showing a specific example of decoding.

FIG. 25 is a diagram illustrating a decoding processing procedure.

FIG. 26 is a diagram showing an example of a tree structure of a dictionary.

FIG. 27 is a schematic block diagram of a conventional processing circuit,
(A) is a schematic block diagram of a conventional data compression circuit,
3B is a schematic block diagram of a conventional data restoration circuit.

[Explanation of symbols]

 1 Intermediate Data Converting Means 2 Encoding Means 3 Decoding Means 4 Intermediate Data Inverse Converting Means B1 Buffer Memory B2 Buffer Memory

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Hirotaka Chiba 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited

Claims (7)

[Claims] 1. A data compression circuit for compressing input data input from an information source by encoding the intermediate data converting means (1) for converting the input data into intermediate data and an output code for the intermediate data. Coding means (2) for coding into, the intermediate data converting means (1) and the coding means (2)
And a buffer memory (B1) connected in series, and a data compression circuit. 2. A data compression circuit for compressing input data inputted from an information source by encoding the intermediate data converting means (1) for converting the input data into intermediate data and an output code for the intermediate data. And a buffer memory (B) for temporarily storing the input data.
1), a buffer memory (B1) for temporarily storing the intermediate data, and a buffer memory (B1) for temporarily storing the output code according to the nature of the input data. Buffer memory (B1)
A data compression circuit comprising: 3. A data compression circuit for compressing input data input from an information source by encoding the data, the intermediate data converting means (1) converting the input data into intermediate data, and the intermediate data conversion. A buffer memory (B) provided corresponding to the means (1) for temporarily storing the intermediate data.
1), selection means (11) for selecting the intermediate data output from the plurality of intermediate data conversion means (1), and encoding the intermediate data selected by the selection means (11) into an output code And a run length integrating means (12) for integrating the intermediate data selected by the selecting means (11) and outputting the integrated data to the selecting means (11). Data compression circuit. 4. A data decompression circuit for decompressing an input code input from an information source to decode the input code into intermediate data, and decoding means (3) for converting the intermediate data into output data. Intermediate data inverse conversion means (4) for inverse conversion, and a buffer memory (B2) serially connected to the decoding means (3) and the intermediate data inverse conversion means (4).
And a data recovery circuit comprising: 5. A data restoration circuit for restoring an input code input from an information source by decoding the decoding means (3) for converting the input code into intermediate data, and the intermediate data into output data. Intermediate data inverse conversion means (4) for inverse conversion, and a buffer memory (B) for temporarily storing the input code.
2), a buffer memory (B2) for temporarily storing the intermediate data, and a buffer memory (B2) for temporarily storing the output data according to the nature of the input code. Buffer memory (B2)
And a data recovery circuit comprising: 6. A data decompression circuit for decompressing an input code input from an information source to decode the input code into intermediate data, and decoding means (3) for converting the intermediate data into output data. A plurality of intermediate data inverse conversion means (4) for inverse conversion; a buffer memory (B2) provided corresponding to the plurality of intermediate data inverse conversion means (4) for temporarily storing the intermediate data; A selection means (13) for selecting the output data output from the plurality of intermediate data inverse conversion means (4) and the selection means (13) by integrating the intermediate data output by the decoding means (3). ), And a run length integrating means (14) for outputting to the data restoration circuit. 7. A data compression / decompression device for compressing and decompressing input data and an input code inputted from an information source by encoding and decoding, intermediate data for converting the input data into intermediate data. A conversion means (1), an encoding means (2) for encoding the intermediate data into an output code, and a buffer connected in series to the intermediate data conversion means (1) and the encoding means (2). A data compression circuit including a memory (B1), a decoding means (3) for converting an input code into intermediate data,
A buffer memory (B2) connected in series to the intermediate data inverse conversion means (4) for inversely converting the intermediate data into output data, the decoding means (3) and the intermediate data inverse conversion means (4). A data compression / decompression device comprising: