JPH05175849A - D/a converter - Google Patents

Abstract

PURPOSE:To improve the accuracy and operating speed of the D/A converter. CONSTITUTION:This D/A converter is constituted of a first resistor sequence NT1 having K resistors R11-R1K, second resistor sequence NT2 having L resistors R21-R2L and having the synthesized resistance value roughly equal to the resistance values of the K resistors R11-R1K, first switch means S11-S1K, S21-S2K, S41-S4K and S51-S5K to select (K-1) resistors out of the K resistors R11-R1K according to a digital input signal and to connect a serial circuit composed of these K-1 resistors and the second resistor sequence NT2 between first and second voltages, and second switch means S31-S3L to connect one of the L resistors R21-R2L to the output terminal of the D/A converter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DA converter. More specifically, when the input voltage is Vin, the digital input is X, and the number of bits of the digital input is n, the output voltage Vout is Vout = Vin.X. / 2 ⁿ related to a DA converter. The DA converter is adopted in an output circuit of a digital system, and it is desired that the DA converter be operated at high speed and improved in accuracy in accordance with the request for speeding up from the digital system.

[0002]

2. Description of the Related Art FIG. 9 shows a conventional DA converter composed of a two-stage resistor string voltage dividing type circuit. The resistors R11 to R1K forming a first resistance series circuit NT1 whose resistance values are equal to each other and are connected in series as a whole, and are respectively arranged at both ends of the resistors R11 to R1K of the first resistance series circuit. Upper bit side circuit 10 including switches S11 to S1K and S21 to S2K, and a second resistance string circuit N in which resistance values are equal to each other and are connected in series as a whole.
Of the lower bit side circuit 12 comprising resistors R21 to R2L forming T2 and switches S31 to S3L arranged between one end of each resistor R21 to R2L of the second resistor string circuit NT2 and the output terminal T ₀ . Two resistance voltage dividing type circuits are connected by unit gain buffer amplifiers (buffer amplifiers) A1 and A2. In the figure, V _RP is a positive reference voltage input, V _RN is a negative reference voltage input, V _1i and V _1o are input and output voltages of the buffer amplifier A1, V _2i and V _2O are input and output voltages of the buffer amplifier A2. , Vout is the overall analog output. If the number of bits of the converter is n, then K
・ There is a relationship of L = 2 ⁿ (n is a natural number).

The upper bit side circuit 10 extracts the upper bit side output from the analog input Vin (V _RP -V _RN ). That is, the decoder 30 decodes the upper bits D _{t to} D _{S + 1} of the digital input signal and outputs the switch control signal, and the switches S11 to S are generated by the switch control signal.
1K and S21 to S2K are controlled. As a result, the location where the output voltage in the first resistor string circuit NT1 on the upper bit side is extracted is selected, and the output voltages V _1i and V _{2i of} the bit side circuit 10 are V _1i = (V _RP −V _RN ) · Y / K + V _RN (Y ≦ K:
Y is a natural number) V _2i = (V _RP −V _RN ) · (Y−1) / K + V _RN is obtained. The output voltages V _1i and V _2i are output V _1o and V 2 via the first and second buffer amplifiers A 1 and A 2, respectively.
_It is transmitted as _2O and becomes the input of the lower bit side circuit.

The decoder 40 decodes the lower bits D _{S to} D _O of the digital input signal and switches S31 to S3.
A switch control signal for controlling L is generated. As a result, one switch S3Z is selected, and the lower bit side circuit 1
By selecting the location to retrieve the second output voltage of the second resistor string circuit NT2, the analog output Vout to the output terminal _{T O, Vout = (V 1O} -V 2O) · (Z-1) / L + X 2O (1 ) (Z ≦ L: Z is a natural number) Since the buffer amplifiers A1 and A2 are unity gain amplifiers, V _1O = V _1i and V _2o = V _2i , and if these are substituted into the equation (1), the analog output Vou
t _{is, Vout = (V 1i - V} 2i) · (Z-1) / L + V 2i = (V RP -V RN) · (Y-Y + 1) / K · (Z-1) / L + (V RP -V _RN ) ・ (Y-1) / K + V _RN = (V _RP -V _RN ) ・ 1 / K ・ (Z-1) / L + (V _RP -V _RN ) ・ 1 / K ・ (Y-1) + V _RN = a _{(V RP -V RN) · 1} / K · {Y-1 + (Z-1) / L} + V RN.

[0005] Here, X = (Y-1) · L + Z-1 and the put, the X because it is K · L = 2 ⁿ is a digital input to take 0 ≦ X ≦ 2 ⁿ becomes a value. Thus, the circuit operates from a digital input X analog output Vout, as an n-bit DA converter to obtain _{Vout = (V RP -V RN)} · X / 2 n + V RN.

[0006]

In the conventional circuit, a buffer amplifier as shown in FIG. 10 is used to connect the upper bit side circuit 10 and the lower bit side circuit 12, and the general characteristics of the buffer amplifier are used. Therefore, offset voltage is unavoidable in these. Assuming that the output voltages V _1O and V _2O of the respective buffer amplifiers have offset voltages Δ ₁ and Δ _{2 such} that V _1O = V _1i + Δ ₁ and V _2O = V _2i + Δ ₂ , analog output Vout is Vout = _{(V 1O -V 2O) · (} Z-1) / L + V 2O = (V RP -V RN) · 1 / K · (Z-1) / L + (Δ 1 -Δ 2) · (Z-1) / L + (V _RP −V _RN ) · (Y−1) / K + V _RN + Δ ₂ = (V _RP −V _RN ) · 1 / KL · {(Y−1) L + Z−1} + V _RN + (Δ ₁ −Δ ₂ ) · (Z−1) / Z + Δ ₂ = (V _RP −V _RN ) · X / 2 ⁿ + V _RN + (Δ ₁ −Δ ₂ ) · (Z−1) / L + Δ ₂

Here, if V _RN = 0 is set for simplicity,
Analog output Vout is expressed as _{Vout = V RP · X / 2} n + (Δ 1 -Δ 2) · (Z-1) / L + Δ 2. For example, the selection Y and Z values of the upper bit side circuit 10 and the lower bit side circuit 12 are Y = 1,
When Z = L, that is, X = (1-1) .L + L-1 = L-
When 1, Vout (I) = V RP · (L-1) / 2 n + (Δ 1 -Δ 2) · (L-1) / L + Δ 2 = V RP · (L-1) / KL + Δ 1 ( the L-1) / L + Δ 2 · 1 / L.

Similarly, the value of each selection Y and Z is Y = 2,
When Z = 1, i.e., when X = (2-1) · L + 1-1 = L, Vout (II) = V RP · L / 2 n + (Δ 1 -Δ 2) · (1-1) / L + Δ ₂ = V _RP · L / KL + Δ ₂ . Both analog outputs Vout (I) and Vou
Taking the difference V _diff of _{t (II), V diff =} Vout (II) -Vout (I) = V RP · 1 / KL- (Δ 1 -Δ 2) · (L-1) / L = 1 / L {V _RP · 1 / K− (Δ ₁ −Δ ₂ ) · (L−1)}.

Now, as a numerical example, the power supply voltage is 5 V and X is
8-bit digital signal and both buffers
The drifts of A1 and A2 are + 15mV and -15mV, respectively.
Consider the time of_diffV = 5 [V], K = L = 1
6, Δ₁= 15 [mV], Δ ₂= Substitute -15 [mV]
Then V_diff= 1/16 · {5 / 16- (15 × 10^-3+15 x 10^-3) ・ 15} to V_diffIs obtained as about −8.59 [mV].

However, in the above case, V _diff should be 1 LSB and must be a positive value. Therefore, in the conventional DA converter, the output voltage obviously loses the monotonicity, which is caused by the buffer amplifier. Due to the influence of the offset voltage, accuracy problems occur in the DA converter. Also, due to the frequency characteristics of the buffer amplifier, D
There is also a problem that the operating frequency of the entire A converter circuit, that is, the operating speed is limited.

In view of the problem of the conventional DA converter, the present invention eliminates the use of the buffer amplifier, so that an error due to the offset voltage of the buffer amplifier does not occur in the analog output, and the operating frequency of the amplifier does not change. It is an object of the present invention to provide a DA converter that is highly accurate and can improve the operating speed because it is not limited by frequency characteristics.

[0012]

[Means for Solving the Problems] As shown in FIG.
The converter includes a first resistor string (NT1) having K resistors (R11 to R1K) and L resistors (R21).
To R2L), the combined resistance value of which is approximately equal to the resistance value of the K resistors (NT2) and (K2) of the K resistors according to the digital input signal.
First switch means (S11) for selecting (-1) pieces and connecting a series circuit of the (K-1) pieces of resistors and the second resistor series between a first voltage and a second voltage. ~ S1K, S21
~ S2K, S41 to S4K, S51 to S5K) and second switch means (S31 to S3L) for connecting one of the L resistors to the output terminal of the DA converter.

[0013]

In the DA converter of the present invention, by switching the first and second switch groups, the entire lower bit side circuit forming the second resistor string is converted into the resistance of the upper bit side circuit forming the first resistor string. It can be replaced with one resistor selected as the upper bit of the resistor, and the combined resistance of the second resistor string of the entire lower bit circuit is the same as each resistor of the upper bit circuit. Since it is a resistance value, the potential of the connection part of each resistor of the upper bit side circuit is kept constant regardless of the selection of the upper bit side circuit, and this potential changes depending on the selection of the lower bit side circuit. Therefore, the output locations of the upper and lower bit side circuits can be independently selected according to the upper and lower bits of the digital input. Therefore, it is not necessary to use the buffer amplifier for coupling the resistance voltage dividing circuits on both the upper and lower bit sides, the error caused by the offset voltage generated when the buffer amplifier is used does not occur, and the transmission of the buffer amplifier The operating speed is not limited by the frequency characteristics.

[0014]

The present invention will be further described below with reference to the drawings.
In FIG. 1, K resistors R11 to R1K each having a resistance value equal to each other and each having a first resistance value, and a pair of each of the resistors R11 to R1K arranged in pairs at the ends of each resistor. The switch means S11 to S1K and S21 to S2K constitute each set in the first resistor row, and by connecting each set in series as a whole, K resistors R11 to R are provided.
1K and 2K switches S11 to S1K, S21 to S
A first resistor row NT1 consisting of a first switch group with 2K is formed.

Further, the first resistor group NT1 and a second switch group having switch means S41 to S4K and S51 to S5K connected to both ends of each set of resistors and switches The bit side circuit 110 is configured. The switches of the first switch group do not necessarily have to be inserted at both ends of each of the resistors R11 to R1K, and can be provided only on one side. Further, the second switch groups S41 to S4K and S51 to S5K are not limited to the illustrated mode composed of the respective switch means, but the second switch groups S41 to S4K and S51K to S5K may be configured as a single changeover switch, for example, a multiplexer.

The lower bit side circuit 120 has L resistances R21 each having the same resistance value and having a second resistance value and connected in series to have a first resistance value as a total combined resistance. ~ R2L second resistor row NT2, each of the resistors R21 ~ R2L one end and the output end T ₀ are respectively releasably connected to each other and each of the R resistors R21 ~ R2L form a pair. And a third switch group including switch means S31 to S3L. D of this example
The A converter has a configuration including two resistance voltage dividing type circuits that respectively configure the upper and lower bit side circuits as described above. Like the second switch group, the third switch group can also be configured as a pair of changeover switches.

The DA converter includes decoders 130 and 140.
Have. The decoder 130 receives the upper bits D _{t to} D _{s + 1} of the digital input signal and outputs K decoded signals (switch control signals). This switch control signal is given to the switches S5K to S51 and S4K to S41. One of the K switch control signals is one of the switches S51 to S5K and one of the switches S41 to S4K.
Have a level to turn one on. As shown in FIG. 1, K
Inverters 132 are connected to the decoder 130. The inverter 132 outputs the switch control inversion signal from the decoder 130. The output signal of the inverter 132 is given to the switches S2K to S21 and S1K to S11 to turn on (K-1) of the switches S2K to S21 and (K-1) of the switches S1K to S11.

Decoder 140 receives the lower bits of the digital input signal and produces L decoded signals (switch control signals). These switch control signals are given to the switches S3L to S31. Decoder 140
The L switch control signals generated in step S1 turn on one of the L switches S31 to S3L. A single decoder having the functions of the decoders 130 and 140 may be used. The digital input signal is decoded as follows.

Digital input decode signals D _t , ..., D1, D0 S _y , ..., S1, S0 1, ..., 1, 1 1, ..., 0, 0 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ 0, ... , 0, 1 0, ..., 0, 1 0, ..., 0, 0 0, ..., 0, 0 One of the resistors R11 to R1K is selected by the decoder.
In FIG. 1, resistor R1K-1 is selected. In this state, the switches S1K and S2K-1 are off, and the switch S
4K-1 and S5K-1 are on. Therefore, current flows through the resistor R1K, the first output terminals OT1, R2L to RΔ, and the second output terminals OT2, R1K-1 to RR.

The resistors R1K-1 are resistors R21 to R2L.
Is replaced by a series circuit consisting of. In other words, resistor R
1K-1 is equivalent to a series circuit of resistors R21 to R2L. That is, the resistor R1K-1 corresponds to the resistor R21-
It has a resistance value equal to the combined resistance value of R2L. Of course, the other resistors R1K and R1K-2 to R11 are also
It has a resistance value equal to the combined resistance value of the resistors R21 to R2L. In addition, each resistor R11 to R1K corresponds to each resistor R21.
It can be said that it has a resistance value that is L times R2L.

Switches S11 to S1K, S21 to S2
K, S31 to S3L, S41 to S4K and S51 to S5
Each K has an internal resistance. Resistors R31 to R3L
Must have a resistance value sufficiently larger than this internal resistance. As a result, the internal resistance can be ignored.
First resistor string NT1 forming the upper bit side circuit 110
Is connected to the positive reference voltage input V _RP and the negative reference voltage input V _RN , respectively, and each switch S11 of the first and second switch groups selected by the value of the upper bit.
~ S1K, S21 ~ S2K, S41 ~ S4K, S51 ~
One resistor (R1K-1 in the figure) in the first resistor string is selected by S5K, and at the same time, the entire resistance voltage dividing circuit of the lower bit side circuit 120 is selected by the upper bit side circuit 110. One resistor R1K-1
It is configured to be replaced with. The overall output voltage Vout as a DA converter is determined by the switch means S31 to 3L of the third switch group of the lower bit side circuit 120 selected by the value of the lower bit. If the number of bits of the converter is n, K · L = 2 ⁿ (n is a natural number)
There is a relationship. This operation will be described in more detail below.

Digital input in the upper bit side circuit
The first switch group and the second switch group according to the upper bits of
Switches below the first resistor string circuit NT1
Output voltage to the output side circuit 120
Select the output voltage V₁, V ₂, V₁= (V_RP-V_RN)
・ Y / K + V_RN (Y ≦ K: Y is a natural number) V₂= (V_RP-V_RN) ・ (Y-1) / K + V_RN To get During this time, the switches S1 #,
For S2 # (# is a natural number), only S1Y and S2Y
Open and close others. This makes it possible to
The resistor R1Y on the output side is the resistance of the circuit 120 on the lower bit side.
It will be replaced by the entire equipment row R21 to R2L,
Negative reference power supply V as a whole_RNFrom the side, R11 to R1Y
Via -1, R21 to R2L, R1Y + 1 to R1K
Positive reference power supply V_RPA resistor string circuit leading to is formed.

In the lower bit side circuit 120, the output voltage of the higher bit side 110 is divided by the selection of the switch of the third switch group and output, whereby the analog output Vout, Vout = (V ₁ − V ₂ ) ・ (Z-1) / L + V ₂ (Z ≦
L: Z is a natural number. The analog output Vout Substituting the V ₁ and V _{2 are, Vout = (V 1 - V} 2) · (Z-1) / L + V 2 = (V RP -V RN) · (Y-Y + 1) / K · (Z-1) / L + (V RP -V RN) · (Y-1) / K + V RN = (V RP -V RN) · 1 / K · (Z-1) / L + (V RP -V RN) · 1 / K · (Y- 1) + V RN = (V RP -V RN) · 1 / K · {Y-1 + (Z-1) / L} + a V _RN.

[0024] Here, when put between X = (Y-1) · L + Z-1, because it is K · L = 2 ^n, X is a digital input to take 0 ≦ Z ≦ 2 ⁿ becomes a value. Therefore, this DA converter circuit operates as an n-bit DA converter in which the input is X and the output Vout and Vout = (V _RP −V _RN ) · X / 2 ⁿ + V _RN are obtained.

A circuit diagram of the DA converter of the second embodiment of the present invention is shown in FIG. From the circuit of the first embodiment, one resistor R2 at one end of the second resistor row R21 to R2L.
Instead of L, instead of this, each of the resistors R30 to R30 having a second resistance value as a total combined resistance value, each of which has one of a large number of stepwise different resistance values, is connected in series.
A third resistor string NT3 including R3M is provided, and one resistor R of the third resistor string NT3 is provided.
A fourth switch group consisting of switches S61 to S6M which are paired with M other resistors R31 to R3M except 30 and which are arranged so that the corresponding resistors R31 to R3M can be short-circuited is provided. There is.

Each resistor R30-of the third resistor array NT3
When the resistance value of the first resistor R30 having the smallest resistance value is 1, the resistance value of R3M is the second resistor R31.
Is also 1, the third resistor R32 is 2, the fourth resistor R
33 is 4 different in stages, and the resistance values of the resistors are selected in combination so that any resistance value from 0 to 16 can be selected by short-circuiting or opening via a switch. With this configuration, it is possible to select the number of bits of 4 in the least significant bit side circuit. Further, at the other end of the second resistor row R21 to R2L-1, the same configuration as the third resistor row except for the one resistor R30 is provided, and each of the M series-connected resistors is connected. Resistors R41 to R4M
Is connected to the fourth resistor string NT4 and is paired with the fourth resistor string NT4 to form a corresponding resistor R41.
~ R4M switches S71 to S7 arranged so that they can be short-circuited
A fifth switch group consisting of M is provided. In addition,
If the total number of bits of the digital input of the converter is n, there is a relationship of K · L · M = 2 ⁿ (n is a natural number).

In the circuit of the second embodiment, the circuit including the resistors R11 to R1K of the first resistor string NT1 configures the upper bit side circuit 110 and the second resistor string R21 to R2L.
The circuit including -1 constitutes the middle bit side circuit 120A, and the circuit including the third and fourth resistor rows R30 to R3M and R41 to R4M constitutes the lower bit side circuits 150 and 160, respectively. The lower bit side circuits 150 and 160 are controlled by the switches S61 to S6M and S7 of the fourth and fifth switch groups.
1 to S7M is appropriately short-circuited or opened. Each of the switches S6 # of the fourth switch group and the corresponding fifth switch S7 # are in the short-circuited or open state, while the other is in the open-circuited or short-circuited state, respectively. Resistor row R30 to R3M, R41 to
Control is performed so that the apparent combined resistance value of the entire R4M caused by the opening or the short circuit by these switches becomes the second resistance value.

Specifically, the lower bits D _{0 to} D _S of the digital input signal are directly switched to the switches S61 to S6M, respectively.
To the switch S.
71 to S7M. The second embodiment can convert a digital input signal into an analog output signal more accurately than the first embodiment. Resistors R30-R3M and R41
~ R4M has a resistance value sufficiently smaller than the resistors of the high-order bit side circuit 110 and the middle-order bit side circuit 120A. Therefore, even if there is a deviation (error) from the target resistance value in the resistors R30 to R3M and R41 to R4M, there is substantially no problem. That is, in the combined resistance of the resistor R30 and the M selected resistors, the above error is canceled. Therefore, the above error hardly affects the D / A conversion characteristic. In principle, the switches S31 to S34
It is also possible to control L by the lower bits of the digital input signal and control the switches S61 to S6M and S71 to S7M by the middle bits. However, in this case, the region forming the resistor becomes large as a whole.

FIG. 3 shows a DA converter according to the third embodiment of the present invention. The same reference numerals are attached to the above-mentioned components. As shown in the figure, this D / A converter is characterized by the configuration of the upper bit side circuit 110A. The upper bit side circuit 110A is the upper bit side circuit 11 of FIG.
0 is provided with resistors R51 to R5K. The resistors R51 to R5K are connected in series, and the voltages VRP and VRN are applied across the series circuit. As described below,
The resistors R51 to R5K have the same resistance value, and this resistance value is sufficiently smaller than the resistance values of the resistors R11 to R1K and R21 to R2K.

The use of the resistors R51 to R5K is advantageous in the following points. In reality, the parasitic capacitance is coupled to the node of the circuit. For example, when the switch is turned on / off or when the operation of the D / A converter is started, a certain parasitic capacitance is charged and a certain parasitic capacitance is discharged. It takes some time to charge this parasitic capacitance. In the circuit configuration of FIG. 3, current flows through the series circuit of the resistors R51 to R5K, so that the parasitic capacitance can be charged quickly. In the prior art of FIG. 9, the current flows through the resistors R11 to R1K and the resistors R21 to R2K excluding the selected resistor to charge the parasitic capacitance. Resistor R of FIG.
By using 51 to R5K, the RC time constant of the entire circuit can be reduced.

Furthermore, the DA converter of FIG. 3 can follow changes in the voltages V _RP and V _RN . Depending on the application of the DA converter, the potential difference between the voltages V _RP and V _RN may be intentionally changed. When this potential difference changes, the current flowing through the D / A converter also changes. As described above, since the parasitic capacitance can be charged and discharged at high speed, it is possible to follow the change in the potential difference. Of course, even if this potential difference slightly changes due to a certain factor of the power supply system, it is quickly stabilized.

Further, the resistors R51 to R5K also have a function of eliminating the influence of the on resistance of the switches. Resistor R5
1 to R5K have resistance values sufficiently smaller than the resistance values of the resistors R11 to R1K, and most of the current is
This is because it flows through 1 to R5K. Next, the response characteristics of the first and third implementation differences will be described.

Now, in the circuit of FIG. 1, the error in the output voltage when the internal resistance of the switch is taken into consideration will be calculated. Since the voltage drop in the switch S3 # (# is a natural number) is determined by the output current, it is sufficient to consider the potentials V ₁ and V ₂ at the connection point of the first resistor string NT1 and the second resistor string NT2. .. The resistance value of the first resistor in the circuit of FIG. 1 is R, and the internal resistances of the switches S1 #, S2 #, S4 #, and S5 # are all r.

Here, it can be said that R21 + ... + R2L = R. Of the first resistor array NT1, R1 × (1 ≦ X ≦
The potential when K) is replaced by the second resistor string NT2 is

[0035]

[Equation 1]

It can be expressed as The voltage error that occurs when raising the digital input on the first resistor string NT1 by one bit is:

[0037]

[Equation 2]

[0038] 1/2 the error in the output Vout
Since V _2X −V _1X−1 ≦ 1/2 LSB in order to reduce the LSB or less,

[0039]

[Equation 3]

When L = 16, R ≧ 30r (5) Next, consider the internal impedance of the circuit of FIG. Since the impedance of the second resistor string NT2 is sufficiently lower than that of the first resistor string NT1, an equivalent circuit is approximately obtained as shown in FIG. 4 (A). The maximum internal impedance expected from the output is when X = K / 2, so the impedance Z ₀₁ at this time is

[0041]

[Equation 4]

From (5), if R = 30r, then Z ₀₁ ≈8 Kr (7) The response speed of the circuit of FIG. 1 is approximately governed by the time constant determined by the resistance component (7), the output capacitance, and the like. Furthermore, consider the internal impedance of the circuit of FIG. Similar to the circuit of FIG. 1, the impedance of the second resistor string NT2 can be ignored. Assuming that the resistance value of R5 # is sufficiently lower than that of R1 #, an approximate equivalent circuit is as shown in FIG. Also in this case, the internal impedance Z ₀₂ expected from the output becomes maximum when X = K / 2,

[0043]

[Equation 5]

For example, even if r≈P, Z ₀₂ is sufficiently smaller than Z ₀₁ , that is, the response speed of the circuit is faster. Each of the decoders in the above embodiment is configured as shown in FIG. 5, for example. The illustrated decoder is a 4-bit decoder, and the 4-bit inputs D0 to D3 are S0.
It is developed in 16 ways from 0 to S15. As shown, the decoder has an inverter 181 and an AND gate 182. The decoder is not limited to this.

Each switch in the above-mentioned embodiment is, for example, as shown in FIG.
It is configured like. The illustrated switch is a transfer gate having two transistors 183 and 184 and one inverter 185. The switch control signal (here, S _G for convenience) is directly applied to the gate of the transistor 184, and is also applied to the gate of the transistor 183 through the inverter 185. When the switch control signal S _G is high (H), it conducts between S _{1 and} S ₂ ,
During S ₁ -S ₂ when row (L) is in the open. The switch is not limited to that shown in FIG.

FIG. 7 is a diagram showing a fourth embodiment of the present invention. The fourth embodiment corresponds to a combination of the second embodiment of FIG. 2 and the third embodiment of FIG. Specifically, FIG.
The first resistor array NT1A in FIG.
K is applied to the first resistor array NT1 in FIG. This fourth embodiment combines the effects of the second and third embodiments.

FIG. 8 shows a modification of the first embodiment shown in FIG. In the modification of FIG. 8, switches (only switches S11 to S1K in the illustrated example) are provided only at one end of each of the resistors R11 to R1K. With this configuration, the same effect as the configuration of FIG. 1 can be obtained. Note that, for example, in the configuration described above, in which the combined resistance value of the second resistor row NT2 is the same as the resistance value of each resistor of the first resistor row NT1, both resistance values are substantially the same. Is the same, and does not necessarily require a strict match, but a match required to obtain the required accuracy of the DA converter is sufficient.

Further, the configuration of each switch group can be constituted by, for example, an analog switch, and various modifications can be made. Naturally, a DA converter which is modified well known from the circuit diagram of the embodiment is within the scope of the present invention. included.

[0049]

As described above, according to the DA converter of the present invention, by selecting the switch group defined by the upper and lower bits, the output of the resistance voltage dividing type circuit of the upper and lower bits can be mutually controlled. It is not necessary to use a buffer amplifier at the time of coupling because it is possible to couple both resistance voltage divider type circuits without affecting the output voltage, and the output error and operating frequency limitation due to the buffer amplifier offset voltage are eliminated. The remarkable effect is that the accuracy and operating speed of the DA converter can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a DA converter according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a DA converter according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a DA converter according to a third embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of the first and third embodiments of the present invention.

FIG. 5 is a circuit diagram of a decoder used in each embodiment of the present invention.

FIG. 6 is a circuit diagram of a switch used in each embodiment of the present invention.

FIG. 7 is a circuit diagram of a DA converter according to a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram of a modified example of the first embodiment of the present description.

FIG. 9 is a circuit diagram of a conventional DA converter.

FIG. 10 is a circuit diagram of a buffer amplifier used in a conventional DA converter.

[Explanation of symbols]

R11 to R1K each resistor of the first resistor string R21 to R2L each resistor of the second resistor string R30 to R3M each resistor of the third resistor string R41 to R4M each of the fourth resistor string Resistors S11 to S1K, S21 to S2K Each switch means of the first switch group S41 to S4K, S51 to S5K Each switch means of the second switch group S31 to S3L Each switch means of the third switch group S61 to S6M Each switch means of the fourth switch group S71 to S7M Each switch means of the fifth switch group

Claims (4)

[Claims] 1. A first resistor string (NT1) having K resistors (R11 to R1K) and L resistors (R21 to R2L) having a combined resistance value of K resistors. A second resistor string (NT2) substantially equal to the resistance value of the resistors, and (K-1) of the K resistors are selected according to the digital input signal, and the (K-1) is selected. First switch means (S11-S1K, S) for connecting a series circuit of a plurality of resistors and the second resistor string between first and second voltages.
21-S2K, S41-S4K, S51-S5K) and second switch means (S31-S3L) for connecting one of the L resistors to the output terminal of the DA converter. Characteristic DA converter. 2. One of the L resistors is connected in series, and a plurality of resistors (NT3) forming a third resistor string (NT3) connected in series to the second resistor string ( R30 to R3
M), the DA converter includes a fourth resistor string (NT4) having a plurality of resistors (R41 to R4M) connected in series to the second resistor string, and selectively according to a digital input signal. And a third switch (S61 to S6) for short-circuiting the resistors of the third and fourth resistor rows.
M, S71 to S7M). 3. The DA converter includes a third resistor string having K resistors connected in series, and the first and second voltages are applied to the third resistor string. The DA converter according to claim 1, wherein 4. One of the L resistors is connected in series, and a plurality of resistors (NT3) forming a third resistor string (NT3) connected in series with the second resistor string (NT3). R30 to R3
M), the DA converter includes a fourth resistor string (NT4) having a plurality of resistors (R41 to R4M) connected in series to the second resistor string, and selectively according to a digital input signal. And a third switch (S61 to S6) for short-circuiting the resistors of the third and fourth resistor rows.
M, S71 to S7M), and a fifth resistor string having K resistors connected in series, and the first and second voltages are applied to the third resistor string. The DA converter according to claim 1, wherein: