JPH05175752A - Differential voltage comparator - Google Patents

Abstract

PURPOSE:To amplify an input voltage up to a logic level without increasing the circuit scale even when a difference between two input voltages to be compared by providing a differential amplifier circuit, a nonlinear differential amplifier circuit and a voltage comparator circuit with a latch on the subject comparator. CONSTITUTION:Two voltages to be compared are fetched by an input circuit 1 and two outputs of the input circuit 1 are amplified by a degree with a differential amplifier circuit 2 receiving them through capacitors C1, C2. Then the two outputs of the differential amplifier circuit 2 are inputted to a nonlinear differential amplifier circuit 3 via capacitors C3, C4, in which they are largely amplified by the positive feedback effect suppressed from a positive feedback circuit. The two outputs are amplified up to a logic level by a voltage comparator circuit 4 with a latch.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential voltage comparator for comparing two voltages, and more particularly to a differential voltage comparator capable of amplifying to a logic level even if the difference between two analog voltages is small. Regarding

[0002]

2. Description of the Related Art A conventional differential voltage comparator, for example, "Th
e Journal OF Solid-State
Circuits, Vol. 24, No. 1 FEBR
11 shows an example shown in UARY 1989; pp 241-249 ". Here, a differential amplifier circuit having the same configuration is connected by three capacitor couplings to amplify the input voltage difference to a logic level. hand,
Realizes a differential voltage comparator.

In FIG. 11, MOSFETs QF1 and QF are provided.
2, QF3, QF4, QF5, and QF6 are for putting the respective differential amplifier circuits 5 in a reset state, and MOS
A pulse FB0 and a MOSFET are applied to the FETs QF1 and QF2.
The pulse FB1 is input to QF3, QF4, QF5, and QF6. The pulse FB0 and the pulse FB1 simultaneously become high level to reset each differential type amplifier circuit 5, and the pulse FB0 becomes low level before FB1 to activate the differential type amplifier circuit in the first stage, and sequentially in the subsequent stages. The differential amplifier circuit is put into an operating state to stabilize the entire circuit.

FIG. 12 is a circuit diagram of the differential amplifier circuit of FIG.
Shown in. + V input to MOSFETs Q11 and Q12
in and -Vin are MO in which the gate and the drain are connected
Load circuit composed of SFETs QL1 and QL2, load circuit composed of MOSFETs QL3 and QL4 whose gates are supplied with a constant voltage, MOS whose gate is supplied with a constant voltage
Differential amplification is performed by a cascode circuit composed of FETs QC1 and QC2 and a constant current circuit of a MOSFET Q9 whose gate is supplied with a constant voltage, and + Vout and −Vout are output from the drains of QC1 and QC2. In addition, QC
1. MOSFET QR1 connected to the drain of QC2
Constitutes a reset circuit, and is reset by short-circuiting between QC1 and QC2 by a reset signal applied to the gate.

[0005]

However, if the difference between the two input voltages to be compared is small only by connecting about 2-3 such differential type amplifier circuits, the input voltage difference is reduced to the logic level. It cannot be amplified, and if it is attempted to amplify to a logic level, it is necessary to add a differential amplifier circuit, which causes a problem that the circuit scale becomes large.

The present invention is intended to solve the above-mentioned problems, and even if the difference between two input voltages to be compared is small,
An object of the present invention is to provide a differential voltage comparator that can amplify an input voltage to a logic level without increasing the circuit scale.

[0007]

SUMMARY OF THE INVENTION Therefore, according to the present invention, in a differential voltage comparator for comparing two voltages and amplifying a voltage difference, an input circuit for taking in two voltages to be compared, and the input circuit. Two outputs of the differential amplifier circuit are input via the first capacitor C1 and the second capacitor C2, and a switching circuit is connected between the input and output, and two outputs of the differential amplifier circuit are the third output. Non-linear differential amplifier circuit which is input via the capacitor C3 and the fourth capacitor C4, and a switching circuit is connected between the input and output, and a differential amplifier circuit to which two outputs of the non-linear differential amplifier circuit are input. And a latched voltage comparison circuit having a latch circuit formed of a positive feedback circuit, to which the output of the differential amplifier circuit is input.

Further, according to the present invention, at least one of the differential amplifier circuit, the non-linear differential amplifier circuit, and the voltage comparison circuit with a latch is of a self-bias type, which does not require an external bias voltage and simplifies the circuit configuration. It is characterized by

[0009]

In the differential voltage comparator of the present invention, the two voltages to be compared are fetched by the input circuit, and the two outputs of this input circuit are the first capacitor C1 and the second capacitor for offset cancellation. The signal is amplified to some extent by the differential amplifier circuit input via C2. The capacitors C1 and C2 are configured to store electric charges according to an offset amount due to variations in circuit elements. Next, the two outputs of the differential amplifier circuit are input to the non-linear differential amplifier circuit via the third capacitor C3 and the fourth capacitor C4 for offset cancellation, and are greatly increased by the suppressed positive feedback effect of the positive feedback circuit. Amplify. The positive feedback circuit of the non-linear differential amplifier circuit applies positive feedback to one output that is differentially amplified and the other output, and performs voltage amplification toward the saturation voltage. The two outputs of this non-linear differential amplifier circuit are amplified to a logic level by a voltage comparison circuit with a latch. The voltage comparator circuit with a latch consists of a differential amplifier circuit and a latch circuit that constitutes a positive feedback circuit.When the differential amplifier circuit has amplified the voltage to the saturation voltage because it has a large input voltage difference, it is held and output as is. If the amplification is not sufficient because the voltage difference is small, the positive feedback circuit of the latch circuit amplifies and outputs to the saturation voltage. Even if the difference between the two input voltages to be compared is small, it is amplified to the logic level. Can be taken out.

Further, according to the present invention, each element constituting the differential amplifier circuit, the non-linear differential amplifier circuit, and the voltage comparison circuit with a latch may be bias-controlled by an external voltage or self-biased. By using the self-bias type, the bias voltage generating circuit can be eliminated.

[0011]

1 is a block diagram of an embodiment of a differential type voltage comparator of the present invention. In FIG. 1, reference numeral 1 denotes an input circuit that takes in two voltages Vin and Vref to be compared,
2 indicates that the two outputs of the input circuit are the first capacitor C1.
And a differential amplifier circuit 3 which is input via the second capacitor C2, and 3 is a non-linear differential amplifier in which the two outputs of the differential amplifier circuit are input via the third capacitor C3 and the fourth capacitor C4. A circuit 4 is a voltage comparison circuit with a latch to which the two outputs of the non-linear differential amplifier circuit are input and which outputs Vout1 and Vout2.

First, the operation of the differential voltage comparator of FIG. 1 will be briefly described with reference to FIG. FIG. 6 shows operation waveforms, and Vi
n, Vref, V1, V2, V3, V4, Vout1,
Vout2 is the voltage at each terminal shown in FIG. 1, and the timing pulses PH1 and PH2 are non-overlapping pulses. 6A shows the timing pulses PH1 and PH2. FIG. 6B shows the input voltage Vin and the reference voltage Vref.
(C) is a diagram showing output voltages V1 and V2 of the differential amplifier circuit,
FIG. 6D shows output voltages V3 and V4 of the non-linear differential amplifier circuit.
FIG. 6E is a diagram for explaining output voltages Vout1 and Vout2 of the voltage comparison circuit with a latch.

As shown in FIG. 6B, from time t0 to t
Up to 1, two input voltages Vin, Vre to be compared
The difference of f is large in Vin >> Vref, and from time t1 to t2
Up to Vin> Vref, after time t2 Vin <Vr
Two input voltages Vin, Vref to be compared at ef
Is small. The output voltages V1 and V2 of the differential amplifier circuit when such an input voltage is applied are amplified to a certain degree during the period PH2 as shown in FIG. 6C. And FIG.
As shown in (d), it is further amplified by the non-linear differential amplifier circuit, and when Vin >> Vref, it becomes a saturation voltage,
Further, even when the difference between Vin and Vref is small, positive feedback is performed to amplify the voltage, and the voltages V3 and V4 are output. When the timing pulse PH1 is at a high level, the differential amplifier circuit and the non-linear differential amplifier circuit are in a reset state, and the output voltages V1, V2, V3, and V4 each show a certain constant voltage, and are offset as described later. Cancellation is supposed to be done. Next, the voltage of the non-linear differential amplifier circuit is input to the voltage comparator with a latch, and when the voltage is amplified to the saturation voltage, its value is held as it is. It is amplified to the saturation voltage, held, and output as Vout1 and Vout2.

Next, each circuit of the differential type voltage comparator of the embodiment will be described in order. (1) Input Circuit FIG. 2 is a diagram showing an embodiment of the input circuit 1 shown in FIG. N-type MOSFET (hereinafter referred to as "NMOS") QT
1, QT2 outputs the voltage of one input terminal Vref to both output terminals by the first timing pulse PH1. The NMOSs QT3 and QT4 output the voltages of the input terminals Vin and Vref, respectively, in response to the second timing pulse PH2. Therefore, the first timing pulse PH1
Is high level, the voltage of the input terminal Vref is taken in as a reference voltage, and when the second timing pulse PH2 is high level, the voltages of the input terminals Vin and Vref are taken in.

(2) Differential Amplifier Circuit FIG. 3 is a diagram showing an embodiment of the differential amplifier circuit 2 shown in FIG. The input terminals + Vin and -Vin are connected to the respective gates of the NMOS QI1 and QI2 in the differential input stage. The NMOS QC1 and QC2 are cascode stages, and their gates are connected to the terminal BIASc. Also, QC
1, the drain of QC2 is the output terminal -Vout,
It is connected to + Vout. P-type MOSFETs (hereinafter referred to as "PMOS") QL1, QL2, QL3, QL4
Constitutes a load circuit, and the power supply voltage V is applied to each source.
DD is given.

The gates and drains of QL1 and QL2 are short-circuited, and the gates of QL3 and QL4 are connected to the terminal BIASp. An NMOS Q9 as a constant current source for supplying a current is connected to the common source of QI1 and QI2. The gate of Q9 is terminal B
It is connected to IASn and the substrate potential is applied to the source. NMOS QF1 and QF2 are timing pulses PH
1 is a switch for short-circuiting the drain of QC1 and the gate of QI1, and the drain of QC2 and the gate of QI2. Also, the terminals BIASc, BIASp,
BIASn is supplied with a constant bias voltage, and QL3, QL4, QC1, QC2, and Q9 are controlled to have predetermined impedance values.

When the timing pulse PH1 is at a high level, the drain of QC1 and the gate of QI1 and the drain of QC2 and the gate of QI2 are short-circuited by QF1 and QF2, respectively, and the differential amplifier circuit is in the reset state, and the voltage at the input terminal + Vin. Is QL1, QL3, QF1, QC
It becomes -Vout determined by 1, QI1, Q9, and the voltage of the input terminal -Vin is QL2, QL4, QF2, QC2, Q.
It becomes + Vout determined by I2 and Q9. At this time, if there is no variation in the transistors of the differential amplifier circuit, -Vout
6 and + Vout have the same constant value as shown in FIG. 6C, but if there are variations in the transistors, a certain constant voltage corresponding to the offset amount is output to the output terminal −Vout, the input terminal + Vin, and the output terminal. It outputs to + Vout and the input terminal -Vin, respectively.

When PH1 is at a high level, the terminals on the input circuit side of the capacitors C1 and C2 shown in FIG. 1 are connected to the input circuit QT1 and QT2 shown in FIG.
ref is given to each. Therefore, charges corresponding to the offset amount of the differential amplifier circuit are stored in the capacitors C1 and C2. Then, the timing pulse P
When H1 goes low, the drain of QC1 and QI1
, The drain of QC2 and the gate of QI2 are opened by QF1 and QF2, respectively, and the differential amplifier circuit becomes active.

Next, when the timing pulse PH2 becomes high level, Vin, Vr fetched from the input circuit 1
The voltage of ef appears at the input terminals + Vin and -Vin via the capacitors C1 and C2 in which electric charges corresponding to the offset amount are stored, and the offset is canceled. In the present embodiment, since the voltage of Vref is constant, an offset of the differential circuit and a potential difference obtained by adding | Vref-Vin | Output terminal + Vou as shown in FIG.
t, output to -Vout.

(3) Non-Linear Differential Amplifier Circuit FIG. 4 is a diagram showing an embodiment of the non-linear differential amplifier circuit 3 of FIG. The NMOS QI1 and QI2 are differential input stages, and their gates are connected to the input terminals + Vin and -Vin, respectively. The drains are output terminals -Vout,
It is connected to + Vout. PMOS QL1, QL
2, QL3 and QL4 are load circuits, and the power supply voltage VDD is applied to their sources. Also, QL1, Q
The gate and drain of L2 are short-circuited, and QL
3, QL4 has its gate connected to the terminal BIASp. The PMOS QP1 and QP2 are positive feedback circuits, the gates and drains of which are cross-connected, and the power supply voltage VDD is applied to their sources.

An NMOS Q9 is connected as a constant current source for supplying a current to the common source of QI1 and QI2, the gate thereof is connected to the terminal BIASn, and the substrate potential is given to the sources. NMOS QF1, QF
2 is QI1 according to the timing pulse PH1.
Is a switch for short-circuiting the drain and the gate of QI2 and the drain and the gate of QI2. Also, the terminals BIASp, BI
A constant bias voltage is applied to each ASn, and Q
L3, QL4, and Q9 are controlled to have a predetermined impedance value.

When the timing pulse PH1 is at high level, the drain and gate of QI1 and the drain and gate of QI2 are short-circuited by QF1 and QF2, respectively, and the non-linear differential amplifier circuit is reset (FIG. 6 (d)).
Then, as in the case of FIG. 3, a constant voltage corresponding to the offset amount due to the variation of the transistors of the nonlinear differential amplifier circuit is output to the output terminal −Vout, the input terminal + Vin and the output terminal + Vout, and the input terminal −Vin, respectively. .. At this time, the voltage at the time of resetting the differential amplifier circuit is applied to the terminals of the capacitors C3 and C4 on the side of the differential amplifier circuit 2. Therefore, the offset amount of the differential amplifier circuit and the offset of the nonlinear differential amplifier circuit are applied. Electric charges corresponding to the amount are stored in the capacitors C3 and C4.

When the timing pulse PH1 becomes low level, the drain and gate of QI1 and the drain and gate of QI2 are opened by QF1 and QF2, respectively, and the nonlinear differential amplifier circuit 3 becomes active. Then, the difference between the output voltage of the differential amplifier circuit 2 and the output voltage of the differential amplifier circuit 2 at the time of reset appears at the input terminals + Vin and -Vin via the capacitors C3 and C4, respectively. These are transmitted to the gates of QI1 and QI2, respectively,
It is amplified and output to the output terminals + Vout and -Vout. As shown in FIG. 6D, when Vin >> Vref or Vin << Vref, the output of the nonlinear differential amplifier circuit 3 is immediately saturated, and when Vin> Vref or Vin <Vref, the output of the nonlinear differential amplifier circuit. Is gradually amplified by the functions of the suppressed positive feedback circuits QP1 and QP2.

That is, the drain voltages of QI1 and QI2 have a relationship that when one becomes high level, the other becomes low level, and when the drain voltage of QI2 is low level, QP1 becomes low impedance and -Vout. Is amplified to the power supply voltage VDD, while QI1 is high level and QP2 is high impedance, so + Vo
ut is maintained at a low level. When the voltage of the drain of QI1 is low level, QP2 has a low impedance and + Vout is amplified to the power supply voltage VDD. At this time, QP1 has a high impedance, so −
Vout is maintained at low level. Thus, the non-linear differential amplifier circuit amplifies the difference voltage between Vin and Vref to a saturation voltage or a value close to the saturation voltage.

(4) Voltage Comparison Circuit with Latch FIG. 5 is a diagram showing an embodiment of the voltage comparison circuit 4 with latch in FIG. Since the differential voltage between Vin and Vref is amplified to a sufficiently large voltage by the non-linear differential amplifier circuit 3 shown in FIG. 4, the offset amount is canceled between the non-linear differential amplifier circuit 3 and the latched voltage comparison circuit 4. The capacitor to do this is not inserted. Therefore, a switch for short circuit is not provided between the input and output of the voltage comparison circuit with a latch, and auto reset is not applied. NMOS QI1, QI
2 is a differential input stage, and each gate has an input terminal + Vi
It is connected to n and -Vin. NMOS QC1, QC
2 is a cascode stage, the gate of which is connected to the terminal BIASc. The drains are output terminals -Vou, respectively.
t, + Vout.

PMOS QL1, QL2, QL3, QL4
Is a load circuit, and the source of each is connected to the drain of the PMOS QS1. The gates and drains of QL1 and QL2 are short-circuited, and the gates of QL3 and QL4 are connected to the terminal BIASp. Q above
PH2 #, which is an inversion pulse of the timing pulse PH2, is applied to the gate of QS1 which supplies the power supply voltage to the common source of L1, QL2, QL3, and QL4.

PMOS QP1 and QP2 are positive feedback circuits Q
C1 and QC2 are connected to their respective drains, their gates and drains are cross-connected, and their respective sources are P
It is connected to the drain of MOSQS2. QP1, Q
PH1 # which is an inversion pulse of the timing pulse PH1 is applied to the gate of QS2 which supplies the power supply voltage to the common source of P2.

An NMOS Q9 is connected as a constant current source for supplying a current to the common source of QI1 and QI2, the gate of Q9 is connected to the terminal BIASn, and the substrate potential is applied to the sources. Also, the terminal BIAS
A constant bias voltage is applied to each of c, BIASp, and BIASn, and QL3, QL4, QC1, QC2,
Q9 is controlled to have a predetermined impedance value.

When the timing pulse PH2 is at high level, QS1 is turned on, and the load circuits QL1, QL2, QL.
3 and QL4, the output difference of the non-linear differential amplifier circuit 3 is amplified and appears at the output terminals -Vout and + Vout. At this time, the positive feedback circuit is not working because QS2 is off.

When the timing pulse PH1 is at high level, QS2 is turned on, the positive feedback circuits QP1 and QP2 are activated, and the voltage output when PH2 is at high level is amplified to the logic level and held. As shown in FIG. 6E, when Vin >> Vref or Vin << Vref, the output of the non-linear differential amplifier circuit 3 has already been amplified to the logic level, and therefore is held as it is in the positive feedback circuit. When Vin> Vref or Vin <Vref, the differential amplification output of the voltage comparison circuit with a latch is not yet amplified to the logic level, so it is amplified and held to the logic level. That is, when the drain of QC1 is low level, QP1 becomes low impedance,
The voltage of −Vout is amplified to the power supply voltage VDD, and when QC2 is at a low level, QP2 has a low impedance and + Vout is amplified to the power supply voltage VDD and held. In this way, the input voltages Vin, Vre
The comparison result can be amplified to the logic level and output regardless of the voltage difference of f.

FIG. 7 is a diagram showing another embodiment of the input circuit. The input circuit of this embodiment is such that Vin-Vref is used as two inputs of the differential amplifier circuit. Figure 7
, The NMOSFETs QT2 and QT3 are supplied to the input terminals Vin and Vref by the first timing pulse PH1.
Is output to the respective output terminals + Vout and -Vout, and the NMOS QT1 outputs the second timing pulse PH.
2, the input terminals Vin and Vref are short-circuited. Therefore, when the first timing pulse PH1 is at the high level, the voltage of the input terminal is taken in, and when the second timing pulse PH2 is at the high level, each output terminal + Vou.
A difference between Vin and Vref appears in t and -Vout, and Vin-Vref is the input signal of the next stage. In the case of this input circuit, the number of transistors can be reduced by one compared with the case of FIG. Further, in the case of FIG. 2, it is premised that the same voltage is applied as Vref during the period of PH1 and PH2, but in the case of the present embodiment, the voltage is read only at PH1.
There is an advantage that the same voltage needs to be applied only during this period.

FIG. 8 is a diagram showing another embodiment of the differential amplifier circuit. In the present embodiment, the load circuit is configured by omitting QL3 and QL4 controlled by an external bias voltage in the differential amplifier circuit shown in FIG. 3 and self-biasing with the differentially amplified output. Also, the cascode stage QC1, QC
The control voltage of 2 is used as the power supply voltage, and the constant current circuit has two NMOSFETs in which the drain voltages of the differential input stages whose phases are inverted are added to the gates by short-circuiting their drain sides.
It is a self-biased differential amplifier circuit configured as follows.

In FIG. 8, NMOS QI1 and QI2 are differential input stages, and their gates are input terminals + Vin and −Vin.
It is connected to Vin. The NMOS QC1 and QC2 are cascode stages, the power supply voltage VDD is applied to their gates, and their drains are output terminals −Vout and + Vout, respectively.
It is connected to the. The PMOS QL1 and QL2 are load circuits, each of which has a source to which a power supply voltage is applied and whose gate and drain are short-circuited to function as a diode. NMs whose drains are short-circuited as a constant current source for supplying current to the common source of QI1 and QI2
OSQS1 and QS2 are connected. Also, QS1,
The gate of QS2 is connected to the drains of QI1 and QI2, respectively, and the substrate potential is applied to the sources. NM
OSQF1 and QF2 are connected to the drain of QC1, the gate of QC1 and QC according to the timing pulse PH1.
It is a switch for short-circuiting the drain of 2 and the gate of QI2.

When the timing pulse PH1 is at a high level, the drain of QC1 and the gate of QI1 and the drain of QC2 and the gate of QI2 are short-circuited by QF1 and QF2, respectively, and the differential amplifier circuit is reset. Then, a certain voltage corresponding to the offset amount due to the variation of the transistors of the differential amplifier circuit is output terminal -Vou.
t, input terminal Vin and output terminal + Vout, input terminal −
Output to Vin respectively. At this time, voltages of Vin and Vref are given to the respective terminals on the input circuit side of the capacitors C1 and C2 by the input circuit, and the charges corresponding to the offset amount and the input voltage of the differential amplifier circuit are respectively supplied. It can be stored. When the timing pulse PH1 goes low, the drain of QC1 and the gate of QI1, Q
The drain of C2 and the gate of QI2 are QF1 and QF, respectively.
It is opened by F2, and the differential amplifier circuit becomes active. The self-biased differential amplifier circuit of this embodiment is configured so that no gate control voltage is applied from the outside, and the constant current source is configured by short-circuiting the drains of NMOS QS1 and QS2,
Since the voltages of the drains of QI1 and QI2 are related to the gates of QS1 and QS2, in which the other goes low when one goes high, the total value of the currents flowing through QS1 and QS2 is constant.

When the timing pulse PH2 becomes high level, the voltage difference between Vin and Vref taken from the input circuit 1 when PH1 is high level causes the capacitors C1 and C2 in which electric charges corresponding to the offset amount are stored.
Through the input terminals + Vin and −Vin, respectively. In this embodiment, an offset of the differential circuit and a potential difference of | Vref−Vin | are generated between the input terminals + Vin and −Vin, and the potential difference is transmitted to the gates of QI1 and QI2, amplified, and the offset is canceled. It is output to the output terminals + Vout and -Vout.

FIG. 9 is a diagram showing another embodiment of the non-linear differential amplifier circuit. In this embodiment, the QL controlled by a bias voltage from the outside with respect to the nonlinear differential amplifier circuit shown in FIG.
3, QL4 is omitted, a load circuit is configured so as to be self-biased by a differentially amplified output, a positive feedback circuit for amplifying a differential output voltage is connected, and a cascode QC
1. The control voltage of QC2 is used as the power supply voltage, and the constant current circuit has two NMOs in which the drain side of each other is short-circuited and the drain voltage of the differential input stage whose phase is inverted is added to the gate.
It is a self-biased non-linear differential amplifier circuit configured by SFET. In this embodiment, the cascode stage QC
1 and QC2 are provided to prevent the gate inputs of QI1 and QI2 from being affected by the voltage fluctuation on the output side and to reduce the output capacitance of the nonlinear differential amplifier circuit.

The NMOS QI1 and QI2 are differential input stages,
Each gate is connected to input terminals + Vin and -Vin, and its drain is connected to output terminals -Vout and + Vout via cascodes QC1 and QC2, respectively. The PMOS QL1 and QL2 are load circuits, each of which is supplied with a power supply voltage and has its gate and drain short-circuited to function as a diode. PM
OSQP1 and QP2 are positive feedback circuits, the gates and drains of which are cross-connected, and the power supply voltage is applied to their sources.

Further, as constant current sources for supplying currents to the common source of QI1 and QI2, NMOS QS1 and QI
S2 is connected, and the gates of QS1 and QS2 are Q
It is connected to the drains of I1 and QI2, and the substrate potential is applied to the sources. The NMOSs QC1 and QF2 are switches for short-circuiting the drain of QC1 and the gate of QI1, and the drain of QC2 and the gate of QI2, respectively, according to the timing pulse PH1.

When the timing pulse PH1 is at the high level, the drain of QC1 and the gate of QI1, the drain of QC2 and the gate of QI2 are short-circuited by QF1 and QF2, respectively, and the self-biased nonlinear differential amplifier circuit is reset. Then, a certain voltage corresponding to the offset amount due to the variation of the transistors of the self-biased nonlinear differential amplifier circuit is output terminal −Vout and input terminal + V.
in, the output terminal + Vout, and the input terminal -Vin, respectively. At this time, capacitors C3 and C4 of FIG.
The voltage at the time of resetting the differential amplifier circuit is applied to the terminals on the side of the differential amplifier circuit of, and therefore, the charge corresponding to the offset amount of the differential amplifier circuit and the offset amount of the self-biased nonlinear differential amplifier circuit, respectively. Is stored.

When the timing pulse PH1 goes low, QF1 and QF2 are drained between the drain of QC1 and the gate of QI1 and between the drain of QC2 and the gate of QI2, respectively.
Is opened, and the non-linear differential amplifier circuit becomes active. And the output voltage of the self-biased differential amplifier circuit,
The difference between the output voltage of the differential amplifier circuit at the time of resetting and the input terminal + Vi via the capacitors C3 and C4, respectively.
Appear in n, -Vin. These are QI1 and QI, respectively.
It is transmitted to the gate of I2, amplified, and output terminal + Vou
t, output to -Vout. When Vin >> Vref or Vin << Vref, the output of the self-biased nonlinear differential amplifier circuit is immediately saturated. Vin> Vre
When f or Vin <Vref, the output of the self-biased nonlinear differential amplifier circuit is suppressed, and the positive feedback circuit QP1,
It is gradually amplified by the function of QP2. That is, the drain voltages of QI1 and QI2 have a relationship in which one is at a high level and the other is at a low level. Up to the high level, while QC1 is at the high level and QP2 is at the high impedance, + Vout is maintained at the low level. When the drain side voltage of QC1 is low level, QP2 becomes low impedance and + Vout is amplified to the power supply voltage VDD. At this time, QP1 is high impedance and -Vout is maintained at low level. In this way, the input voltage difference is amplified to a sufficient magnitude.

FIG. 10 is a diagram showing another embodiment of the voltage comparison circuit with a latch. In the present embodiment, in contrast to the voltage comparison circuit with a latch shown in FIG. 5, the differential amplifier circuit omits QL3 and QL4 controlled by a bias voltage from the outside, and self-biases with a differentially amplified output. To form a load circuit, and to prevent constant current from flowing by controlling QC1 and QC2 of the cascode stage with timing pulses, and the constant current circuit short-circuits the drain sides of each other and inverts the phase to the gate. It is configured by two NMOSFETs to which the drain voltage of the differential output stage is added, and the latch circuit operates when the differential amplifier circuit does not operate to separate the constant current source from the differential amplifier circuit. It was done like this.

The NMOS QI1 and QI2 are differential input stages,
Each gate is connected to the input terminals + Vin and -Vin. The NMOS QC1 and QC2 are cascode stages, and the gate is supplied with the timing pulse PH2. The drains are output terminals -Vout and + Vout, respectively.
It is connected to the. The PMOS QL1 and QL2 are load circuits, the respective sources are connected to the drain of the PMOS QS1, and the gate and the drain are short-circuited. PH2 #, which is an inversion pulse of the timing pulse PH2, is applied to the gate of QS1 which supplies the power supply voltage to the common source of QL1 and QL2. Also, QI1, QI
NMOSs QS4 and QS5 are connected as constant current sources for supplying a current to the two common sources, the gates are connected to the drains of QC1 and QC2, respectively, and the substrate potential is applied to the sources.

PMOS QP1, QP2, NMOS QP
3 and QP4 are positive feedback circuits, which form a latch circuit. QP1 and QP2 are connected to the respective drains of QC1 and QC2, their gates and drains are cross-connected, and their respective sources are connected to the drain of PMOS QS2. PH1 #, which is an inversion pulse of the timing pulse PH1, is applied to the gate of QS2, which supplies the power supply voltage to the common source of QP1 and QP2.

QP3 and QP4 are QC1 and
It is connected to the drain of QC2, its gate and drain are cross-connected, and each source is connected to the drain of NMOS QS3. A timing pulse PH1 is applied to the gate of QS3 which applies the substrate potential to the common source of QP3 and QP4.

When the timing pulse PH2 is at the high level, QS1, QC1 and QC2 are turned on, and the load circuit QL.
The input voltage difference is amplified by the action of 1 and QL2 and appears at the output terminals −Vout and + Vout.

When the timing pulse PH1 is at high level, QS2 and QS3 are turned on, and the positive feedback circuits QP1 and QP are provided.
The functions of P2, QP3, and QP4 amplify and hold the voltage output when PH2 is at a high level up to the logic level. That is, Vin >> Vref or Vin <<
At Vref, the output of the differential amplification section has already been amplified to the logic level, and is therefore retained in the latch circuit. Vin> Vref or Vin <Vref
At this time, the output of the differential amplifying portion is not yet amplified to the logic level, so the latch circuit amplifies and holds the logic level. That is, in the latch circuit, QC
When the drain of 1 is low level, QP1 becomes low impedance, the voltage of −Vout is amplified to the power supply voltage VDD, and when QC2 is low level, QP2 becomes low impedance and + Vout is amplified to the power supply voltage VDD. It

In the comparison circuit of FIG. 5, QC1 and QC2 are always ON, and therefore, the current consumption in the differential input stage and the constant current circuit was large, but in the present embodiment, when PH2 is at the low level, it becomes QS1. Since QC1 and QC2 are off, the current consumption in the differential input stage and the constant current circuit can be reduced. At this time, the positive feedback circuits QP1, QP2, Q
Only P3 and QP4 operate, and after amplifying the comparison result to the logic level, almost no power is consumed.

[0048]

As described above, according to the present invention, after the two outputs of the input circuit are amplified to some extent by the differential amplifier circuit, the non-linear differential amplifier circuit becomes large due to the positive feedback effect of the positive feedback circuit. Since the positive feedback circuit of the voltage comparison circuit with a latch is used to amplify the voltage gradually and hold it, even if the difference between the two input voltages to be compared is small, the input is made without increasing the circuit scale. The voltage can be amplified to logic level.
Further, by making the differential amplifier circuit, the non-linear differential amplifier circuit, and the voltage comparison circuit with a latch self-biased, it becomes possible to eliminate the need for the bias voltage generation circuit and reduce the power consumption.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram of an embodiment of an input circuit.

FIG. 3 is a circuit diagram of an embodiment of a differential amplifier circuit.

FIG. 4 is a circuit diagram of an embodiment of a non-linear differential amplifier circuit.

FIG. 5 is a circuit diagram of an embodiment of a voltage comparison circuit with a latch.

FIG. 6 is an operation waveform diagram of the embodiment.

FIG. 7 is a diagram of another embodiment of the input circuit.

FIG. 8 is a circuit diagram of another embodiment of the differential amplifier circuit.

FIG. 9 is a circuit diagram of an embodiment of a self-biased nonlinear differential amplifier circuit.

FIG. 10 is a circuit diagram of another embodiment of the voltage comparison circuit with a latch.

FIG. 11 is a circuit diagram of a conventional differential voltage comparator.

FIG. 12 is a circuit diagram of a conventional differential amplifier circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input circuit, 2 ... Differential amplification circuit, 3 ... Non-linear differential amplification circuit, 4 ... Latch voltage comparison circuit, 5 ... Differential amplification circuit, Vin, Vref ... Input voltage, V1, V2 ... Differential amplification circuit Output voltages of V3, V4 ... Non-linear differential amplifier circuit, Vout1, Vout2.

Claims (2)

[Claims] 1. A differential voltage comparator for comparing two voltages and amplifying a voltage difference, wherein an input circuit for receiving two voltages to be compared and two outputs of the input circuit are first capacitors. A differential amplifier circuit that is input via C1 and a second capacitor C2 and has a switching circuit connected between the input and output, and two outputs of the differential amplifier circuit are a third capacitor C3 and a fourth capacitor C4. A non-linear differential amplifier circuit having a switching circuit connected between the input and the output, a differential amplifier circuit to which two outputs of the non-linear differential amplifier circuit are input, and an output of the differential amplifier circuit are input. And a voltage comparison circuit with a latch having a latch circuit formed of a positive feedback circuit, and a differential voltage comparator. 2. The differential voltage comparator according to claim 1, wherein at least one of the differential amplifier circuit, the non-linear differential amplifier circuit, and the latched voltage comparator circuit is of a self-bias type. Dynamic voltage comparator.