JPH05175468A - Design method of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enhance the design efficiency of a semiconductor integrated circuit which has a core region where a plurality of basic logic circuit cells are laid out on a semiconductor board regularly, a power supply wiring ring which runs about in this core region and an input/output cell section laid out on the outer periphery of the ring. CONSTITUTION:There are preliminarily available a plurality of unit block-based basic layout patterns, which include a basic logical circuit 3, an input/output cell 1 and a power supply wiring 20, as a library. A core region, a power supply wiring ring, and input/output cell section are formed by combining these basic layout patterns.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a semiconductor integrated circuit, and more particularly to a full-element formation type gate array (SO
G: Sea Of Gate), a core region in which a plurality of basic logic circuit cells are regularly arranged on a semiconductor substrate, a power supply wiring ring that surrounds the core region, and an input / output cell portion arranged on the outer periphery are provided. A method for designing a semiconductor integrated circuit having the same.

[0002]

2. Description of the Related Art Conventionally, in the case of designing a semiconductor integrated circuit of this type, as shown in FIG. 4, first, an input / output cell 1 is arranged around the chip (FIG. 4 (a)), and then an input / output cell. 1, a power supply wiring ring 2 having an appropriate size is formed and arranged (FIG. 4B), and then a plurality of basic logic circuit cells 3 are regularly arranged inside the power supply wiring ring 2 to form a core. The method of setting the area (FIG. 4C) is adopted. Here, the input / output cell 1 and the basic logic circuit cell 3 are prepared as a library of basic layout patterns that have been unitized in advance, and by simply arranging these basic layout patterns in combination, the input / output cell unit and core A region is formed. However, the power supply wiring ring 2 is
After the configurations of the input / output cell unit and the core region are determined, the size and shape are determined and created each time.

[0003]

As described above, in the conventional method for designing a semiconductor integrated circuit, the generation and arrangement of the power supply wiring ring is performed independently of the arrangement of the input / output cells and the basic logic circuit cells. It is being appreciated. For this reason, even if the same input / output cell or basic logic circuit cell can be used, when designing circuits with different circuit scales (number of cells) This has to be done from the beginning, which causes a reduction in design efficiency. Not only is it troublesome to modify the power supply terminal position of the basic logic circuit, but the power supply wiring ring is always created as a whole, so once it is changed, It is difficult to recognize the changes.

An object of the present invention is to eliminate such a problem.

[0005]

A method of designing a semiconductor integrated circuit according to the present invention includes a plurality of types of basic layout patterns which are unit blocks including not only basic logic circuit cells and input / output cells but also power supply wirings in advance. It is prepared as a library and the basic layout patterns are combined and arranged to form a core region, a power supply wiring ring, and an input / output cell portion.

[0006]

The semiconductor integrated circuit including the core region, the power supply wiring ring, and the input / output cell portion can be obtained by simply selecting and combining an appropriate block (basic layout pattern) because the power supply wiring and the unit block are formed. Composed. Designing circuits with different circuit scales can be handled by simply changing the number of blocks used. Similarly, corrections such as when the power supply terminal position of the basic logic circuit is changed can be dealt with easily by adding or removing partial blocks, and since the changes are made in block units, which block was changed? It is easy to recognize the changed part.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a basic layout pattern used in this embodiment. Although the basic layout pattern of (e) in the figure consists of only the basic logic circuit cell 3, (a)-
Each of the basic layout patterns (d) and (f) to (i) includes an input / output cell 1, a basic logic circuit cell 3, and a wiring element 20 which is a constituent element of the power supply wiring ring 2.

FIG. 2 shows a layout example of a semiconductor integrated circuit realized by a combination of these basic layout patterns. A core region in which basic logic circuit cells 3 are regularly arranged is located in the center, and a power supply wiring ring 2 is arranged around the core region by a combination of wiring elements 20 in each basic layout pattern. An input / output cell portion composed of the input / output cells 1 is arranged on the outer periphery of the. The power supply wiring ring 2 has a double structure for supplying a power supply voltage on the inner side and for grounding the outer side.

The example of FIG. 2 is constructed by using one basic layout pattern of each of FIGS. 1A to 1I, using a total of nine basic layout patterns. According to this, it is possible to easily deal with the design of integrated circuits having different circuit scales. For example, FIG. 3 shows FIG. 1 (a), (c),
Each of the basic layout patterns (g) and (i) is one, each of the basic layout patterns (b), (d), (f) and (h) is two, and the basic layout pattern (e) is the same. It is configured by using four layout patterns. Similarly, by changing the number of basic layout patterns used in (b), (d), (f), (h) and (e), various integrated circuits having the same shape and different scales can be designed. By making a difference between the number of basic layout patterns used in (b) and (h) and the number of basic layout patterns used in (d) and (f), the vertical and horizontal dimensional ratios can be changed.

In the above embodiment, the basic logic circuit cell 3
A basic layout pattern consisting of only one and eight basic layout patterns including the input / output cell 1, the basic logic circuit cell 3 and the wiring element 20 are prepared as basic blocks. The structure of the basic layout pattern is not limited to this, and it goes without saying that the basic layout pattern including only the input / output cells and the wiring elements or the basic layout pattern including only the wiring elements may be made into a unit block. The smaller the unit block and the simpler the basic layout pattern, the larger the number of blocks (the number of basic layout patterns that are repeatedly arranged) required to form an integrated circuit by combining, but the integration that can be realized by combining The size and shape of the circuit will be various, and the degree of freedom will be increased.

[0011]

As described above, according to the present invention, a core having a plurality of basic logic circuit cells regularly arranged is prepared by preparing in advance a basic layout pattern which is divided into unit blocks including power supply wiring. The design efficiency of the semiconductor integrated circuit having the region, the power supply wiring ring that surrounds the core region, and the input / output cell portion arranged on the outer periphery is improved.

[Brief description of drawings]

FIG. 1 is a plan view showing a basic layout pattern used in an embodiment of the present invention.

FIG. 2 is a plan view showing a layout example of a semiconductor integrated circuit realized by combining the basic layout patterns of FIG.

FIG. 3 is a plan view showing another layout example.

FIG. 4 is a process plan view showing a conventional design method.

[Explanation of symbols]

1 ... Input / output cell, 2 ... Power supply wiring ring, 3 ... Basic logic circuit cell, 20 ... Wiring element.

Claims (1)

[Claims] 1. A core region in which a plurality of basic logic circuit cells are regularly arranged on a semiconductor substrate, a power supply wiring ring that circulates around the core region, and an input / output cell portion arranged on the outer periphery of the core region. In designing a semiconductor integrated circuit, a plurality of types of basic layout patterns are prepared in advance as a unit block including basic logic circuit cells, input / output cells, and power supply wiring, and these basic layout patterns are combined and arranged. A method of designing a semiconductor integrated circuit, comprising forming a core region, a power supply wiring ring, and an input / output cell portion by doing so.