JPH05173884A - System for processing address translation - Google Patents

Abstract

PURPOSE:To reduce a hardware amount which is necessary for restarting an instruction after an address translation processing in a data processor having an address conversion buffer. CONSTITUTION:The address translation processing end micro instruction which holds the instruction which misses address translation so as to select the held instruction as the input of an instruction register 11 when the address translation processing is completed and an instruction selecting circuit 10 are provided. The instruction is restarted by instruction write-back, held information at the time of missing address translation is reduced so as to reduce a hardware, an entry address where an exception detected during the address translation processing and a logical address 48 are registered as a directory is held and an equivalence to the entry is checked by address translation buffer access after restarting the instruction so that exception recognizing is enabled at the time of restarting the instruction after the address translation processing is completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address conversion system of a data processor, and more particularly to an address conversion system for restarting a soft instruction after the address conversion process and an address conversion exception reporting circuit detected during the address conversion process. The present invention relates to a conversion processing method.

[0002]

2. Description of the Related Art Conventionally, in this type of address conversion system,
If it is not registered in the address translation buffer (below,
It is called a TLB miss, and when it is registered in the TLB, T
This is called an LB hit). In order to execute the address translation process, not only the main memory access information at the time of the TLB miss but also all the information related to the subsequent instructions are held, and a main memory access path for executing the address translation process is provided. , The internal state of the data processor is TLB by using that path
Address translation processing and address translation exception detection are performed while maintaining the state at the time of the miss, so that a TLB miss main memory access can be immediately executed by a microinstruction indicating the end of the address translation processing. When an exception is detected, it can be reported immediately after the completion of the address conversion process.

[0003]

In this conventional address translation system, an instruction which has a TLB miss after the address translation processing is executed immediately, or an exception report when an exception is detected in the address translation processing is issued immediately after the instruction is restarted. A large amount of hardware must be spent to hold the internal state of the data processing device when a TLB miss occurs, which is a means for performing the above. Especially, when the data processing device is configured by a pipeline, the number of pipeline stages is increased. There was a problem that the amount of hardware also increased as the number increased. In addition, since the main memory access path for address conversion processing is duplicated and, in some cases, the control memory for the address conversion processing microprogram and its control circuit are provided, it is necessary to have dedicated hardware for the address conversion processing. There was a problem of getting bigger.

[0004]

The address translation processing method of the present invention has an instruction register for storing a soft instruction to be executed, analyzes the contents of the instruction register, and controls the execution of the instruction. And a logical address register that stores the logical address of the logical address generation block that generates this logical address when the main memory is accessed by the logical address that includes the segment number by segmentation and the page number by paging, and the logical address register that outputs this logical address generation block. The TLB has a TLB having a plurality of entries in a fully associative structure for taking out the physical address and the storage protection information of the space at a high speed without performing the address conversion process on the logical address of the address register output, and this TLB has the segment number and page. Number In the case where the logical address at the time of main memory access is not registered in the TLB, that is, it is composed of a directory part for registering the logical address and a data part for registering the physical address corresponding to this logical address and the storage protection information of the space. , A TLB miss occurs in a main memory access by a logical address in a data processing device in which an address translation interrupt is activated at the time of a TLB miss, an address translation is processed by a microprogram, and a soft instruction process is restarted by a microinstruction indicating the end of the address translation. An address conversion processing display flip-flop that is set at this time indicating that the address conversion processing is in progress, and when this address conversion processing display flip-flop is set, a logical address register and the above T as a physical address for accessing the main memory. A physical address selection circuit for selecting a logical address register from the physical address output from the B data section, a logical address and a history register for holding the logical address when the TLB miss occurs as the registered data of the TLB directory section, and a main memory for the TLB miss. It has an instruction history register that holds a history of soft instructions including accesses, an instruction selection circuit that selects the instruction history register output as the instruction register input at the end of the address translation processing, and an address translation processing end microinstruction. The instruction is returned to the instruction register, and the soft instruction returned to the instruction register is restarted.

An address translation processing method according to another invention of the present invention is an address translation exception register for storing exception information such as a segment fault or page fault detected in the address translation processing in the above data processing device. An exception entry number register that stores the TLB entry number that registers the logical address that detected the exception stored in the address translation exception register as a directory, and when the logical address hits the TLB,
A match detection circuit for detecting a match between the hit entry number and the contents of the exception entry number register, and this match detection circuit detected that the TLB hit entry number matches the contents of the exception entry number register. At this time, an exception reporting circuit for reporting the address translation exception information stored in the address translation exception register as an exception is provided.

[0006]

In the present invention, the soft instruction after the TLB miss and the address translation processing is executed is resumed by writing the TLB miss instruction back to the instruction register to reduce the hardware dedicated to the address translation processing. Only the logical address of the instruction that started the address translation process and the soft instruction are retained.

[0007]

FIG. 1 is a block diagram showing an embodiment of the present invention, showing an embodiment of a main memory access control unit of a data processing apparatus including the address translation processing system of the present invention.
The embodiment shown in FIG. 1 has a pipeline structure having three stages: an instruction execution control stage, a logical address generation stage, an address translation and a main memory access stage.

FIG. 2 is a block diagram showing the details of the configuration example of the address translation block in FIG.

The main memory access control unit of the data processor in the embodiment shown in FIG. 1 stores the soft instruction input data 40 returned from the main memory as a result of the main memory access for fetching the soft instruction, and the instruction execution control block. Instruction register 11 for supplying the soft instruction data 41 to 15, and the soft instruction data 41 output from the instruction register 11
The micro instruction 45 of the corresponding micro program is sequentially issued to the micro instruction register A16 of the logical address generation stage. If the issued micro instruction 45 is an instruction indicating the end of the soft instruction processing, the instruction register An instruction execution control block 15 that outputs an update signal 71 to update the instruction register 11 to control execution of a soft instruction and a pipeline control microinstruction 45 issued by the instruction execution control block 15 are stored, and a logical address is generated. Micro instruction register A16 for controlling the stage
And a logic that stores the output 46 of the microinstruction register A16 and that controls the address conversion and the main memory access stage, and a logic that generates a main memory access logical address by the instruction of the output 46 of the microinstruction register A16. Address generation block 18
And the logical address register 19 for storing the logical address 48 of the output of the logical address generation block 18, and the output 47 of the micro instruction register B17, the output 49 of the logical address register 19 is changed to the physical address 51.
A main memory access control block 21 for controlling the main memory access to the address conversion block 20 for converting to the physical address 51 and the converted physical address 51 by outputting the main memory access control signal 52, and an instruction history register for holding a soft instruction in stages. A12, the instruction history register B13, and the output 43 of the instruction history register B13 when the address translation fails in the address translation block.
The instruction history register C14 updated by

The instruction history register A12 stores the soft instruction issued by the micro instruction register A16, and the instruction history register B13 stores the soft instruction issued by the micro instruction register B17. The instruction history register A12 always stores the soft instruction data 41 output from the instruction register 11, and the instruction history register B13 always stores the output 42 from the instruction history register A12. Since the instruction history register C14 is updated by the output 43 of the instruction register B13 when the address translation fails, the soft instruction whose address translation failed is stored. 10 is an instruction register 11 at the end of the address conversion process
The instruction selection circuit for selecting the output of the instruction history register as an input of the instruction history register, the instruction history register A12, the instruction history register B13, and the instruction history register C14 are instruction history registers for holding the history of the soft instruction including the main memory access in which the TLB miss occurs. .. An output 44 of the instruction history register C14 is sent to the instruction selection circuit 10. Reference numeral 50 is an address translation processing display signal sent from the address translation block 20 to the instruction execution control block 15, and 53 and 54 are instruction invalidations sent from the instruction execution control block 15 to the micro instruction register A16 and the micro instruction register B17, respectively. The signal A and the instruction invalidation signal B.

Here, the instruction register 11 is an instruction register for storing an instruction to be executed, and the logical address register 19 stores this logical address at the time of main memory access by a logical address including a segment number by segmentation and a page number by paging. It is a logical address register for storing the logical address generation block 18 to be generated and the logical address of the output of this logical address generation block.

Next, the address conversion block 2 shown in FIG.
0 will be described. The address conversion block 20 is composed of an associative memory in which the directory portion is searched by the output 49 of the logical address register 19 in FIG. 1 and various registered data is output from the data portion of the entry in which the same data is registered. A full associative TLB 27, a logical address history register 23 for storing a logical address that is used as write data of a directory portion of the TLB 27 in an address conversion process, a TLB access data selector 24 for selecting TLB access data 62, and a main memory access A physical address selector 28 for selecting a physical address to be used, a TLB hit detection circuit 29 for checking the directory registration status signal 63 of the TLB 27 and detecting that search data is registered,
The TLB hit signal 66 output from the TLB hit detection circuit 29 is stored, the address conversion processing display flip-flop 31 indicating that the address conversion processing is in progress, and the TLB write data 55 are checked to detect an address conversion exception such as a segment fault or a page fault. The address translation exception detection circuit 25 to detect and the address translation exception register 26 that stores the detected address translation exception information 60, and the TLB registration entry number 68 when registering the logical address that detected the address translation exception in the directory part of the TLB 27. Exception entry number register 32 to store and TL
Directory registration status signal 63 obtained by searching B27
And the output 69 of the exception entry number register 32 are compared and a match detection circuit 33 that outputs an exception entry match signal 70 when they match, and a TLB 27 when a TLB hit occurs.
The exception report circuit 30 that recognizes the exception by the output 61 of the address translation exception register 26 and outputs the exception report signal 67 according to the storage protection information 65 output from the data section B of FIG. The micro instruction decode circuit 22 outputs the TLB registration timing signal 56, the address translation exception check signal 57, and the main memory access instruction signal 58 by inputting and analyzing the output 47 of the micro instruction register B17. Reference numeral 50 is an address conversion processing display signal output from the address conversion processing display flip-flop 31, and 59.
Is a logical address history register output sent from the logical address history register 23 to the TLB access data selector 24, and 64 is physical address registration data sent from the data section A of the TLB 27 to the physical address register 28.

Here, the logical address history register 2
Reference numeral 3 is a logical address history register that holds a logical address when a TLB miss occurs as registered data in the TLB directory section, and an address translation exception register 26 stores exception information such as a segment fault or page fault detected in the address translation process. This is an address translation exception register. Further, the TLB 27 is an address translation buffer having a plurality of entries in a full associative structure for extracting the physical address and the storage protection information of the space at high speed without passing through the address translation processing of the logical address of the output of the logical address register 19. It is composed of a directory section for registering a logical address including a number and a page number, and a data section for registering a physical address corresponding to the logical address and storage protection information of a space. The address selector 28 is a physical address selection circuit for selecting a logical address register from the logical address register and the physical address of the output of the TLB data section as the physical address for accessing the main memory when the address conversion processing display flip-flop 31 is set. Is composed of. Address conversion display flip-flop 3
Reference numeral 1 denotes an address conversion processing display flip-flop which indicates that the address conversion processing is being set when the main memory access by the logical address makes a TLB miss.

Then, the exception entry number register 32 registers the logical address stored in the address translation exception register for detecting the exception as a directory.
The match detection circuit 33 stores the entry number of the exception entry number, and the match detection circuit 33 detects the match between the hit entry number and the contents of the exception entry number register when the logical address has a TLB hit. When the match detection circuit 33 detects that the entry number of the TLB hit matches the content of the exception entry number register, 30 reports the address translation exception information stored in the address translation exception register as an exception. It is an exception reporting circuit.

Then, in the case of a TLB miss, the data processing device is configured to activate an address conversion processing interrupt, process the address conversion by the microprogram, and restart the soft instruction processing by the microinstruction indicating the end of the address conversion processing. ing. Further, the address translation processing system of the present invention has the instruction selection circuit 10 for selecting the instruction history register output as the instruction register input at the end of the address translation processing and the address translation processing end microinstruction, and stores the instruction that misses the TLB in the instruction register. And the soft instruction returned to the instruction register is restarted.

The operation and function of the embodiment shown in FIGS. 1 and 2 will be described below. First, the instruction execution control block 15 analyzes the soft instruction data 41 output from the instruction register 11 and continuously issues micro instructions related to the soft instruction one after another. This analyzed soft instruction is an instruction that execution ends with only one micro instruction, and if these are executed continuously, each soft instruction is expanded in each pipeline stage of the data processing device. Become. When the TLB hit detection circuit 29 detects that the logical address register output 49 for main memory access is not registered in the TLB 27 of the address translation block 20 in the address translation and main memory access stage, the address translation and main memory access are suppressed. At the same time, the output 43 of the instruction history register B13 is stored in the instruction history register C14, the address translation processing display flip-flop 31 is set, and the address translation processing display signal 50 is reported to the instruction execution control block 15. When the execution control block 15 receives the address conversion processing display signal 50, the micro instruction register A
16 and the instruction invalidation signal A53 and the instruction invalidation signal B54 for invalidating the subsequent microinstruction stored in the microinstruction register B17, all the operations in the pipeline are invalidated. At the same time, the micro instruction of the micro program for the address conversion processing is started to be issued.

Next, in the address conversion processing microprogram, various address control tables for controlling segmentation and paging are accessed to take out physical addresses. When accessing the address control table, the logical address register output 49 is selected by the physical address selector 28, and the data in the address control table can be taken out without accessing the TLB 27. Then, the data in the address table is checked in the process of fetching the physical address, and an address translation exception such as a segment fault or a page fault is detected. The address control table data is output on the TLB write data 55, and is checked by the address translation exception detection circuit 25 at the timing of the address translation exception check signal 57 output from the microinstruction decode circuit 22, and the address translation exception information 60 is translated. It is stored in the exception register 26. Here, if the address can be translated into a physical address without detecting an address translation exception, the TLB miss held in the logical address history register 23 causes the logical address that initiated the address translation process to be stored in the directory or address control table. The memory protection information and the physical address are registered in the TLB 27, and the address conversion process is completed. When the address translation exception is detected, the TLB registration entry number 68 is stored in the exception entry number register 32 together with the directory registration in the TLB 27, and the address translation process is terminated. At this time, a microinstruction indicating the end of the address translation process is issued from the instruction execution control block 15, and when the instruction selection circuit 10 reaches the microinstruction register B17, the instruction selection register 10 determines that the instruction history register C14 is a soft instruction whose execution has not been completed due to a TLB miss. Output 44 is selected and stored in the instruction register. At the same time, the address conversion processing display flip-flop 31 is reset. The soft instruction written back to the instruction register 11 is input to the instruction execution control block 15 as the soft instruction data 41 and analyzed, and the soft instruction is restarted.

Next, when the soft instruction is restarted, the main memory access is executed again by the logical address that has missed the TLB last time, but this time the TLB 27 is hit and the physical address is transferred from the data section A to the physical address registration data 64.
As a result, the storage protection information of the access space can be taken out from the data section B as the storage protection information 65, and the physical address selector 28 selects the physical address 51 and the exception reporting circuit 30 checks the storage protection information, without delay. Soft instructions can be executed. When an address translation exception is detected during the address translation process, the logical address register output 49 as the TLB access data 62 hits the TLB 27, and the hit entry number matches the contents of the exception entry number register 32. Is detected by the coincidence detection circuit 33, and the exception report circuit 30 recognizes that an exception of the contents of the address translation exception register 26 has occurred, the exception report signal 67 can be output, and exception processing can be started. it can.

With the circuit configuration and function described above,
By retaining only the logical address information of the instruction that started the address translation process and the soft instruction, all subsequent instructions can be invalidated, and the address translation process using the existing main memory access control circuit becomes possible A data processing device that does not require hardware for saving and holding data or instruction execution control hardware dedicated to address translation processing is configured.

[0020]

As described above, according to the present invention, the soft instruction after executing the TLB miss address conversion processing is restarted by writing back the TLB miss instruction to the instruction register, and the hardware dedicated to the address conversion processing is executed. Since the hardware is reduced and only the logical address and the soft instruction of the instruction that started the address translation process are held, the subsequent instruction can be stored by holding only the logical address information and the soft instruction of the instruction that started the address translation process. Can be disabled, address translation processing using the existing main memory access control circuit is possible, and hardware for saving and holding subsequent instructions or instruction execution control hardware dedicated to address translation processing is required. Data processing device can be configured, and the amount of hardware can be significantly reduced. There can be effectively. In general, the possibility that the address translation will miss the TLB depends on the specifications of the TLB itself, such as the number of entries and the number of compartments. Further, if the TLB itself has a hit ratio of a certain value or more, immediate restart of a TLB missed instruction is not significant as a contribution to the performance of the data processing device. Therefore, the address conversion processing method of the present invention has an effect that the impact on performance can be minimized and a large amount of hardware can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a main memory access control unit of a data processing device including the present invention.

FIG. 2 is a block diagram showing details of a configuration example of an address conversion block in FIG.

[Explanation of symbols]

 10 instruction selection circuit 11 instruction register 12-14 instruction history register A, B, C 15 instruction execution control block 16-17 micro instruction register A, B 18 logical address generation block 19 logical address register 20 address translation block 21 main memory access control Block 23 Logical address history register 26 Address translation exception register 27 Address translation buffer (TLB) 28 Physical address selector 29 TLB hit detection circuit 30 Exception reporting circuit 31 Address translation processing display flip-flop 32 Exception entry number register 33 Match detection circuit

Claims (2)

[Claims] 1. An instruction execution control block having an instruction register for storing a soft instruction to be executed, analyzing the contents of the instruction register and controlling the execution of the instruction, and a segment number by segmentation and a page number by paging. A logical address generation block that generates this logical address when accessing the main memory by a logical address, a logical address register that stores the logical address of the output of this logical address generation block, and the logical address of this logical address register output does not undergo address conversion processing. Has an address translation buffer having a plurality of entries in a fully associative structure for high speed retrieval of physical address and storage protection information of space, and this address translation buffer registers a logical address including the segment number and page number. It is composed of a directory part to be recorded and a data part for registering storage protection information of a physical address and space corresponding to this logical address, and when the logical address at the time of main memory access is not registered in the address conversion buffer, an address conversion processing interrupt In the data processing device that starts up the address, processes the address translation by the microprogram, and restarts the soft instruction processing by the microinstruction indicating the end of the address translation processing, when the main memory access by the logical address is not registered in the address translation buffer. An address conversion processing display flip-flop that indicates that the address conversion processing is being set, and when the address conversion processing display flip-flop is set, the logical address register and the address are used as physical addresses for main memory access. A physical address selection circuit for selecting a logical address register from a physical address output from the translation buffer data section, and a logical address history for holding a logical address when it is not registered in the address translation buffer as registered data in the address translation buffer directory section. A register, an instruction history register that holds a history of soft instructions including main memory access when not registered in the address translation buffer, and an instruction that selects the instruction history register output as the instruction register input at the end of the address translation process. The present invention is characterized in that it has a selection circuit and a micro instruction for terminating address conversion processing, and returns an instruction when it is not registered in the address translation buffer to the instruction register, and restarts from the soft instruction returned to the instruction register. When Address conversion processing method that. 2. An instruction execution control block, which has an instruction register for storing a soft instruction to be executed, analyzes the contents of the instruction register and controls the execution of the instruction, and includes a segment number by segmentation and a page number by paging. A logical address generation block that generates this logical address when accessing the main memory by a logical address, a logical address register that stores the logical address of the output of this logical address generation block, and the logical address of this logical address register output does not undergo address conversion processing. Has an address translation buffer having a plurality of entries in a fully associative structure for high speed retrieval of physical address and storage protection information of space, and this address translation buffer registers a logical address including the segment number and page number. It is composed of a directory part to be recorded and a data part for registering storage protection information of a physical address and space corresponding to this logical address, and when the logical address at the time of main memory access is not registered in the address conversion buffer, an address conversion processing interrupt In the data processing device that starts up, processes the address translation by the micro program, and restarts the soft instruction process by the micro instruction indicating the end of the address translation process, the exception information such as the segment fault and the page fault detected by the address translation process is stored. Address translation exception register,
An exception entry number register that stores the entry number of the address translation buffer that registers the logical address that detected the exception stored in this address translation exception register as a directory, and a logical address when the logical address is registered in the address translation buffer. , A match detection circuit for detecting a match between the hit entry number and the contents of the exception entry number register, and a match detection circuit that matches the entry number registered in the address translation buffer with the contents of the exception entry number register. An address translation processing method characterized by comprising an exception reporting circuit for reporting the address translation exception information stored in the address translation exception register as an exception when it is detected.