JPH05173584A - Effect addition device - Google Patents

Abstract

PURPOSE:To finely add effect. CONSTITUTION:An input acoustic signal Ei is divided by band-pass filter processing parts 301 of #A, #B, and #C into respective acoustic signals W(A4), W(B4), and W(C4) of three frequency bands, and respective reverberation processing parts 302 of #A, #B, and #C add reverberation effect respectively. Consequently, the resulting outputs W(A9), W(B9), and W(C9) of the three frequency bands are mixed by a mixing process part 303 and outputted as an acoustic signal Eo.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an effect adding device for adding a sound effect to a sound signal input from a musical instrument or the like.

[0002]

2. Description of the Related Art Conventionally, an effect adding device has been proposed which adds effects such as reverberation, chorus and delay to an input acoustic signal.

With the development of digital signal processing technology, these conventional effect adding devices have become possible to be miniaturized and have multiple functions. That is, for example, it is possible to simultaneously add a plurality of different types of effects to the acoustic signal. Or the depth and depth of the effect,
For example, in the case of a reverb effect, it is possible to easily and finely adjust the initial delay time, the attenuation ratio, and the like.

[0004]

However, even if the above-described effects are added, it is often impossible to completely respond to the player's will and the external environment, and only an artificial output sound can be generated. I have a problem.

For example, a reverb device is applied as such an effect adding device, and no matter how much the initial delay time or the attenuation coefficient is adjusted in order to give an input acoustic signal a reverberation like that in a special music hall. ,
In many cases, I could only get an artificial feeling.

An object of the present invention is to make it possible to add effects more finely.

[0007]

According to the present invention, first, there is a band dividing means for dividing an input acoustic signal into a plurality of band divided acoustic signals each having a different frequency band. The means is, for example, a digital signal processor that executes a plurality of band pass filtering processes each having a different pass band by time division processing.

Next, there is provided band-specific sound effect adding means for adding a sound effect to each band-divided sound signal output from the band-division means. This means executes, for example, a plurality of reverberation effect (reverb) addition processes each having different reverberation characteristics.

Further, it has a mixing output means for mixing and outputting the respective band-divided acoustic signals to which the acoustic effect is added by the band-specific acoustic effect adding means.

[0010]

According to the present invention, after dividing the acoustic signal into signals of a plurality of frequency bands, different acoustic effects can be added to the acoustic signals of the respective bands.

Therefore, for example, the reverberation of a music hall having different reverberation characteristics depending on the frequency band can be added with a natural feeling.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. Overall Configuration FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

An analog acoustic signal I input from the outside
After being converted into a digital signal by the A / D converter 107, n is input to the DSP 105. DSP105,
By using a connected delay memory (E) 106 and the like and executing a predetermined operation program, processing for adding a reverberation effect to the input digital acoustic signal data is performed.

The digital acoustic signal to which the reverberation effect has been added is converted into an analog acoustic signal Out by the D / A converter 108 and output. The CPU 101 executes a program stored in the ROM 102 by using the RAM 103 as a work memory so that the user can operate the console unit 10
Various setting contents for adding reverberation set in 4 are fetched and set in the DSP 105. Internal Configuration of DSP Next, FIG. 2 is a diagram showing the internal configuration of the DSP 105 of FIG.

In FIG. 1, a program memory 201 is a memory for storing a predetermined microprogram, and supplies a predetermined operation program to the control circuit 202 in accordance with an instruction from the CPU 101 of FIG.

The control circuit 202 includes a program memory 20.
Based on the output content of 1, outputs each register described later, data transfer and calculation between memories, various control signals for controlling opening and closing of each gate and latch, and a counter value SC incremented at each sampling timing, Perform desired signal processing operations.

As shown in FIG. 17, the coefficient memory (P) 203 is a register for storing various parameters for adding the reverberation effect, and these coefficients are read from the RAM 103 of FIG. 1 under the control of the CPU 101. Stored.

The work memory (W) 204 is a working memory for temporarily saving the waveform signal created in the DSP 105, as shown in FIG. The delay offset memory (T) 205 is a register for storing an offset value of an address of a delay memory (E) 106, which will be described later, as shown in FIG. 17, and the offset value is controlled by the CPU 101 as shown in FIG. RAM1
It is read from 03 and stored.

The delay memory (E) 106 has its output and input connected in a ring shape through registers (EI) 230 and (EO) 229, and has a counter value SC incremented at each sampling timing and a delay memory. The value obtained by adding the offset value from the delay offset memory (T) 205 by the adder 227 is used as the address. The delay time of data written with a certain offset value is expressed by the difference between the offset delay and the offset delay of the address to be read. Data is read from and written to the delay memory 106 in registers (EO) 229 and (E) described later.
I) 230.

The input register (PI) 206 stores the digital input acoustic signal Ei from the sound source 104 of FIG. 1 and supplies it to each unit via the internal bus 207. The outputs of the coefficient memory (P) 203 and the work memory (W) 204 and the output of the input register (PI) 206 described above are input to the gate terminals of gates 208 to 211 together with the outputs from the registers described later, and the gates 208 to 211 are output. The outputs from 211 are registers (M0) 212, (M1) 213, (A0) 21.
4 and (A1) 215.

Registers (M0) 212, (M1) 213
Stores the data in the middle of calculation supplied to the multiplier 216, and the registers (A0) 214 and (A1) 215 store the data in the middle of calculation supplied to the adder / subtractor 217. Also, the register (M1) The output of the register 213 and the output of the register (SR) 224, which will be described later, are input to the multiplier 216 via the gate 218 and the register (A0) 2
14 and the output of the register (MR) 221 described later are input to the adder / subtractor 217 via the gate 219, and the output of the register (A1) 215 and the register (A
The output of R) 222 is added via the gate 220 to the adder / subtractor 21.
7 is output.

The multiplication result of the multiplier 216 is stored in the register (M
R) 221 and the output of the register (MR) 221 is supplied to the gate 209 and the gate 219.
The calculation result of the adder / subtractor 217 is stored in the register (AR) 222, and the output of the register (AR) 222 is the gate 22.
0 and the register (LF) 231,
It is supplied to the register (SR) 224 via the clipper circuit 223 for preventing overflow (digit overflow). In addition, the sign bit F (A
R) is input to the control circuit 202. Register (S
The output of R) 224 is supplied to the gate 218, and the internal bus 20
7 to the work memory (W) 204.

The above calculation result is the work memory (W) 20.
4 and the series of processing is completed, the data stored in the same memory is transferred to the output register (OR) 225, and output from the same register to the D / A converter 107 of FIG.
It is output as o.

On the other hand, the delay offset memory (T) 205
Is output to the register (TR) 226. The output of the register (TR) 226 or the output of the register (LF) 231 (the output of the register AR is stored) is a counter value S that is incremented at each sampling timing.
It is input to the adder 227 together with C. The calculation result of the adder 227 is input to the register (EA) 228, and the value of the register is stored in the delay memory (E) 106 as an address. Further, the digital input acoustic signal to which the reverberation effect is added is transmitted via the internal bus 207 to the register (E
O) 229, and the output of the register is supplied to the delay memory (E) 106. The output from the delay memory (E) 106, which is delayed by a predetermined amount and modulated by the difference value between the write address and the read address, is the register (EI) 23.
It is output to 0.

The acoustic signal data added with the reverberation effect and stored in the register (EI) 230 is transferred to the registers (A0) 214, (A) via the internal bus 207, for example.
1) Transferred to 215. Operating Principle of DSP Next, FIG. 3 shows the sound source 104 of FIG. 1 and the DS of FIG. 1 or 2.
It is an operation principle block diagram of P105.

First, the input acoustic signal Ei is #A, #
The acoustic signals W (A4), W (B4), W of the three frequency bands are processed by the B and #C bandpass filter processing units 301.
After being divided into (C4), reverberation effects are added in the respective reverb processing units 302 of #A, #B, and #C. Outputs W (A9), W (B) of the three frequency bands obtained as a result
9) and W (C9) are mixed in the mixing processing unit 303 and output as an acoustic signal Eo.

As described above, the present invention is characterized in that after dividing the acoustic signal into signals in a plurality of frequency bands, different reverberation effects can be added to the acoustic signals in the respective bands. Therefore, for example, the reverberation of a music hall having different reverberation characteristics depending on the frequency band can be added with a natural feeling.

Next, FIG. 4 is a more detailed block diagram of the operating principle of the bandpass filter processing section 301 of #A in FIG. In this way, the #A bandpass filter processing unit 301
Includes a #A low-pass filter processing unit 401 that executes a low-pass filtering process and a #A high-pass filter processing unit 402 that executes a high-pass filtering process.

The low-pass filter processing unit 401 of #A has multipliers 403 to 405, adders 406 and 407, and a one-sample delay element (Z ^-1 ) having the circuit configuration shown in FIG.
408. Multipliers 403, 404, 40
5, the multiplication coefficients P (L1A), P (L2A), and P (L3A) are given from the coefficient memory (P) 203 (see FIG. 17), and the input acoustic signal Ei and the one-sample delay element (Z ^{− 1} ) The output of 408 and the output of the adder 407 are respectively stored in the work memory (W) 204 as variable values W
It is held as (INP), W (A1), and W (A2) (see FIG. 18).

The high-pass filter processing unit 402 of #A has multipliers 409 to 411, adders 412 and 413, and a 1-sample delay element (Z ⁻¹ ) having the circuit configuration shown in FIG.
414. Multipliers 409, 410, 41
1 is given each multiplication coefficient P (H1A), P (H2A), P (H3A) from the coefficient memory (P) 203 (see FIG. 17), and one sample delay element (Z ⁻¹ ) 408.
And the output of the adder 407 are held in the work memory (W) 204 as variable values W (A3) and W (A4), respectively (see FIG. 18).

The detailed operation principle block diagram of the band pass filter processing section 301 of #B and #C in FIG. 3 is also the same as in FIG. However, each multiplication coefficient P (L1A), P (L2) of #A
A), P (L3A), P (H1A), P (H2A), and P (H3A) are P (L1B) and P in the case of #B, respectively.
(L2B), P (L3B), P (H1B), P (H2
B) and P (H3B), and in the case of #C, P (L1)
C), P (L2C), P (L3C), P (H1C), P
(H2C) and P (H3C) (Fig. 1
7).

Further, the variable values W (A1), W (A
2), W (A3), and W (A4) are W (B1), W (B2), W (B3), and W (B4) in the case of #B, respectively.
In the case of #C, W (C1), W (C2), W (C
3) and W (C4) (see FIG. 18).

Next, FIG. 5 is a more detailed block diagram of the operating principle of the reverb processing unit 302 of #A in FIG. As described above, the #A reverb processing unit 302 includes the three comb filter processing units 502 (# A-1, # A-2, #A) connected in parallel via the #A all-pass filter processing unit 501. -3) is input. Then, the respective outputs of the comb filter processing unit 502 are mixed by the reverb mixing processing unit 503 (#A) and output.

First, the bandpass filter processing section 30 of #A
The output W (A4) of 1 (see FIG. 3 or FIG. 4) is input to the all-pass filter (all-pass filter) processing unit 501, where the delay component of the output is increased and has a large number of delay components. As the output signal W (A5), three comb filter processing units 502 (# A-1, # A- connected in parallel) are used.
2, # A-3).

In the present embodiment, an example in which one all-pass filter processing section 501 is inserted as an all-pass filter provided in the preceding stage of the comb filter processing section 502 for adding reverberant sound is shown, but of course, this number and connection are required. The method is not limited, and two or more may be used.

The all-pass filter processing unit 501 is shown in FIG.
, The multipliers 504, 505 and the adder 50
6, 507 and a delay element 508. Multipliers 504 and 505 have multiplication coefficients P (A1A) and P (A2) from coefficient memory (P) 203, respectively.
A) is given (see FIG. 17), and the output of the adder 507 is held as a variable value W (A5) in the work memory (W) 204 (see FIG. 18).

As described above, the all-pass filter processing unit 5
01 has a delay element 508 in between, and its output has a coefficient P.
It is fed back through a multiplier 504 multiplied by (A1A), and its input is feed-forwarded through a multiplier 505 multiplied by a coefficient P (A2A). Therefore, when a signal is input to the all-pass filter 501, a large number of delay components are output based on the input signal.

The output signal data W (A5) of the above all-pass filter processing unit 501 is input to the comb filter processing units 502 (# A-1, # A-2, # A-3) provided in parallel with each other. Has been done. Each of these comb filter processing units 502 includes a multiplier 509, an adder 510, and a delay element 512. Each of the multipliers 509-1, 509-2, and 509-3 has a multiplication coefficient P from the coefficient memory (P) 203.
(C1A), P (C2A), P (C3A) are given (see FIG. 17), and adders 511-1, 511-2, 511-3 are added.
Output of each variable is stored in the work memory (W) 204 as the value of each variable W.
It is held as (A6), W (A7), and W (A8) (see FIG. 18).

From each comb filter processing unit 502,
The signal data W (A5) is the delay elements 512-1, 512-
2, 512-3 are delayed by an amount corresponding to different offset addresses (described later), and the feedback amount to each input side is given to each multiplier 509-1, 509-2, 509-3. Coefficients P (C1A), P (C2A), P (C3A)
Outputs W (A6), W (A7), which are determined corresponding to
W (A8) is obtained.

Each of these outputs is supplied to the reverb mixing processing unit 5
The adders 513 and 514 in 03 (#A) add and mix and output. Then, this mixed output is held in the work memory (W) 204 as a variable value W (A9) (see FIG. 18).

The detailed operation principle block diagram of the #B and #C reverb processing unit 302 in FIG. 3 is also the same as that in FIG. However, #A
Multiplication coefficients P (A1A), P (A2A), P (C1
A), P (C2A), and P (C3A) are P (A1B), P (A2B), P (C1B), and P in the case of #B, respectively.
(C2B) and P (C3B), in case of #C, P respectively
(A1C), P (A2C), P (C1C), P (C2
C) and P (C3C) (see FIG. 17).

The variable values of #A W (A5), W (A
6), W (A7), W (A8), and W (A9) are #B
, W (B5), W (B6), W (B7), W
(B8) and W (B9), W (C
5), W (C6), W (C7), W (C8), and W
(C9) (see FIG. 18). Specific Operation of DSP The specific operation of the DSP 105 of FIG. 1 having the configuration of FIG. 2 which operates based on the operation principle of FIGS. 3 to 5 will be described with reference to the operation flowcharts of FIGS. .. Note that these operation flowcharts are for the DSP 10
5 is realized as an operation for executing the microprogram stored in the internal program memory 201. <Overall Operation> FIG. 6 is an operation flowchart showing the overall operation of the DSP 105.

In the input processing of step S601,
A process of taking the acoustic signal Ei from the A / D converter 107 of FIG. 1 into the work memory (W) 204 is executed. In the band pass filter process (#A) of step S602, the process of FIG.
The bandpass filtering process for realizing the function of the #A bandpass filter processing unit 301 is executed.

In the reverb processing (#A) of step S603, reverberation adding processing for realizing the function of the reverb processing unit 302 of #A of FIG. 3 is executed. In the bandpass filter processing (#B) of step S604, the bandpass filtering processing for realizing the function of the bandpass filter processing unit 301 of #B of FIG. 3 is executed.

In the reverb processing (#B) of step S605, reverberation addition processing for realizing the function of the reverb processing unit 302 of #B of FIG. 3 is executed. In the bandpass filter processing (#C) of step S606, the bandpass filtering processing for realizing the function of the bandpass filter processing unit 301 of #C of FIG. 3 is executed.

In the reverb processing (#C) of step S607, reverberation adding processing for realizing the function of the reverb processing unit 302 of #C in FIG. 3 is executed. In the mixing process of step S608, a mixing process for realizing the function of the mixing processing unit 303 of FIG. 3 is executed.

In the output process of step S609, a process of outputting the output data obtained in the work memory (W) 204 to the D / A converter 108 of FIG. 1 as the output acoustic signal Eo is executed. <Input Processing> Next, FIG. 7 is an operation flowchart of the input processing in step S601 of FIG.

In this process, as shown in step S701, the input acoustic signal Ei A / D converted by the A / D converter 107 in FIG. 1 is converted into the input register (P
The variable value W (INP) is stored in the work memory (W) 204 from the IO) 206 via the bus 207. <Bandpass Filter Processing (#A)> Next, FIG.
7 is an operation flowchart of the bandpass filter process (#A) in step S602 of FIG.

As shown in FIG. 8, the bandpass filter process (#A) is composed of the lowpass filter process (#A) of step S801 and the highpass filter process (#A) of step S802, each of which is shown in FIG. #A low-pass filter processing section 401 and #A high-pass filter processing section 40
It realizes the function of 2.

FIG. 9 is an operation flowchart of the low-pass filter processing (#A) in step S801 of FIG. First, in step S901, the coefficient P (L1A) is read from the coefficient memory (P) 203, and the register (M0) 21
Set to 2. Further, the variable value W (INP) is read from the work memory (W) 204, and the register (M1)
213 is set. Next, in step S902, the coefficient P (L1 set in the register (M0) 212 is set.
A) and the variable value W (INP) set in the register (M0) 212 are multiplied by the multiplier 216, and the multiplication result is set in the register (MR) 221. By these processes, the low-pass filter processing unit 40 of FIG.
Processing equivalent to the function of the multiplier 403 in 1 (#A) is realized.

In the same step S902, the variable value W (A1) is read from the work memory (W) 204 and set in the register (M1) 213. Further, the coefficient P (L2A) is read from the coefficient memory (P) 203 and set in the register (M0) 212. Further, step S
At 903, the multiplication result P (L1A) × W (INP) obtained in the register (MR) 221 is stored in the register (AR) 222.
Moved to. Then, the coefficient P (L2A) set in the register (M0) 212 and the register (M1) 213
And the variable value W (A1) set in
6 and the multiplication result is registered in the register (MR) 221.
Is set to. By these processes, a process equivalent to the function of the multiplier 404 in the low pass filter processing unit 401 (#A) in FIG. 4 is realized.

In the same step S903, the variable value W (A1) is read from the work memory (W) 204 and set in the register (M1) 213. Further, the coefficient P (L3A) is read from the coefficient memory (P) 203 and set in the register (M0) 212. Then, in step S904, the multiplication result W (A1) × P (L2A) set in the register (MR) 221 and the register (A
R) The multiplication result P (L1A) set in 222 ×
W (INP) is added by the adder / subtractor 217. By these processes, the low-pass filter processing unit 401 in FIG.
Processing equivalent to the function of the adder 406 in (#A) is realized.

In the same step S904, the register (M
0) coefficient P (L3A) set to 212 and variable value W (A set to register (M1) 213
1) is multiplied by the multiplier 216, and the multiplication result is set in the register (MR) 221. By this processing, processing equivalent to the function of the multiplier 405 in the low-pass filter processing unit 401 (#A) in FIG. 4 is realized.

In step S905, the register (AR)
Addition result W (A1) × P (L
2A) + P (L1A) × W (INP) is the register (S
R) 224. In addition, the register (MR) 221
Multiplication result set to P (L3A) × W (A1)
And the addition result set in the register (AR) 222 are added by the adder / subtractor 217, and the addition result is set in the register (AR) 222. By this processing, processing equivalent to the function of the adder 407 in the low-pass filter processing unit 401 (#A) in FIG. 4 is realized.

In step S906, the register (SR)
Addition result W (A1) × P (L
2A) + P (L1A) × W (INP) is stored in the work memory (W) 204 as a variable value W (A1). By this processing, the low-pass filter processing unit 401 of FIG.
Processing equivalent to the function of the 1-sample delay element 408 in (#A) is realized.

In the same step S906, the register (A
R) result of addition P (L3A) set to 222 ×
W (A1) + {W (A1) × P (L2A) + P (L1
A) × W (INP)} is moved to the register (SR) 224. Then, in the next step S907, the addition result set in the register (SR) 224 is stored in the work memory (W) 204 as the variable value W (A2). By these processes, a process equivalent to the function of outputting data from the adder 407 of the low pass filter processing unit 401 (#A) in FIG. 4 is realized.

Next, FIG. 10 shows step S802 of FIG.
3 is an operational flowchart of the high-pass filter process (#A) of FIG. First, in step S1001, the coefficient memory (P)
The coefficient P (H1A) is read from 203 and set in the register (M0) 212. Further, the variable value W (A2) is read from the work memory (W) 204 and set in the register (M1) 213. Next, step S
In 1002, the coefficient P (H1A) set in the register (M0) 212 and the variable value W (A2) set in the register (M0) 212 are multiplied by the multiplier 216, and the multiplication result is registered in the register. (MR) 221 is set. By these processes, a process equivalent to the function of the multiplier 409 in the high pass filter processing unit 402 (#A) in FIG. 4 is realized.

In the same step S1002, the variable value W (A3) is read from the work memory (W) 204 and set in the register (M1) 213. Further, the coefficient P (H2A) is read from the coefficient memory (P) 203 and set in the register (M0) 212. Further, step S
In 1003, the multiplication result P (H1A) × W (A2) obtained in the register (MR) 221 is stored in the register (AR) 222.
Moved to. Subsequently, the coefficient P (H2A) set in the register (M0) 212 and the register (M1) 213
The variable value W (A3) set in
6 and the multiplication result is registered in the register (MR) 221.
Is set to. By these processes, a process equivalent to the function of the multiplier 410 in the high pass filter processing unit 402 (#A) in FIG. 4 is realized.

In the same step S1003, the variable value W (A3) is read from the work memory (W) 204 and set in the register (M1) 213. Further, the coefficient P (H3A) is read from the coefficient memory (P) 203 and set in the register (M0) 212. Then, in step S1004, the multiplication result W (A3) × P (H2A) set in the register (MR) 221 and the register (A
R) multiplication result set in 222 P (H1A) ×
W (A2) is added by the adder / subtractor 217. By these processes, the high pass filter processing unit 402 of FIG.
Processing equivalent to the function of the adder 412 in (#A) is realized.

In the same step S1004, the coefficient P (H3A) set in the register (M0) 212 and the variable value W set in the register (M1) 213 are set.
(A3) is multiplied by the multiplier 216, and the multiplication result is set in the register (MR) 221. By this processing, processing equivalent to the function of the multiplier 411 in the high pass filter processing unit 402 (#A) in FIG. 4 is realized.

In step S1005, the register (A
R) addition result W (A3) × P set in 222
(H2A) + P (H1A) × W (A2) is transferred to the register (SR) 224. In addition, the register (MR) 2
The multiplication result set to 21 is P (H3A) × W (A
3) and the addition result set in the register (AR) 222 are added by the adder / subtractor 217, and the addition result is set in the register (AR) 222. By this processing, the high pass filter processing unit 402 (#A) of FIG.
The processing equivalent to the function of the adder 413 in FIG.

In step S1006, the register (S
R) addition result W (A3) × P set in 224
(H2A) + P (H1A) × W (A2) is stored in the work memory (W) 204 as the variable value W (A3).
By this processing, the high pass filter processing unit 402 of FIG.
Processing equivalent to the function of the 1-sample delay element 414 in (#A) is realized.

At the same step S1006, the addition result P (H3) set in the register (AR) 222 is set.
A) × W (A3) + {W (A3) × P (H2A) + P
(H1A) × W (A2)} becomes the register (SR) 224
Moved to. Then, in the next step S1007, the addition result set in the register (SR) 224 is stored in the work memory (W) 204 as the variable value W (A4). By these processes, a process equivalent to the function of outputting data from the adder 413 of the high pass filter processing unit 402 (#A) in FIG. 4 is realized. <Reverb Processing (#A)> Next, FIG. 11 is an operation flowchart of the reverb processing (#A) in step S603 of FIG.

As shown in FIG. 11, the reverb processing (#A) is
All-pass filter processing (#A) in step S1101,
Comb filter processing (# A-1) in step S1102, comb filter processing (# A-2) in step S1103, comb filter processing (# A-3) in step S1104, and reverb mixing processing (#A) in step S1105. Consists of and
The all-pass filter processing unit 501 of #A in FIG.
Comb filter processing unit 502 (# A-1), comb filter processing unit 502 (# A-2), comb filter processing unit 502 (# A-
3) and the function of the reverb mixing processing unit 503 (#A) are realized.

FIG. 12 is an operation flowchart of the all-pass filter process (#A) in step S1101 of FIG. First, in step S1201, in the adder 227, the read delay offset T read from the delay offset memory (T) 205 is added to the counter value SC generated from the control circuit 202 at each sampling timing.
(ARA) (see FIG. 19) is added, and the added value is set in the register (EA) 228 as an address value.

Next, in step S1202, the delay memory (E) 106 is accessed with the address value set in the register (EA) 228 as described above, and the delay memory (E) 106 is written from that address at the sampling timing earlier than the present. The waveform data E (EA) is read out and the register (E
I) 230.

Subsequently, in step S1203, the above-mentioned waveform value E (EA) stored in the register (EI) 230.
However, the register (M1) 213 and the register (A0) 21
4 is transferred. Along with this, the coefficient P (A1A) is read out from the coefficient memory (P) 203, and the register (M0)
It is set to 212.

Then, in step S1204, the coefficient P (A1A) set in the register (M0) 212 and the waveform value E (EA) from the delay memory (E) 106 set in the register (M1) 213 are set. And are multipliers 21
6 and the multiplication result is registered in the register (MR) 221.
Is set to.

By the operations of the above steps S1201 to S1204, the all-pass filter processing unit 5 of #A in FIG.
In 01, the waveform value of one sampling period before is read from the delay element 508, and the multiplier 504 outputs the coefficient P (A1
A process equivalent to the function by which A) is multiplied is realized.

In the same step S1204, the variable value W (A4), which is the output generated by the bandpass filter processing (#A) in step S602 of FIG. 6, is read from the work memory (W) 204, and the register ( A1) 21
Set to 5. Next, in step S1205, the variable value W (A4) set in the register (A1) 215 is set.
And the multiplication result P (A1A) × E (EA) set in the register (MR) 221 are added by the adder / subtractor 217, the addition result is set in the register (AR) 222, and further, step S1206 And register (S
R) 224. By these processes, #A in FIG.
Processing equivalent to the function of the adder 506 of the all-pass filter processing unit 501 is realized.

In step S1207, the register (S
R) addition result W (A4) + P (A set to 224)
1A) × E (EA) is set in the register (EO) 229. Further, the adder 227 adds the write delay offset T (AWA) read from the delay offset memory (T) 205 to the sampling counter value SC, and sets it in the register (EA) 228.

In the same step S1207, the coefficient P (A2A) is read from the coefficient memory (P) 203,
The value set in the register (M0) 212 and the addition result W (A4) + P (A1A) × E (EA) set in the register (SR) 224 are multiplied by the multiplier 216. , The multiplication result is a register (M
R) 221 is set. By these processes, FIG.
#A all-pass filter processing unit 501 multiplier 505
The function equivalent to the processing in (1) is realized.

At the same step S1207, the delay memory (E) set in the register (A0) 214 is set.
The waveform data E (EA) from 106 at the sampling timing before the present is transferred to the register (A1) 215.

In the following step S1208, the addition result W (A4) set in the register (EO) 229 is set.
+ P (A1A) × E (EA) is the register (EA) 22
The value set to 8 is used as an address and is stored in the delay memory (E) 106 as a new storage value E (EA). By this processing, processing equivalent to the function of storing the output of the adder 506 of the all-pass filter processing unit 501 of #A in FIG. 5 in the delay element 508 is realized.

In the same step S1208, the delay memory (E) set in the register (A1) 215 is set.
The waveform data E (EA) from the sampling timing 106 before the present and the multiplication result {W (A4) + P (A1A) × E set in the register (MR) 221.
(EA)} × P (A2A) is added by the adder / subtractor 217, and the addition result is set in the register (AR) 222. By this processing, processing equivalent to the function of the adder 507 of the all-pass filter processing unit 501 of #A in FIG. 5 is realized.

After the above addition result is transferred to the register (SR) 224 in step S1209, it is further processed in step S1.
Variable value W (A5) in work memory (W) 204 at 210
Is stored as By this processing, processing equivalent to the function of outputting data from the adder 507 of the all-pass filter processing unit 501 of #A in FIG. 5 is realized.

Next, FIG. 13 shows step S11 of FIG.
It is an operation flowchart of the comb filter process (# A-1) of 02. First, in step S1301, in the adder 227, the read delay offset T read from the delay offset memory (T) 205 is added to the counter value SC generated from the control circuit 202 at each sampling timing.
(CR1A1) (see FIG. 19) is added, and the added value is set in the register (EA) 228 as an address value.

In step S1302, the delay memory (E) 106 is accessed by the address value set in the register (EA) 228 as described above, and the waveform data E written at the sampling timing earlier than the present is accessed from the address. (EA) is read and the register (EI)
It is stored in 230.

In step S1303, the adder 227 adds the read delay offset T (CR1A2) (see FIG. 19) read from the delay offset memory (T) 205 to the counter value SC from the control circuit 202, This added value is set in the register (EA) 228 as a new address value.

In the same step S1303, step S
The waveform value E (EA) stored in the register (EI) 230 by the processing of 1302 is stored in the register (M0) 212.
Transferred to. At the same time, the coefficient P (C1A) is read from the coefficient memory (P) 203, and the register (M1) 2
Set to 13.

In step S1304, step S13
03, the delay memory (E) 106 is newly accessed with the address value set in the register (EA) 228,
The waveform data E (EA) written at the sampling timing earlier than the present is read from the address and stored in the register (EI) 230.

In the same step S1304, step S
The waveform value E (EA) read from the delay memory (E) 106 by the processing of 1302 and set in the register (M0) 212 and the coefficient P (C1A) set in the register (M1) 213 are , Multiplier 216, and the multiplication result is set in the register (MR) 221. By this process, the comb filter processing unit (#A
A process equivalent to the function of the multiplier 509-1 of -1) is realized.

Further, in step S1304, the variable value W (A5) is read from the work memory (W) 204 and set in the register (A1) 215. Also, step S
In 1305, the register (EI) 2 read from the delay memory (E) 106 by the process of step S1304.
The waveform value E (EA) set to 30 is transferred to the register (A0) 214.

In the same step S1305, the multiplication result corresponding to the processing result of the multiplier 509-1 (see FIG. 5) set in the register (MR) 221 and #A set in the register (A1) 215. The variable value W (A5) corresponding to the output from the all-pass filter processing unit 501 (see FIG. 5) is added by the adder / subtractor 217, and the addition result is set in the register (AR) 222. In step S1306, the register (SR) 224
Moved to. By this processing, processing equivalent to the function of the adder 510-1 of the comb filter processing unit 502 (# A-1) in FIG. 5 is realized.

In step S1307, the adder 227 adds the write delay offset T (CW1A) read from the delay offset memory (T) 205 to the sampling counter value SC and adds it to the register (EA) 22.
Set to 8. Further, the addition result corresponding to the adder 510-1 (see FIG. 5) set in the register (SR) 224 is set in the register (EO) 229. Then, in step S1308, this addition result is set as a new storage value E (EA) using the value set in the register (EA) 228 as an address, and the delay memory (E)
It is stored in 106. By this processing, processing equivalent to the function of storing the output of the adder 510-1 of the comb filter processing unit 502 (# A-1) of FIG. 5 in the delay element 512-1 is realized.

In step S1309, the register (S
The addition result corresponding to the adder 510-1 (see FIG. 5) set in (R) 224 is set in the register (A1) 215. Then, in step 1310, the addition result set in the register (A1) 215 and step S130 set in the register (A0) 214.
The waveform value E (EA) read from the delay memory 106 by the processing of 4 is added by the adder / subtractor 217, and the addition result is set in the register (AR) 222. The result of this addition is further registered in the register (S
R) 224. By these processes, a process equivalent to the function of the adder 511-1 of the comb filter processing unit 502 (# A-1) in FIG. 5 is realized.

Further, the addition result set in the register (SR) 224 is written in the work memory (W) 204 as a variable value W (A6) in step S1312. By this processing, the comb filter processing unit 502 of FIG.
A process equivalent to the function of outputting data from the (# A-1) adder 511-1 is realized.

Next, steps S1103 and S1 in FIG.
The operations of the comb filter processing (# A-2) and (# A-3) of 104 can be considered similar to the operation of the comb filter processing (# A-1) based on the operation flowchart of FIG. 13 described above. In these cases, the delay offset memory (T) 205
Read delay offset T (CR1A
1) and T (CR1A2) are respectively T (CR2A1)
And T (CR2A2), T (CR3A1) and T (CR3A
2). Similarly, write delay offset T
(CW1A) is T (CW2A), T (CW3)
A). Further, the coefficient P (C1A) is replaced with P (C2A) and P (C3A), respectively.
Further, the output variable value W (A6) is W (A6).
7) and W (A8).

As described above, the outputs W (A6) and W (A7) corresponding to the comb filter processing units 502 (# A-1), (# A-2) and (# A-3) shown in FIG. ), W (A8) are obtained.
FIG. 14 is an operation flowchart of the reverb mixing process (#A) in step S1105 of FIG.

First, in step S1401, the variable value W (A6) held in the work memory (W) 204 is read and set in the register (A0) 214, and similarly, the variable value W (A7) is read. Issued to register (A1) 2
Set to 15. Then, in step S1402,
The contents of these two registers are added by the adder / subtractor 217, and the addition result is set in the register (AR) 222. By these processes, a process equivalent to the function of the adder 513 of the reverb mixing processing unit 503 (#A) in FIG. 5 is realized.

Next, in step S1403, the addition result obtained in the register (AR) 222 is stored in the register (A
1) Set to 215. Also, work memory (W)
The variable value W (A8) is read from 204 and set in the register (A0) 214. And step S1
At 404, the contents of these two registers are added / subtracted by the adder / subtractor 2
17 and the addition result is registered in the register (AR) 22.
Is set to 2, and the result of this addition is step S14.
After being transferred to the register (SR) 224 at 05, it is written in the work memory (W) 204 as the variable value W (A9). By these processes, a process equivalent to the function of the adder 514 of the reverb mixing processing unit 503 (#A) in FIG. 5 is realized. <Bandpass Filter Processing (#B) and (#C), Reverb Processing (#B) and (#C)> The bandpass filter processing (#A) in step S602 and the reverb processing in step S603 in FIG. Although (#A) has been described based on the operation flowcharts of FIGS. 8 to 13, step S60 of FIG.
The operations of the band pass filter process (#B), the reverb process (#B), the band pass filter process (#C), and the reverb process (#C) in 4 to S607 are also described in FIG.
It can be considered similarly to each operation based on the operation flowchart of FIG.

In this case, in the bandpass filter processing (#B) of step S604 of FIG. 6, the subscript #A is replaced with #B in each operation flowchart of FIGS. 8 to 10, and each multiplication coefficient P (L1A) is replaced. , P (L2A), P (L3A),
P (H1A), P (H2A), and P (H3A) are P (L1B), P (L2B), P (L3B), P (H
1B), P (H2B), and P (H3B) (see FIG. 17), and further, variable values W (A1), W (A
2), W (A3), and W (A4) are each W (B
1), W (B2), W (B3), and W (B4) are realized (see FIG. 18).

Similarly, in the bandpass filter processing (#C) of step S606 of FIG. 6, the subscript #A is replaced with #C in each operation flowchart of FIGS. 8 to 10, and each multiplication coefficient P (L1A) is replaced. , P (L2A), P (L3A), P
(H1A), P (H2A), and P (H3A) are respectively P (L1C), P (L2C), P (L3C), P (H1
C), P (H2C), and P (H3C) (see FIG. 17), and further, variable values W (A1), W (A
2), W (A3), and W (A4) are each W (C
1), W (C2), W (C3), and W (C4) are replaced (see FIG. 18).

On the other hand, in the reverb processing (#B) of step S605 of FIG. 6, the subscripts #A, # A-1, # A-2, and # A-3 in the operation flowcharts of FIGS. , Each #B,
Replaced with # B-1, # B-2, and # B-3, each multiplication coefficient P
(A1A), P (A2A), P (C1A), P (C2
A) and P (C3A) are P (A1B) and P (A
2B), P (C1B), P (C2B), and P (C3
B) (see FIG. 17), and each variable value W (A
5), W (A6), W (A7), W (A8), and W
(A9) is W (B5), W (B6), W (B
7), W (B8), and W (B9) (see FIG. 18), and delay offsets T (ARA), T
(AWA), T (CR1A1), T (CR1A2), T
(CW1A), T (CR2A1), T (CR2A2),
T (CW2A), T (CR3A1), T (CR3A
2) and T (CW3A) are respectively T (ARB), T
(AWB), T (CR1B1), T (CR1B2), T
(CW1B), T (CR2B1), T (CR2B2),
T (CW2B), T (CR3B1), T (CR3B
2) and T (CW3B) are replaced with the processing (see FIG. 19). Similarly, step S in FIG.
The reverb processing (#C) of 607 corresponds to the subscripts #A, # A-1, # A-2, and # A-2 in the operation flowcharts of FIGS.
# A-3 is replaced with #C, # C-1, # C-2, and # C-3, respectively, and each multiplication coefficient P (A1A), P (A2A), P (C1
A), P (C2A), and P (C3A) are each P (A
1C), P (A2C), P (C1C), P (C2C),
And P (C3C) (see FIG. 17), and each variable value W (A5), W (A6), W (A7), W (A
8) and W (A9) are W (C5) and W (C
6), W (C7), W (C8), and W (C9) (see FIG. 18), and the delay offset T (A
RA), T (AWA), T (CR1A1), T (CR1
A2), T (CW1A), T (CR2A1), T (CR
2A2), T (CW2A), T (CR3A1), T (C
R3A2) and T (CW3A) are respectively T (AR
C), T (AWC), T (CR1C1), T (CR1C
2), T (CW1C), T (CR2C1), T (CR2
C2), T (CW2C), T (CR3C1), T (CR
3C2) and T (CW3C) are replaced (see FIG. 19). <Mixing Process> FIG. 15 shows step S608 in FIG.
5 is an operation flowchart of the mixing process of FIG.

First, in step S1501, the variable value W (A9) held in the work memory (W) 204 is read and set in the register (A0) 214, and similarly, the variable value W (B9) is read. Issued to register (A1) 2
Set to 15. Then, in step S1502,
The contents of these two registers are added by the adder / subtractor 217, and the addition result is set in the register (AR) 222.

Next, in step S1503, the addition result obtained in the register (AR) 222 is stored in the register (A
1) Set to 215. Also, work memory (W)
The variable value W (C9) is read from 204 and set in the register (A0) 214. And step S1
At 504, the contents of these two registers are added and subtracted by the adder / subtractor 2.
17 and the addition result is registered in the register (AR) 22.
Is set to 2, and the result of this addition is step S15.
After being transferred to the register (SR) 224 in 05, it is written in the work memory (W) 204 as a variable value W (OUT).

The variable value W (OU
T) is each reverb mixing processing unit 3 of #A, #B and #C in FIG.
Variable values W (A9), W (B9) corresponding to each output of 02
And the results of mixing W (C9) are shown. <Output Processing> FIG. 16 shows step S609 in FIG.
3 is an operation flowchart of the output processing of FIG.

In this processing, step S1601
15, the variable value W (OUT) obtained in the work memory (W) 204 by the mixing process of FIG. 15 is transferred to the output register (OR) 225, and from the same register, the D / A converter of FIG. It is output to 107 as an output Eo.

As described above, the DSP 105 of FIG. 1 having the circuit configuration of FIG. 2 repeats the processing program shown in the operation flowcharts of FIGS. The function of each processing unit is realized. Concrete Operation of CPU Finally, the operation of the CPU 101 of FIG. 1 will be described.

In FIG. 20, the CPU 101 is the ROM of FIG.
3 is an operation flowchart realized as an operation of executing a control program stored in 102. First, when the power of the device is turned on, in step S2001, C
Contents of various registers in the PU 101 and the RAM 103 are cleared or initialized.

Next, in step S2002, the process waits until the user operates any switch on the console section 104, and when the switch is operated, step S2003.
, Various setting contents for adding reverberation set by the switch operation, that is, various coefficient values P (see FIG. 17).
DS) and delay offset T (see FIG. 19)
It is set in the coefficient memory (P) 203 and the delay offset memory (T) 205 in P105.

[0102]

According to the present invention, after dividing an acoustic signal into signals in a plurality of frequency bands, different acoustic effects can be added to the acoustic signals in the respective bands.

Therefore, the reverberation of a music hall or the like having different reverberation characteristics depending on the frequency band can be added with a natural feeling.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a DSP.

FIG. 3 is a block diagram of the operating principle of the DSP.

FIG. 4 is a block diagram of an operation principle of a bandpass filter processing unit (#A).

FIG. 5 is a block diagram of an operation principle of a reverb processing unit (#A).

FIG. 6 is an overall operation flowchart of the DSP.

FIG. 7 is an operation flowchart of input processing.

FIG. 8 is an operation flowchart of bandpass filter processing (#A).

FIG. 9 is an operation flowchart of low-pass filter processing (#A).

FIG. 10 is an operation flowchart of high-pass filter processing (#A).

FIG. 11 is an operation flowchart of reverb processing (#A).

FIG. 12 is an operation flowchart of all-pass filter processing (#A).

FIG. 13 is an operation flowchart of comb filter processing (# A-1).

FIG. 14 is an operation flowchart of reverb mixing processing (#A).

FIG. 15 is an operation flowchart of mixing processing.

FIG. 16 is an operation flowchart of output processing.

FIG. 17 is a diagram showing a coefficient memory map.

FIG. 18 is a diagram showing a work memory map.

FIG. 19 is a diagram showing a delay offset memory map.

FIG. 20 is an operation flowchart of the CPU.

[Explanation of symbols]

 101 CPU 102 ROM 103 RAM 104 Console Unit 105 DSP 106 Delay Memory 107 A / D Converter 108 D / A Converter

Claims (3)

[Claims] 1. A band division unit for dividing an input acoustic signal into a plurality of band division acoustic signals each having a different frequency band, and each of the band division acoustic signals output from the band division unit. Band-specific sound effect adding means for adding a sound effect, and mixing output means for mixing and outputting each of the band-divided sound signals to which the sound effect has been added by the band-specific sound effect adding means. Effect adding device. 2. The effect adding device according to claim 1, wherein the band dividing unit executes a plurality of band pass filtering processes each having a different pass band. 3. The effect adding device according to claim 1, wherein the sound effect adding means for each band executes a plurality of reverberant effect adding processes each having a different reverberation characteristic. ..