JPH05167066A - New quantum-well switching element having exciting and emitting capability - Google Patents

New quantum-well switching element having exciting and emitting capability

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Publication number
JPH05167066A
JPH05167066A JP4064663A JP6466392A JPH05167066A JP H05167066 A JPH05167066 A JP H05167066A JP 4064663 A JP4064663 A JP 4064663A JP 6466392 A JP6466392 A JP 6466392A JP H05167066 A JPH05167066 A JP H05167066A
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Japan
Prior art keywords
layer
quantum well
type
region
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4064663A
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Other versions
JPH07118566B2 (en
Inventor
Szutsun S Ou
シモン オウ ズットサン
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Northrop Grumman Space and Mission Systems Corp
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TRW Inc
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Publication of JPH07118566B2 publication Critical patent/JPH07118566B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00Nanooptics, e.g. quantum optics or photonic crystals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035236Superlattices; Multiple quantum well structures
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    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101Devices sensitive to infrared, visible or ultraviolet radiation
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    • H01S5/00Semiconductor lasers
    • H01S5/06Arrangements for controlling the laser output parameters, e.g. by operating on the active medium
    • H01S5/062Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying the potential of the electrodes
    • H01S5/06203Transistor-type lasers
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    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
    • H01S5/34Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
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    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
    • H01S5/305Structure or shape of the active region; Materials used for the active region characterised by the doping materials used in the laser structure
    • H01S5/3054Structure or shape of the active region; Materials used for the active region characterised by the doping materials used in the laser structure p-doping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
    • H01S5/305Structure or shape of the active region; Materials used for the active region characterised by the doping materials used in the laser structure
    • H01S5/3095Tunnel junction
    • HELECTRICITY
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    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
    • H01S5/32Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/3211Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures characterised by special cladding layers, e.g. details on band-discontinuities
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    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
    • H01S5/34Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/343Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/34313Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer having only As as V-compound, e.g. AlGaAs, InGaAs
    • H01S5/3432Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer having only As as V-compound, e.g. AlGaAs, InGaAs the whole junction comprising only (AI)GaAs
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/919Elements of similar construction connected in series or parallel to average out manufacturing variations in characteristics

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Abstract

PURPOSE: To provide a diode switching element of semiconductor-insulator- semiconductor structure having a possibility of higher rate optoelectronic switching and exhibiting a good laser performance, a prominent negative differential resistance and a high sensitivity. CONSTITUTION: A buffer layer 14 is formed on a GaAs substrate 12, and an n-type clad layer 16 is formed on the buffer layer 14 and an undoped i-region is provided thereon. The i-region includes first and second quantum well layers 20, 24 isolated by a quantum well barrier layer 22 provided between two waveguide layers 18, 26 and it must include at least one quantum well. A lightly doped p-type clad layer 28 is provided on the top of the i-region and a connection layer 30 is provided thereon. Furthermore, first and second connection terminals 36, 38 are provided thus obtaining a two terminal element. A diode thus obtained has good laser emission properties, a prominent negative differentiation resistance and a high optical sensitivity.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体−絶縁体−半導体
(SIS)構造ダイオードに関し、特に励起放出能力を
有する新規量子井戸オプトエレクトロスイッチング素子
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor-insulator-semiconductor (SIS) structure diode, and more particularly to a novel quantum well optoelectroswitching device having a pumping emission capability.

【0002】[0002]

【従来の技術】マイクロ波半導体素子は一般に高周波数
電磁波エネルギーの発生、増幅、検出及び制御に一般に
使用されている。しかしながら、比較的高い周波数では
従来の半導体素子の有用性は、高周波数効果によって厳
しく制限されている。シリコン以外のガリウム砒素(G
aAs)又はインジウム燐の様なIII-V族化合物の使用
は著しい改善を与える。これは、これらの材料の電子の
移動度はシリコンよりも数倍高く、より低い直列抵抗を
もたらすためである。
Microwave semiconductor devices are commonly used in the generation, amplification, detection and control of high frequency electromagnetic energy. However, at relatively high frequencies, the usefulness of conventional semiconductor devices is severely limited by the high frequency effects. Gallium arsenide other than silicon (G
The use of III-V compounds such as aAs) or indium phosphide gives a significant improvement. This is because the electron mobility of these materials is several times higher than that of silicon, resulting in lower series resistance.

【0003】励起放出を呈する種々のオプトエレクトロ
スイッチング素子が開発されている。この様な素子は、
マイクロ波発生、高速度論理スイッチ、集積回路様の光
学的相互接続、光計算システム及びオプトエレクトロ集
積回路(OEIC)における潜在的な応用のために、魅
力的なものとなっている。二重バリヤー共鳴トンネルダ
イオードは、量子井戸(QW)レーザーと単一結晶とし
て一体化されており、光双安定素子を形成している。単
一量子井戸レーザーと組み合わさった二重ヘテロ接続構
造オプトエレクトロスイチッング(DOES)素子及び
表面垂直伝播エレクトロホトニック(VSTEP)素子
が、励起放出を達成するレーザーとして実証されてい
る。しかしながら、pn接合の存在のために、これらの
素子の効率及びパワーが制限されていることが分かっ
た。更に、オプトエレクトロスイッチング素子構造の多
くはOEICと両立できない、従って、OEICに容易
には組み込むことができない。
Various optoelectroswitching devices have been developed that exhibit stimulated emission. Such elements are
It is attractive for potential applications in microwave generation, high speed logic switches, integrated circuit-like optical interconnects, optical computing systems and optoelectronic integrated circuits (OEICs). The double barrier resonant tunneling diode is integrated as a single crystal with a quantum well (QW) laser to form an optical bistable element. Double heterojunction structure optoelectroswitching (DOES) devices and surface vertical propagation electrophotonic (VSTEP) devices in combination with single quantum well lasers have been demonstrated as lasers to achieve pumped emission. However, the existence of pn junctions has been found to limit the efficiency and power of these devices. Moreover, many opto-electro switching device structures are not compatible with OEICs and therefore cannot be easily incorporated into OEICs.

【0004】従って、より高速なオプトエレクトロスイ
ッチングの可能性を有するオプトエレクトロスイッチン
グ素子を得ることが望まれる。更に、良好なレーザー性
能、顕著な負微分抵抗及び強い感度を呈する素子を得る
ことが望まれる。更に、OEIC技術と互換性のある素
子を得ることが望まれる。
Therefore, it is desirable to have an optoelectroswitching device that has the potential for faster optoelectroswitching. Furthermore, it is desirable to have devices that exhibit good laser performance, significant negative differential resistance and strong sensitivity. Furthermore, it is desirable to have devices that are compatible with OEIC technology.

【0005】[0005]

【発明の要約】本発明の教えに従って、SIS構造ダイ
オードが提供される。このダイオードは頂部にバッファ
ー層が設置された基板を有する。n型クラッド層は、バ
ッファー層の頂部に設置される。非ドープi領域がバッ
ファー層の頂部に設置されている。i領域は、2つの導
波層間に設置された少なくとも一つの量子井戸を含む。
軽くドープされたp型クラッド層はi領域の頂部に設置
される。接続層は更にo型クラッド素子の頂部に設置さ
れる。
SUMMARY OF THE INVENTION In accordance with the teachings of the present invention, a SIS structure diode is provided. The diode has a substrate with a buffer layer on top. The n-type cladding layer is placed on top of the buffer layer. The undoped i-region is located on top of the buffer layer. The i-region includes at least one quantum well located between two waveguiding layers.
The lightly doped p-type cladding layer is placed on top of the i region. The connection layer is further placed on top of the o-type cladding element.

【0006】[0006]

【実施例】図1に戻る。複数の作成層を有するガリウム
砒素(GaAs)/ガリウムアルミニュウム砒素(Ga
AlAs)半導体−絶縁体−半導体SIS構造ダイオー
ド10が示されている。GaAs/GaAlAs SI
S構造ダイオード10は、本質的に、室温でs型負微分
抵抗を呈し、高性能励起放出を行うオプトエレクトロス
イッチング素子である。この素子は2端子素子10であ
ってもよいし、更に3端子素子としても構成することが
できる。素子は光学的及び/又は電気的にスイッチさ
れ、光又は電気的出力を発生する。この素子構造は従来
の分離監禁ヘテロ接合量子井戸レーザーと似ており、従
って容易にオプトエレクトロ集積回路と集積化すること
ができる。
EXAMPLE Returning to FIG. Gallium arsenide (GaAs) / gallium aluminum arsenide (Ga) having a plurality of fabrication layers
An AlAs) semiconductor-insulator-semiconductor SIS structure diode 10 is shown. GaAs / GaAlAs SI
The S-structure diode 10 is essentially an opto-electro switching device that exhibits s-type negative differential resistance at room temperature and performs high-performance stimulated emission. This element may be a two-terminal element 10 or may be a three-terminal element. The element is optically and / or electrically switched to produce an optical or electrical output. This device structure resembles a conventional separate confinement heterojunction quantum well laser, and thus can be easily integrated with an optoelectronic integrated circuit.

【0007】GaAs/GaAlAs SIS構造ダイ
オード10は基板12を含む。基板12は強くドープさ
れたn+ GaAsを含む。n+ 型GaAsバッファー層
14は基板12の頂部に設置されている。バッファー層
14は、約1.0マイクロメータ厚であり、6×1018cm
-3の濃度のSe ドーピングを含む。このバッファー層
14は本質的に基板12を平滑にする。GaAlAsク
ラッド層16はバッファー層14の頂部に設置される。
n型クラッド層16はGa0.6 Al0.4 Asから形成さ
れ、4×1018 cm -3の濃度のSe ドーピングされた約
1.2マイクロメータ厚である。
The GaAs / GaAlAs SIS structure diode 10 includes a substrate 12. Substrate 12 comprises heavily doped n + GaAs. The n + type GaAs buffer layer 14 is provided on the top of the substrate 12. The buffer layer 14 is about 1.0 micrometer thick and has a size of 6 × 10 18 cm.
-3 with Se doping. This buffer layer 14 essentially smoothes the substrate 12. The GaAlAs cladding layer 16 is provided on top of the buffer layer 14.
The n-type cladding layer 16 is formed of Ga 0.6 Al 0.4 As and is doped with Se at a concentration of 4 × 10 18 cm -3.
It is 1.2 micrometers thick.

【0008】非ドープのi領域はクラッド層16の頂部
上に設置されている。i領域は非ドープGa0.8 Al
0.2 Asからなる第1の導波層18を含む。第1の導波
層18は、励起放出に対するガイドを与え、約700オ
ングストローム厚である。第1の非ドープGaAs量子
井戸20が、第1の導波層18の頂部に設置される。第
1の量子井戸20は約700オングストローム厚であ
る。GaAlAs量子井戸バリヤー層22は量子井戸2
0の頂部に設置される。量子井戸バリヤー層22は約9
0オングストローム厚である。第2のGaAs量子井戸
24は、量子井戸バリヤー層22の頂部設置されてい
る。第2の井戸24は約70オングストローム厚であ
る。非ドープGa0.8 Al0.2 Asからなる第2の導波
層26が更に第2の量子井戸24の頂部に設置される。
第2の導波層26は約700オングストローム厚であ
り、同様に励起放出に対するガイドを与える。
The undoped i region is located on top of the cladding layer 16. i region is undoped Ga 0.8 Al
It includes a first waveguiding layer 18 of 0.2 As. The first waveguiding layer 18 provides a guide for stimulated emission and is about 700 Å thick. A first undoped GaAs quantum well 20 is placed on top of the first waveguiding layer 18. The first quantum well 20 is about 700 Å thick. The GaAlAs quantum well barrier layer 22 is the quantum well 2
It is installed on the top of 0. The quantum well barrier layer 22 is about 9
It is 0 angstrom thick. The second GaAs quantum well 24 is provided on top of the quantum well barrier layer 22. The second well 24 is about 70 angstroms thick. A second waveguiding layer 26 of undoped Ga 0.8 Al 0.2 As is further placed on top of the second quantum well 24.
The second waveguiding layer 26 is approximately 700 Å thick and also provides a guide for stimulated emission.

【0009】図1に示されるi領域は、量子井戸バリア
ー層22によって分離された第1及び第2の量子井戸層
20及び24を含んでいる。本発明のためには、i領域
は少なくとも一つの量子井戸層を含んでいることのみが
要求される。一つのみの量子井戸が与えられる場合、量
子井戸バリアー層は必要とされない。しかしながら、2
以上の量子井戸層が含まれる場合、量子井戸層は量子井
戸バリアー層によって分離されることが必要とされる。
The i region shown in FIG. 1 includes first and second quantum well layers 20 and 24 separated by a quantum well barrier layer 22. For the purposes of this invention, the i-region need only include at least one quantum well layer. If only one quantum well is provided, no quantum well barrier layer is needed. However, 2
When the above quantum well layers are included, the quantum well layers need to be separated by the quantum well barrier layer.

【0010】i領域の頂部にには、Ga0.6 Al0.4
sからなるp- 型GaAlAsクラッド層28である。
- 型クラッド層28は、5×1015−1016 cm -3
濃度のZn ドーピングで軽くドープされている。p-
クラッド層28は約1.2マイクロメーター厚さである。
- 型クラッド層28は、励起放出を閉じ込め、ホール
に対するバリアーを構成し、ホールが、低バイアス状態
で再結合できない様にする。
At the top of the i region, Ga 0.6 Al 0.4 A
It is a p -type GaAlAs cladding layer 28 made of s.
The p - type cladding layer 28 is lightly doped with Zn doping at a concentration of 5 × 10 15 -10 16 cm -3 . The p - type cladding layer 28 is about 1.2 micrometers thick.
The p -type cladding layer 28 confines the stimulated emission and constitutes a barrier to the holes, preventing the holes from recombining under low bias conditions.

【0011】p+ 型GaAs接続層30が、p- 型クラ
ッド層28の頂部に設置されている。p型接続層30は
約0.5ミクロン厚であり、Zn で強くドープされて、オ
ーミック接続により良好なトンネルオーミック接続を保
証する。p型オーミック接続層32は、p型接続端子3
6を有する接続層30の頂部に設置されて、外部素子と
の接続を可能としている。p型オーミック接続層32は
Ti −Pt −Auの様な導電性材料を含む。これとは別
に、p+ 型接続層30及びP型オーミック接続層32
は、n+ 型接続及びオーミック接続層と置き換えること
ができる。同様に、n型接続端子38を有するn型オー
ミック接続層34は、接続を外部接続に与えるために、
構造ダイオード10の底部に設置される。n型オーミッ
ク接続層34はNi−AuGe−Ni−Auの様な導電
性材料を含む。
A p + type GaAs connection layer 30 is provided on top of the p type cladding layer 28. The p-type connection layer 30 is about 0.5 micron thick and is heavily doped with Zn to ensure a good tunnel ohmic contact with the ohmic connection. The p-type ohmic connection layer 32 includes the p-type connection terminal 3
It is placed on top of the connection layer 30 having 6 to allow connection with external elements. The p-type ohmic connection layer 32 contains a conductive material such as Ti-Pt-Au. Separately from this, the p + type connection layer 30 and the P type ohmic connection layer 32
Can be replaced by n + type connection and ohmic connection layers. Similarly, the n-type ohmic connection layer 34 having the n-type connection terminal 38 is provided to provide a connection to an external connection.
It is installed at the bottom of the structural diode 10. The n-type ohmic connection layer 34 includes a conductive material such as Ni-AuGe-Ni-Au.

【0012】一般的に、結果として得られるダイオード
構造10は、本OEICと集積化することができる従来
の分離隔離ヘテロ結合量子井戸構造と類似する4つの層
+ −i−p- 構造である。このn+ −i−p- 構造
は、金属−絶縁体−半導体(MIS)形態のコンデンサ
ーと同様にして振る舞う、半導体−絶縁体−半導体(S
I)形態コンデンサーである。p- −p+ 構造はGaA
s/GaAlAsヘテロ接合である。従って、このダイ
オード構造素子は、SIS及びp- −p+ GaAs/G
aAlAsヘテロ接合コンデンサーである2つの接合を
含む。ダイオードキ構造素子10は、湿式化学エッチン
グ、反応性イオンエッチング、イオンビームエッチング
及び他の乾式エッチング技術の様な公知の従来技術によ
って製造することができる。
[0012] In general, the diode structure 10 obtained as a result, the four layers n + -i-p similar the OEIC and conventional separation isolation heterojunction quantum well structure can be integrated - a structure in .. The n + -i-p - structure, metal - behave in the same manner as the semiconductor (MIS) form the capacitor, the semiconductor - - insulator insulator - semiconductor (S
I) Form condenser. p −p + structure is GaA
s / GaAlAs heterojunction. Therefore, this diode structure element has SIS and p -- p + GaAs / G
It includes two junctions that are aAlAs heterojunction capacitors. The diode structure element 10 can be manufactured by known conventional techniques such as wet chemical etching, reactive ion etching, ion beam etching and other dry etching techniques.

【0013】図2は本発明の別の実施例に従うGaAs
/GaAlAs SIS構造ダイオード10’を図示し
ている。構造ダイオード10’は、ダイオード構造1
0’が非ドープの半絶縁GaAs基板12’を含むこと
を除いて、図1で示されるダイオード構造10と同じ手
法で製造又は構成される。半絶縁GaAs基板12’は
寄生容量を減少し、より高速な動作を与え、従ってより
高性能を与える。更に、n型オーミック接続層34は、
バッファー層14の頂部に設置され、素子10’の他の
層から分離されている。
FIG. 2 illustrates GaAs according to another embodiment of the present invention.
A / GaAlAs SIS structure diode 10 'is illustrated. The structure diode 10 'is the diode structure 1
It is manufactured or constructed in the same manner as the diode structure 10 shown in FIG. 1, except that 0'includes an undoped semi-insulating GaAs substrate 12 '. The semi-insulating GaAs substrate 12 'reduces parasitic capacitance and provides faster operation and thus higher performance. Furthermore, the n-type ohmic connection layer 34 is
It is placed on top of buffer layer 14 and is separated from the other layers of device 10 '.

【0014】図3は、本発明の別の実施例に従う3端子
素子40を示している。この3端子素子40は、第3の
端子が加えられ、トランジスタとして知られる3端子素
子を形成することを除いて、図2に示される素子10’
と同様の手法で構成される。別の第3の端子42は、i
領域の層内に注入されたSi イオンを含む。第3の端子
42はトランジスタ様のゲートを形成し、オーミック層
44を介してイオン注入部に接続される。p型接続層端
子36は、3端子素子40のエミッター端子を形成す
る。n型接続端子38は、3端子素子40のn型接続コ
レクタを形成する。
FIG. 3 illustrates a three terminal device 40 according to another embodiment of the present invention. This three terminal device 40 is the device 10 'shown in FIG. 2 except that a third terminal is added to form a three terminal device known as a transistor.
It is constructed by the same method as. Another third terminal 42 is i
It contains Si ions implanted in the layers of the region. The third terminal 42 forms a transistor-like gate and is connected to the ion implantation part via the ohmic layer 44. The p-type connection layer terminal 36 forms the emitter terminal of the three-terminal element 40. The n-type connection terminal 38 forms the n-type connection collector of the three-terminal element 40.

【0015】図1から3に、励起放出をもたらすオプト
エレクトロスイッチング素子が、図示されている。素子
は2つのダイオードとして構成された端子素子10とし
て構成することができる。第3の端子に加えて、素子は
3端子素子として構成され、トランジスタを形成するこ
とができる。素子のスイッチング機構が、図4aから4
cに示されるエネルギーバンド図によって示される。図
4aは、熱均衡にあるエネルギーバンド図を図示してい
る。非ドープi領域の導電率が、逆バイアスされたp+
GaAs/p- GaAlAs(p+ /p- )接続52の
ものより大きい場合、印加電圧の多くがp+ /p- 接続
52を横切って降下する。逆バイアス下の素子の電流対
電圧(I−V)特性は従って逆バイアスされたpn接合
と同様に振る舞う。
1 to 3 show an optoelectroswitching element that provides stimulated emission. The element can be configured as a terminal element 10 configured as two diodes. In addition to the third terminal, the element can be configured as a three terminal element to form a transistor. The switching mechanism of the device is shown in FIGS.
This is shown by the energy band diagram shown in c. Figure 4a illustrates an energy band diagram in thermal equilibrium. The conductivity of the undoped i region is reverse biased to p +
If greater than that of the GaAs / p GaAlAs (p + / p ) connection 52, much of the applied voltage will drop across the p + / p connection 52. The current-to-voltage (IV) characteristic of the device under reverse bias thus behaves similarly to a reverse biased pn junction.

【0016】図4bは順バイアスを与えた結果を図示し
ている。順バイアスが増加する時、自由電子がp+ /p
- 接合52を介してp- 領域から掃き出され、空乏層5
8が成長する。電子ホール対が空乏層58内で発生され
る。これは電子がp+ /p- 接合52を介して掃き出さ
れ、ホールが、p- GaAlAs/非ドープGaAlA
s(p- /i)界面へ掃き出される。結果として、発生
されたホールは(p- /i)界面54に集積される。こ
れらの状態下で、ホールは、広帯域ギャップバリアーを
介して非ドープi領域には注入できない。更に、電子は
重大な電圧降下及び空乏領域58及び非ドープi領域を
横切る大きな直列抵抗を結果するバリアーを介するトン
ネリングによって制限される。結果として、これらの領
域は従って電位の多くを吸収し、高電位、低電流、オフ
状態とは異なる電流の流れを与える。
FIG. 4b illustrates the result of applying a forward bias. When the forward bias increases, the free electrons become p + / p
- p through the junction 52 - swept out from the region, the depletion layer 5
8 grows. Electron hole pairs are generated in the depletion layer 58. This is because the electrons are swept out through the p + / p junction 52 and the holes are p GaAlAs / undoped GaAlA.
Swept to the s (p / i) interface. As a result, the generated holes accumulate at the (p / i) interface 54. Under these conditions, holes cannot be injected into the undoped i-region through the wide band gap barrier. Further, the electrons are limited by tunneling through the barrier resulting in significant voltage drop and large series resistance across the depletion region 58 and the undoped i region. As a result, these regions therefore absorb much of the potential, providing a high potential, low current, different current flow than in the off state.

【0017】順バイアスが増加する時、p+ /p- 接合
52を流れるホール電流は(p- /i)界面54のホー
ルの凝集と共に増大する。ホールの凝集は、空乏領域5
8内の電子ホール対の熱及び又は光発生を促進する。こ
の凝集は、またp+ /p- 接合52のパンチスルー、p
- 層のアバランシェ、及び/又はn+ /i接合56から
の初期電子トンネル電流によって生じる場合もある。ホ
ール凝集及びホール電流の増加はn型GaAlAs/非
ドープGaAlAs(n+ /i)接合56を介する電子
電流の増加をもたらす。この増大電子電流はp+ /p-
接合52へフィールドバックし、p+ /p- 接合52を
介して流れる電子及びホール電流を増大する。p+ /p
- 接合52を介して流れるホール電流は、空乏領域58
内の発生電流よりも大きい時、内部電流ループ利得は、
1を越える。電流ループのフィードバックは従って正に
なり、再生スイッチングを増大する。この再生過程の結
果として、電圧が低下し、電流が増加する様なs型負微
分抵抗(NDR)を素子が表示する。この状態におい
て、p+/p- 接合52及びn+ /i接合56は、図4
Cに示される様に強く順方向にバイアスされる。
When the forward bias increases, the hole current flowing through the p + / p junction 52 increases with the aggregation of holes at the (p / i) interface 54. The aggregation of holes is the depletion region 5
Promote heat and / or light generation of electron hole pairs within 8. This agglomeration also causes punch-through of the p + / p junction 52, p
It may also be caused by the avalanche of the layer and / or the initial electron tunneling current from the n + / i junction 56. Hole agglomeration and increased hole current result in increased electron current through the n-type GaAlAs / undoped GaAlAs (n + / i) junction 56. This increased electron current is p + / p -
Field back to the junction 52, increasing the electron and hole currents that flow through the p + / p junction 52. p + / p
- hole current flowing through the junction 52, the depletion region 58
The internal current loop gain is
Exceeds 1. The feedback of the current loop will therefore be positive, increasing regenerative switching. As a result of this regeneration process, the device displays an s-type negative differential resistance (NDR) such that the voltage decreases and the current increases. In this state, the p + / p - junction 52 and the n + / i junction 56 are formed as shown in FIG.
It is strongly forward biased as shown in C.

【0018】電圧が低下した直後、急速に増大された電
子及びホール電流が、i領域の量子井戸50に注入さ
れ、ここで、再結合し、瞬時及び/又は励起放出を与え
る。この再結合は内部電流利得を1以下に減少し、素子
は安定状態に到達する。104 V/mよりも大きい電場
に対して、ホールガスが加熱され、バリアーに渡って熱
電子的安定放出が発生される。しかしながら、量子井戸
はi領域に最小電位を有しているので、熱ホールは、高
電場領域から掃き出される替わりに量子井戸に注入さ
れ、更にn型GaAlAsクラッド層内で再結合され
る。この注入機構は、高電場による衝撃イオン化を防止
する。更に、量子井戸内の電子及びホールの再結合は、
クラッド層によって与えられる固有の波ガイドによっ
て、励起放出を発生する。
Immediately after the voltage drops, rapidly increased electron and hole currents are injected into the quantum well 50 in the i-region, where they recombine and provide instantaneous and / or stimulated emission. This recombination reduces the internal current gain below 1 and the device reaches a stable state. For an electric field greater than 10 4 V / m, the hole gas is heated and a thermoelectron stable emission is generated across the barrier. However, since the quantum well has a minimum potential in the i region, hot holes are injected into the quantum well instead of being swept from the high field region and then recombined in the n-type GaAlAs cladding layer. This injection mechanism prevents impact ionization due to high electric fields. Furthermore, the recombination of electrons and holes in the quantum well is
Excited emission is generated by the inherent wave guide provided by the cladding layer.

【0019】図5は室温での素子の電流対電圧(I−
V)特性を示している。QWがi領域に最小電位を有し
ているので、熱ホールは、高電場領域から掃き出されな
いでQW内に注入され、n−GaAlAs内で再結合す
る。電子及びホールはQW内で再結合するので、クラッ
ド素子によって与えられる固有の波ガイドで、励起放出
が発生する。
FIG. 5 shows the current vs. voltage (I-
V) shows the characteristics. Since QW has the lowest potential in the i region, hot holes are injected into the QW without being swept from the high field region and recombine in n-GaAlAs. Since the electrons and holes recombine in the QW, the stimulated emission occurs with the inherent wave guide provided by the cladding element.

【0020】図6は素子の出力パワー対電流を図示して
いる。600ミリアンペアの閾値、67パーセントの差
動量子効率及びファセット当たり50ミリワットを越え
るパワーが、疑似連続波状態下で得ることができる。こ
れは、励起放出を呈するオプトエレクトロスイッチング
素子に対して電力、差動量子効率及び閾値に関して、最
高の性能を与える。図3に対して測定された素子の電力
は、ファセット当たり50ミリワットよりも低かった。
しかしながら、素子が完全に最適化される時、素子は、
より改良された閾値電流密度、差動量子効率及び出力電
力を与えることができる。
FIG. 6 illustrates the device output power versus current. A threshold of 600 milliamps, a differential quantum efficiency of 67 percent and a power in excess of 50 milliwatts per facet can be obtained under quasi continuous wave conditions. This gives opto-electro switching devices exhibiting stimulated emission the best performance in terms of power, differential quantum efficiency and threshold. The device power measured against Figure 3 was less than 50 milliwatts per facet.
However, when the device is fully optimized, the device
More improved threshold current density, differential quantum efficiency and output power can be provided.

【0021】ここで記述されたスイッチング素子は2又
は3端子素子を結果する。素子は、高速オプトエレクト
ロスイッチングを与え、励起放出を生じる。以上から、
本発明は、使用者が励起放出を有するダイオード構造を
有するオフトエレクトロスイッチ素子を得ることを可能
とする。従って、本発明は、特定の実施例と関連して記
述されたが、特許請求の範囲によって定義されたこと以
外は制限は意図されていない。当業者は、明細書及び図
面を研究することにより本発明の精神から離れること無
しに他の改良を行うことができることが理解されるため
である。
The switching elements described herein result in two or three terminal elements. The device provides fast opto-electro switching and produces stimulated emission. From the above,
The present invention allows a user to obtain an off-electroswitch element having a diode structure with stimulated emission. Accordingly, the present invention has been described in connection with specific embodiments, but is not intended to be limited except as defined by the claims. Those skilled in the art will understand that other improvements can be made by studying the specification and drawings without departing from the spirit of the invention.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に従うGaAs/GaAlAs SIS
構造ダイオードの概略断面図、
FIG. 1 GaAs / GaAlAs SIS according to the present invention.
Schematic cross section of a structural diode,

【図2】本発明の別の実施例に従うGaAs/GaAl
As SIS構造ダイオードの概略断面図、
FIG. 2 is GaAs / GaAl according to another embodiment of the present invention.
Schematic sectional view of an As SIS structure diode,

【図3】本発明の別の実施例に従う3端子GaAs/G
aAlAs SIS構造素子の概略断面図、
FIG. 3 is a three-terminal GaAs / G according to another embodiment of the present invention.
a sectional view of an aAlAs SIS structural element,

【図4】本発明に従うGaAs/GaAlAs SIS
構造素子のエネルギー変化を図示するエネルギーバンド
図、
FIG. 4 GaAs / GaAlAs SIS according to the invention.
An energy band diagram illustrating the energy change of the structural element,

【図5】本発明は従うGaAs/GaAlAs SIS
構造素子の電流対電圧特性を示す図、
FIG. 5: GaAs / GaAlAs SIS according to the invention.
Diagram showing the current-voltage characteristics of the structural element,

【図6】本発明に従うGaAs/GaAlAs SIS
構造素子の出力パワー対電流を示すグラフ。
FIG. 6 GaAs / GaAlAs SIS according to the present invention.
5 is a graph showing output power vs. current of a structural element.

【符号の説明】[Explanation of symbols]

10 GaAs/GaAlAs SIS構造ダイオード 12 基板 14 バッファー層 16 クラッド層 18 第1の導波層 20 第1の量子井戸 22 量子井戸バリヤー層 24 第2の量子井戸 26 第2の導波層 28 クラッド層 30 接触層 32,34 オーミック接触層 36 接続端子 10 GaAs / GaAlAs SIS structure diode 12 substrate 14 buffer layer 16 cladding layer 18 first waveguide layer 20 first quantum well 22 quantum well barrier layer 24 second quantum well 26 second waveguide layer 28 cladding layer 30 Contact layer 32,34 Ohmic contact layer 36 Connection terminal

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】オプトエレクトロスイッチングを提供する
ための構造ダイオード素子であり、この素子が、 基板、 前記基板の上に設置されたバッファー層、 前記バッファー層の頂部に設置されたn型クラッド層、 から成り、更に、 前記n型クラッド層の頂部に設置された少なくとも一つ
の量子井戸を有するドープされていないi型領域を有
し、このi型領域が、更に前記量子井戸の下に位置する
第1の導波層及び前記量子井戸の頂部に設置された第2
の導波路を含む、前記i型領域、 前記i型領域の頂部に設置されたp型クラッド層であ
り、このp型クラッド層は軽くドープされて、ホールに
対するバリアーを形成しているp型クラッド層、及び前
記p型クラッド層の頂部に設置された接続層を有するこ
とを特徴とする構造ダイオード素子。
1. A structural diode device for providing optoelectroswitching, the device comprising: a substrate, a buffer layer disposed on the substrate, an n-type cladding layer disposed on top of the buffer layer, Further comprising an undoped i-type region having at least one quantum well located on top of the n-type cladding layer, the i-type region further being located below the quantum well. A second waveguiding layer and a second layer on top of the quantum well
A p-type clad layer disposed on top of the i-type region and the i-type region, the p-type clad layer being lightly doped to form a barrier to holes. A structural diode device having a layer and a connection layer provided on top of the p-type cladding layer.
【請求項2】前記i領域が、更に前記量子井戸の下に位
置する第1の導波層、及び前記量子井戸の頂部に設置さ
れた第2の導波層を更に含む請求項1記載の素子。
2. The i-region further comprises a first waveguiding layer located below the quantum well, and a second waveguiding layer located on top of the quantum well. element.
【請求項3】前記GaAs接続層の頂部に設置される第
1のオーミック接続層を更に含む請求項2記載の素子。
3. The device according to claim 2, further comprising a first ohmic connection layer disposed on top of the GaAs connection layer.
【請求項4】前記1のオーミック接続層に接続する第1
の接続端子、及び前記第2のオーミック接続層に接続す
る第2の接続端子を更に含む請求項3記載の素子。
4. A first connecting to the one ohmic connection layer
4. The device according to claim 3, further comprising: a connection terminal of 1), and a second connection terminal connected to the second ohmic connection layer.
【請求項5】前記i領域が、複数の量子井戸とこの間に
位置するバリアー層を含む請求項2記載の素子。
5. The device according to claim 2, wherein the i region includes a plurality of quantum wells and a barrier layer located between the quantum wells.
【請求項6】前記接続層がp+ 型GaAsを含む請求項
4記載の素子。
6. The device according to claim 4, wherein the connection layer contains p + -type GaAs.
【請求項7】前記接続層がn+ 型GaAsを含む請求項
4記載の素子。
7. The device according to claim 4, wherein the connection layer includes n + -type GaAs.
【請求項8】光学的又は電気的バイアス信号を受信する
ための入力手段を有するオプトエレクトロスイッチング
素子であり、この素子が、 バイアス入力信号が所定の電圧以下の時にバリアーを形
成し、バイアス信号が所定の電圧以上の場合に励起放出
を与える空乏層を与える手段を含むオプトエレクトロス
イッチング素子。
8. An optoelectronic switching device having an input means for receiving an optical or electrical bias signal, the device forming a barrier when the bias input signal is below a predetermined voltage, and the bias signal is An optoelectroswitching device comprising means for providing a depletion layer that provides stimulated emission above a predetermined voltage.
JP4064663A 1991-09-06 1992-03-23 Semiconductor diode device with optoelectronic switching capability Expired - Lifetime JPH07118566B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US75588691A 1991-09-06 1991-09-06
US07/755886 1991-09-06

Publications (2)

Publication Number Publication Date
JPH05167066A true JPH05167066A (en) 1993-07-02
JPH07118566B2 JPH07118566B2 (en) 1995-12-18

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EP (1) EP0530942B1 (en)
JP (1) JPH07118566B2 (en)
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EP0530942B1 (en) 1997-10-22
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DE69222822T2 (en) 1998-03-05
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US5298762A (en) 1994-03-29
DE69222822D1 (en) 1997-11-27

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