JPH05166806A - Resist pattern formation method - Google Patents

Abstract

PURPOSE:To protect a resist pattern in an oblique direction with an offset level of a substrate from being reduced in size or defective at the offset level induced by the reflection of exposure light. CONSTITUTION:A resist pattern 2 in an oblique direction with an offset level 1 of a substrate is formed near the position where it is intersected with the offset level 1 in such a fashion that it may cross the offset level substantially at a right angle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a resist pattern for etching a base by exposing a photoresist applied to a base having a step in a photolithography process for manufacturing a semiconductor integrated circuit or the like.

[0002]

2. Description of the Related Art FIG. 1 is a plan view of a semiconductor integrated circuit having a resist pattern formed by a conventional resist pattern forming method and a sectional view taken along the line AA '. In the figure, the wiring 4 of the first layer is formed on the semiconductor substrate 3, and the insulating layer 5 is formed thereon.
An aluminum (Al) film 6 is deposited on the Al film 6, and a positive resist film 7 is applied to the Al film 6. By exposing the resist film 7 thus coated with a photomask 8 for shielding the second layer wiring pattern as shown in FIG. 1B, the Al film 6 is etched to form the second layer of the second layer. A resist pattern 2 is formed as a mask for patterning the wiring pattern.

[0003]

However, since the step portion 1 is formed in the Al film 6 at the corresponding portion of the wiring 4 of the first layer, the resist pattern 2 oblique to the step portion 1 is formed. When forming, when the resist pattern 2 intersects the upper surface of the step portion 1 at an angle, the resist pattern 2 near the intersecting position is exposed to the exposure light r diffusely reflected on the side surface of the step portion 1 as shown in FIG. 1 (b). The normal pattern is exposed by the halation effect, the resist line width in the vicinity of the step portion 1 becomes thin as shown in FIG. 1 (a), and the pattern is lost depending on the degree of exposure.

When the Al film 6 is dry-etched to form an Al wiring by using the resist pattern having the thinned line width as a mask, the line width of the Al wiring is thinned, so that the Al wiring is easily broken due to electromigration or stress migration. Become. Further, when the pattern is lost, dry etching results in formation of broken Al wiring, which causes malfunction of the semiconductor integrated circuit.

Further, as the degree of integration and density of semiconductor integrated circuits have increased, submicron level resist pattern forming technology in photolithography process has been required. To meet this requirement, shortening the wavelength of the exposure light is most effective, and the exposure light is changed from the g-line (436 nm) of the mercury lamp to the i-line.
(365 nm) or KrF excimer laser light (248 nm). Further, in order to secure sufficient resolution at the submicron level, it is necessary to increase the optical transparency of the resist material with respect to exposure light.

As the transparency of the resist material is increased due to the shortening of the wavelength of the exposure light as described above, the absorption of light by the resist material is almost eliminated, so Al, tungsten silicide (WSi ₂ ), polysilicon (poly-Si), etc. The halation effect due to the step difference in the ground is further promoted.

To reduce the halation effect, it is known that a method of depositing an antireflection film such as TiN or TiW having a low reflectance on the surface of an Al underlayer and applying a resist material thereto (“Ultra Clean Resist Processing ":
p.7, Seminar on Semiconductor Technology, 1990). However, in dry etching, the antireflection film such as TiN and TiW is etched together with the Al underlayer, but the etching shape remains a problem.

The present invention has been made in order to solve such a problem, and a resist pattern in the vicinity of a portion of a base which intersects a step is formed into a pattern in which an intersection angle with the step is substantially a right angle. An object of the present invention is to provide a resist pattern forming method for forming a resist pattern with high accuracy in a stable manner by preventing the halation effect of exposure light on a step as much as possible.

[0009]

A method for forming a resist pattern according to the present invention is a method of forming a resist pattern by exposing a resist applied to a base having a step, and forming a resist pattern in an oblique direction with respect to the step pattern of the base. It is characterized in that the resist pattern is formed in a resist pattern which is substantially orthogonal to the step pattern in the vicinity of the intersecting position with the step pattern of the base.

[0010]

According to the method of forming a resist pattern according to the present invention, when the resist pattern is formed in an oblique direction with respect to the underlying step pattern, the resist pattern in the vicinity of the intersection with the step pattern is formed in a resist substantially orthogonal to the step pattern. Form in a pattern. Therefore, the exposure light is diffusely reflected on the side surface in the height direction of the step pattern in a direction substantially orthogonal to the side surface. However, since the resist pattern near the intersecting position is formed substantially orthogonal to the step pattern, the exposure light The halation effect due to diffuse reflection is avoided as much as possible.

[0011]

The present invention will be described below with reference to the drawings showing the embodiments thereof. FIG. 2 is a plan view of a semiconductor integrated circuit in which a resist pattern is formed by the resist pattern forming method according to the present invention (hereinafter referred to as the present invention method). A resist film is applied to an aluminum film laminated on the first layer wiring via an insulating film to form a patterning mask for etching the second layer wiring pattern, and the second wiring layer is formed on the resist film. The pattern photomasks are superimposed and irradiated with exposure light such as ultraviolet rays, and the wiring pattern is transferred onto the resist to form a resist pattern as a patterning mask for the second layer wiring.

At this time, the first layer is applied to the base coated with the resist.
Since the step portion 1 is formed in the portion corresponding to the wiring of the layer, when forming the resist pattern 2 in the oblique direction with respect to the step portion 1 as shown in FIG. A resist pattern that intersects the step portion 1 at a substantially right angle is formed, and a resist pattern 9 in an oblique direction is formed until the vicinity of the next intersection position with the step portion 1.

FIG. 3 is a plan view of a semiconductor integrated circuit showing another embodiment of the resist pattern formed by the method of the present invention. As in this embodiment, when the step portions 1 are dense and the distance to the next adjacent step portion 1 is short and there is not enough margin to form the resist pattern in the diagonal direction, Without forming a diagonal resist pattern between
A pattern orthogonal to each step 1 is continuously formed.

FIG. 4 is a plan view of a semiconductor integrated circuit showing still another embodiment of the resist pattern formed by the method of the present invention. This embodiment is a resist pattern in the case where there is a narrow gap between the adjacent step portions 1 similarly to the above-mentioned embodiment, and between the entrance side and the exit side of the resist pattern that intersects the step portion 1 at a substantially right angle. By arranging the pattern (1) on the upper surface of the stepped portion 1 for a predetermined length and shifting the positions of the inlet side and the outlet side, and repeating this, even though no diagonal resist pattern is formed between the stepped portions 1. , Consequently step 1
The pattern on the input side and the pattern on the output side of the dense area are formed as a distant pattern which is continuous in the diagonal direction as in the case of intersecting the step portion 1 in the diagonal direction.

Since the resist pattern formed as described above intersects the step portion 1 at a substantially right angle in the vicinity of the intersection with the step portion 1, the reflected light of the exposure light on the side surface of the step portion 1 becomes a regular resist pattern. Has almost no effect.

The resist pattern formed by the method of the present invention is not limited to this embodiment, and any pattern may be used as long as the resist pattern in the vicinity of the intersection with the step portion intersects the step portion at a substantially right angle. The same effect as the example is obtained.

[0017]

As described above, according to the method of the present invention, the vicinity of the position where the resist pattern in the oblique direction with respect to the step portion intersects the step of the underlying layer is formed into the resist pattern which intersects the step almost at right angles. Since the influence of the halation effect on the regular resist pattern due to the irregular reflection of the exposure light at the step portion can be avoided and the regular resist pattern can be prevented from being thinned or damaged, it is possible to stably form a highly accurate resist pattern. Produce an effect.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit in which a resist pattern is formed by a conventional resist pattern forming method and a sectional view taken along the line AA ′.

FIG. 2 is a plan view of a semiconductor integrated circuit showing an example of a resist pattern formed by the method of the present invention.

FIG. 3 is a plan view of a semiconductor integrated circuit showing another embodiment of a resist pattern formed by the method of the present invention.

FIG. 4 is a plan view of a semiconductor integrated circuit showing still another embodiment of a resist pattern formed by the method of the present invention.

[Explanation of symbols]

 1 step portion 2, 9 resist pattern

Claims (1)

[Claims] 1. A method of forming a resist pattern by exposing a resist applied to a base having steps to form a resist pattern.
A method for forming a resist pattern, comprising forming a resist pattern in an oblique direction with respect to the underlying step pattern in a resist pattern which is substantially orthogonal to the step pattern in the vicinity of an intersection with the underlying step pattern.