JPH0516623B2 - - Google Patents

Description

Detailed Description of the Invention [Industrial Application Field] The present invention utilizes the inherent characteristics of color images in order to realize highly efficient transfer of color image data stored on a one-dimensional memory in a computer system. 3
This invention relates to an address generation circuit that performs memory access taking dimensional structure into consideration.

[Summary of the Disclosure] The present invention cuts out a partial region of an image from a memory having a dimensional structure that stores a color image,
When transferring and storing only the image data in that area as a continuous data string to another memory, or when writing data transferred as a continuous data string from another memory to a 3D structure memory, the 3D structure Achieves high-speed transfer operation by sequentially generating data addresses that are discontinuous as one-dimensional addresses in accordance with control parameters indicating the size and position of a predetermined cutout area in a memory with A three-dimensional address generation circuit is disclosed.

[Prior Art] and [Problems to be Solved by the Invention] Generally, a computer system equipped with an image processing function has a configuration as shown in Fig. 6, and has three common buses (address bus, data bus). bus, control bus) and CPU (Central Processing bus).
Unit) 62, RAM (Random Access Memory)
63, a disk (magnetic storage device) 66, etc. are connected.

In addition, the image memory is VRAM (Video RAM) 6
1, and data processing by the CPU 62, data transfer from the disk, etc. are performed through a common bus. At the same time, the contents of this memory VRAM 61 are always read out through a display-only bus for display purposes.

Furthermore, the DMA (Direct Memory
The access controller 64 uses dedicated hardware to control the bus without using the CPU 62 to perform high-speed data transfer.

In the above configuration, all the memories connected to the common bus have a one-dimensional address arrangement on the common address bus.

On the other hand, images inherently have a two-dimensional extent, and in color images, 1
Three elements of color for one pixel, e.g. Red(R)
Contains Green (G) and Blue (B) components. This color component is also 1
When considered as two axes (dimensions), it includes a three-dimensional structure, and when processing a color image, it must be treated as a three-dimensional array.

In the image memory VRAM 61 in the computer system, a three-dimensional array is scanned in an appropriate direction, converted into one-dimensional data, and transferred and stored.

Normally, as shown in Fig. 7, a color image is divided into R, G, and B screens, and then each screen is converted into one-dimensional data by performing raster scanning, which repeats scanning in the column direction. It is memorized as shown below. FIG. 8 shows that data is arranged one-dimensionally in the vertical direction, and the width in the horizontal direction has no meaning. the result,
The entire image exists collectively on a one-dimensional memory, but when viewed pixel by pixel, the R, G, and B component data are not collected together but exist in separate locations.

Moreover, in the case of pixels that are vertically adjacent to each other in a direction different from the scan direction, the data positions on the memory are separated by one row. In particular, when considering a partial area (partial image) of a color image, as shown in Fig. 7, one of the color components in one row is continuous, but it is continuous in one color component in another row and other color components. continuity is not maintained.

As a result, data is scattered at discontinuous addresses in the partial image.

In addition, when transferring image data, for example when displaying small images side by side, there is a request to transfer the data in small image units and write it sequentially to partial areas of the image memory, but in this case, the above-mentioned It is necessary to perform memory access taking into consideration the special data structure of image memory.

When transferring large amounts of data such as image data, it takes time to use software methods, so the DMA method, which can achieve high-speed transfer, is often used. It is used to read and write to areas with addresses. Therefore, when transferring all data of a color image to a large memory area, it is sufficient to execute DMA transfer only once.
As mentioned above, in the case of a partial image whose addresses are distributed over discontinuous areas, DMA transfer must be repeated line by line.

Furthermore, even if all color image data is stored in the image memory, it is usually stored according to the one-dimensional conversion procedure shown in Figure 7, and the one-dimensional data that is transferred is processed according to this procedure. Even if the order of the data is different, that is, if the order of the data is different, multiple DMA transfers are required. For example, when transferring data to the color image memory that is being displayed, color information (R component,
G component, B component) must be sent, and the order of the transferred data is as shown in FIG. 9A or B. However, this data array follows the normal one-dimensional transformation procedure (i.e., the scan order shown in Figure 7).
It is different from In particular, when transmitting color information in pixel units (see Figure 9A), in a normal memory configuration, addresses are discontinuous for each piece of data, and when attempting to perform DMA transfer in this case, the DMA transfer is performed a number of times equal to the number of data. The transfer will have to be repeated.

If such DMA transfer is performed multiple times, it takes time to set the transfer start address and the number of data to be transferred.
This reduces the original efficiency of DMA transfer, resulting in a reduction in transfer speed. In particular, when the transfer source is a magnetic disk device, data is read out as the disk rotates, so it is necessary to wait until the reading head comes to the desired data position. Therefore, as the number of DMA transfers increases, the total waiting time increases, resulting in a sharp drop in transfer efficiency.

[Objective] The object of the present invention is to extract a part of a color image from an image memory storing the color image and transfer it to another memory (for example, an external storage device) with high efficiency as a continuous data string (or vice versa). An object of the present invention is to provide a three-dimensional address generation circuit for (transfer).

In other words, the present invention provides three-dimensional addresses of data within a desired section including color information in a color image memory (i.e., addresses that are discontinuous in a one-dimensionally allocated memory). ) by continuously generating them according to various scan orders using control parameters.
The purpose is to perform highly efficient transfer to color image memory without sacrificing the high speed of DMA transfer.

[Means for Solving the Problems] The three-dimensional address generation circuit according to the present invention includes an initial parameter latch circuit that introduces initial parameter information, and a mode latch circuit that introduces a mode signal that instructs the arrangement of addresses to be generated. Then, the outputs from the initial parameter latch circuit and the mode latch circuit are introduced, and a counter circuit that sequentially generates the addresses specified by the initial parameter information and the mode signal in synchronization with the timing signal is installed for each predetermined color screen. Provided with 1 piece,
A switching parameter latch circuit that introduces a switching parameter signal that specifies switching the color screen every predetermined number of pixels, and switching the sending of a timing signal to the counter circuit in response to the switching parameter signal from the switching parameter latch circuit. , comprising a timing control circuit that outputs a gate control signal, and a gate circuit that introduces the gate control signal from the timing control circuit and sends out only the output of the counter circuit into which the timing signal is introduced. It is.

[Embodiment] An embodiment in which a DMA controller is used to transfer data between an external storage device and a color image memory will be described below. For convenience of explanation, a case will be described in which data is transferred from an external storage device and written into the image memory, but the same applies to the case where data is transferred and stored from the image memory to the storage device.

FIG. 1 is a block diagram showing an entire embodiment of the present invention. In this figure, data is stored one-dimensionally in the external storage device 10, and the data is sequentially read out at a certain timing. The three-dimensional address generation circuit 13 outputs an address signal in synchronization with a timing signal according to appropriate parameters input in advance. This output address signal and the data signal passed through the DMA controller 11 are input to the color image memory 14, and data is written into the color image memory 14 using a write signal, which is one of the control signals.

Next, the process of generating a three-dimensional address will be explained with reference to the detailed block diagram shown in FIG.

In FIG. 2, 20 is a timing control circuit, 21 is a column start address latch circuit, 22 is a column end address latch circuit, and 23 is a column start address latch circuit.
24 is a row start address latch circuit, 24 is a row end address latch circuit, 25 is a mode latch circuit, 26 is a first counter circuit, 27 is a second counter circuit, 28 is a third counter circuit, 29 is a gate circuit, and 30 is a This is a switching parameter latch circuit.

As an example, from the external storage device 10 (see FIG. 1), as shown in FIG.
Transfer the R, G, and B data two pixels at a time for the partial image data indicated by ~ “200” and the row direction “21” to “140”, and after sending one row of data, send the next row of data. shall be taken as a thing. That is, the data from the external storage device 10 are R ₁₀₁₂₁ , R ₁₀₂₂₁ ,
G ₁₀₁₂₁ , G ₁₀₂₂₁ , B ₁₀₁₂₁ , B _{10221 .} . . are transferred in this order, and this circuit sequentially generates the transfer destination address.
Here, the capital letters represent each color screen, and the subscript represents the two-dimensional position of the pixel. In other words, R _101,21 is the R screen
Represents the data in the 21st row and 101st column.

“101” shown in Figure 3 is set as a parameter in advance.
“200”, “21”, and “140” are column start address latch circuit 21, column end address latch circuit 22, and row start address latch circuit 2, respectively.
3. Input to row end address latch circuit 24, switching parameter latch circuit 30,
A numerical value "2" is input that instructs to switch between R, G, and B screens every two pixels.

The mode latch circuit 25 receives an input mode signal instructing that data in the column direction be transferred before data in the row direction. At this time, the first, second,
The third counter circuits 26-28 are preset with memory start addresses calculated from the column start address and row start address. And each counter circuit 26 to 28
Then, a color address signal indicating R, G, and B color information is added and output to the gate circuit 29 side. The operations of these counter circuits 26 to 28 will be described in detail later.

First of all, the input timing signal is introduced only to the first counter circuit 26 via the timing control circuit 20, and the gate control signal (sent out from the timing control circuit 20)
Accordingly, the output of the first counter circuit 26 is sent out from the gate circuit 29. At this time, the outputs of the second and third counter circuits 27 and 28 are cut off by the gate circuit 29.

In this state, the timing control circuit 20 counts two input timing signals. At that time, switching parameter latch circuit 3
Detects a match with the output from 0 (that is, the pre-latched switching parameter "2"),
The input timing signal is connected only to the second counter circuit 27 by switching the connection of the input timing signal. Further, the gate circuit 29 receives the gate control signal and allows only the output of the second counter circuit 27 to pass through.

Similarly, the connection of the input timing signal and the output of the gate circuit are switched every time two input timing signals are counted. By this, 2
For each pixel, the color screen specified by the output address signal changes.

Next, the operation of the counter circuit will be explained using FIG. 4. Here, 40 is a column address counter, 41 is a row address counter, 42 is a column comparator, 43 is a counter control circuit, 44 is a row comparator,
45 is a color address information generation circuit.

In the counter circuit, first, the column start address and the row start address are input to the counters 40 and 4.
1, and a color address signal indicating the distinction between R, G, and B is added and output. Further, in response to a mode signal indicating that priority is given to data in the row direction, the counter control circuit 43 instructs counting permission using a column counter control signal.

When the timing signal is input, the column address counter 40 counts up accordingly.
When the column address output matches the column ED address, the column comparator 42 outputs a column match signal, and the counter control circuit 43 enables counting by the row counter control signal and loads data by the column counter control signal. instruct. As a result, the row address counter 41 counts up in synchronization with the next input timing signal, and at the same time, the column address counter 40 reloads the column start address.

The same operation is repeated below.

In this way, the column address output repeatedly counts up from the column start address to the column end address. Also, the row address output counts up from the row start address, and
When both columns match the end address, the transfer ends.

As described above, three-dimensional addresses corresponding to one-dimensional conversion such as sending color information in units of two pixels are sequentially generated.

In the above embodiment, the row start, row end,
Since desired values can be selected for each of the row start and row end addresses, the sections on the color image memory can be set to any position and any size.

Further, various scan orders can be supported by switching parameters and mode signals. In other words, if the value of the switching parameter is set to "1", the data order is such that color information is sent pixel by pixel, if the number of data for one line is set, color information is sent by line, and if the number of data for one screen is set, color information is sent by screen. can be accommodated.

Furthermore, by switching the mode signal,
It can also handle one-dimensional data obtained by scanning in the row direction first.

In the embodiments described with reference to FIGS. 1 to 4, it was assumed that only data within a partition was stored in the external storage device, but if data for the entire screen was stored, As in the embodiment shown in FIG. 5, by newly providing an additional circuit and controlling the operation, it is possible to cut out any section from the entire screen.

As the additional circuits, an operation control circuit 51 and a read/write signal gate circuit 53 are provided.

The operation of this embodiment is as follows.

Using the timing signal from the DMA controller 50, the R/W signal in the controller signal is cut until the first data of the desired section arrives. In addition, the three-dimensional address generation circuit 52
stop working.

After the first data arrives, an address is generated using the process described above. Then, write the data to memory.

When the data has been written to memory up to the end of the column,
The operation control circuit 51 waits until it detects that data of the column start address of the next row has arrived.

When the data at the end of the row has been transferred, the transfer ends.

Furthermore, if the address generation operation and data writing are performed intermittently, the image can be reduced and written.

Furthermore, in the above example, it is used to generate an address for either the transfer source or the transfer destination, but by using it for both, it can also be used for transfer between RAMs.

[Effects of the Invention] By carrying out the present invention, the three-dimensional addresses of specific sections in the color image memory are sequentially generated, so image data distributed in discontinuous address areas can be read and written continuously. High-speed data transfer can be achieved.

Furthermore, by changing the control parameters, it is possible to cope with cases where the order of transferred data is different from the scan order in a normal image memory. Therefore, since color information can be sent pixel by pixel or line by line to the color image memory being displayed, unnatural colors are not visible on the display screen even during color image transfer.

On the other hand, a major feature of the present invention is that a three-dimensional address generation circuit can be realized simply by adding it to a DMA controller, so there is no need to change the computer system, and it can be implemented easily and at low cost. Although various scan orders can be supported, depending on the embodiment, the scan order can be fixed to simplify the circuit.

In each of the embodiments described above, the color elements are R,
We have explained it as G and B, but in addition, brightness,
Images may be expressed using hue and saturation.

The present invention can also be used for data transfer for multi-channel images such as satellite images.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an entire embodiment of the present invention, Fig. 2 is a detailed circuit diagram of the three-dimensional address generation circuit shown in Fig. 1, and Fig. 3 is a diagram showing the transfer of partial image data from an external storage device. 4 is a detailed configuration diagram of the counter circuit shown in FIG. 2. FIG. 5 is a block diagram showing another embodiment of the present invention in which the screen is cut out. 6
The figure is a schematic configuration diagram of a conventionally known image processing system, Figure 7 is a diagram showing the process of converting three-dimensional array data into one-dimensional array data and transferring and storing it, and Figure 8 is a diagram of a color image memory. A diagram for explaining address allocation; FIG. 9A is a diagram for explaining the data arrangement order when transmitting color image information for each pixel;
FIG. 9B is a diagram illustrating the data arrangement order when color image information is sent line by line. 10... External storage device, 11... DMA controller, 12... Host computer, 13... Three-dimensional address generation circuit, 14... Color image memory,
20...timing control circuit, 21...
Column start address latch circuit, 22... Column end address latch circuit, 23... Row start address latch circuit, 24... Row end address latch circuit, 25... Mode latch circuit, 2
6...First counter circuit, 27...Second counter circuit, 28...Third counter circuit, 29...Gate circuit, 30...Switching parameter/latch circuit, 40...Column address counter, 41...Row Address counter, 42...Column comparator, 43...Counter control circuit, 44...Row comparator, 45...Color address information generation circuit, 50...DMA controller, 51...Operation control circuit, 52...3 Dimensional address generation circuit, 53...Gate circuit for read/write signals, 54...Color image memory, 60...
Monitor, 61...VRAM, 62...CPU, 6
3...RAM, 64...DMA controller, 6
5...Disk controller, 66...Disk.

Claims (1)

[Scope of Claims] 1. An initial parameter latch circuit that introduces initial parameter information, a mode latch circuit that introduces a mode signal that instructs the arrangement of addresses to be generated, and outputs from the initial parameter latch circuit and the mode latch circuit. one counter circuit is provided for each predetermined color screen, and one counter circuit is provided for each predetermined color screen to sequentially generate addresses specified by the initial parameter information and the mode signal in synchronization with a timing signal, and for each predetermined number of pixels. a switching parameter latch circuit that introduces a switching parameter signal instructing switching of the color screen; and a switching parameter latch circuit that switches transmission of the timing signal to the counter circuit in response to the switching parameter signal from the switching parameter latch circuit; a timing control circuit that outputs a control signal;
A three-dimensional address generation circuit characterized by comprising a gate circuit which introduces the gate control signal from the timing control circuit and sends out only the output of the counter circuit into which the timing signal is introduced. 2. The counter circuit presets a column start address signal, which is the initial parameter information, and a column address counter that sends out a column address signal in synchronization with the timing signal, and a row address signal, which is the initial parameter information. and a row address counter that sends out a row address signal in synchronization with the timing signal;
a column comparator that compares the column address signal and the column end address signal that is the initial parameter information and generates a match signal when the two match;
a row comparator that compares the row address signal and the row end address signal that is the initial parameter information and generates a match signal when the two match; an output signal from the column comparator or the row comparator; a counter control circuit that receives the mode signal and generates a control signal for instructing the column address counter and the row address counter to enable counting or to load data; Claim 3, characterized by comprising a color address information generation circuit that generates color address information for adding.
Dimensional address generation circuit.