JPH05165740A - Input/output controller - Google Patents

Abstract

PURPOSE:To prevent the extinction of important tracing data on an input/output controller. CONSTITUTION:The input/output controller provided with a tracing memory 13 storing tracing data showing a processing process which a processor 11 executes is provided with a first storage means 14 storing information for extracting required tracing data from tracing data which the tracing memory 13 stores, and a second storage means 15 storing tracing data which is extracted based on information which the first storage means 14 stores. The second storage means 15 stores tracing data which is extracted based on information which the first storage means 14 stores among tracing data stored in the tracing memory 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control device controlled by a processor, and more particularly, it is possible to prevent the disappearance of important trace data among the trace data indicating the processing process executed by the processor. I / O control device.

A disk device is used as an external storage device of a computer system. The disk device is controlled by a disk control device and transfers data to and from a channel.

When the data transfer between the disk device and the channel is stopped due to a failure or the like, the processing efficiency of the computer system is lowered, so that the disk control device has history information indicating the processing process executed by the processor, that is, , Equipped with a trace memory to store the trace data,
When a failure occurs, the cause of the failure is sought based on the trace data read from the trace memory, and the failure is promptly eliminated.

Therefore, it is necessary that the trace data at the time of failure occurrence be saved.

[0005]

2. Description of the Related Art FIG. 8 is a block diagram illustrating an example of a conventional technique. Channels 1 to 4 are connected to the interface circuit 8 of the disk control device 5, and disk devices 6 to 7 are connected to the interface circuit 10. Then, the processor 11 of the disk controller 5
When a program stored in the control memory 12 is read and operated, the interface device 8 is used to specify, for example, the disk device 6 from the channel 1 and data writing is instructed. Position the 6 head at the specified address.

When data can be written in the disk device 6, the channel 1 is passed through the interface circuit 8.
To send data to the disk device 6 by instructing the data transfer control circuit 9 to transfer the data sent by the channel 1 to the disk device 6 through the interface circuit 10.

Further, when the processor 11 is instructed to read the data from the channel 2 via the interface circuit 8 and the disk device 7, the processor 11 passes through the interface circuit 10 to the specified address of the head of the disk device 7. The data read by the disk device 7 is instructed to the data transfer control circuit 9 to be transferred to the channel 2 via the interface circuit 8.

The same applies to access from channel 3 or channel 4. In this way, the processor 11
Receives a command from the channel and executes the processing of the received command to return an end status to the channel. Then, during this command processing, a command is issued to the disk device and the completion status is received.

Further, for example, if the error detection circuit provided in the data transfer control circuit 9 has an error in the data being transferred,
When this error is detected and reported, error information is created and the abnormal termination of the command is notified to the corresponding channel.

Then, in response to the abnormal end notification, when a retry request is issued from the channel, the processor 11 executes a retry process. Then, the processor 11
The trace data created based on these operations is sent to and stored in the trace memory 13.

That is, the processor 11 receives the command from the channel, issues the command to the disk device, receives the end status from the disk device, as described above.
The issuance of the end status to the channel is stored as trace data, and during the retry process, each time the retry is repeated, the trace data indicating the history of the process is sequentially written in the trace memory 13.

[0012]

As described above, when the retry process is executed conventionally, the amount of trace data stored in the trace memory 13 increases, but the trace data is recorded up to the final address of the trace memory 13. Then, the next trace data is sequentially written again from the head address of the trace memory 13.

Therefore, the trace data already stored will be erased and lost in order from the start address. As a result, there is a problem that important trace data before and after an error may be lost depending on the frequency of access to the disk device and the frequency of retries.

In view of such a problem, the present invention has a register for storing the contents designating the trace data to be extracted from the trace data stored in the trace memory 13, and a storage means for storing the extracted trace data. Is provided so that only the necessary trace data can be left in the trace data stored in the trace memory 13.

[0015]

FIG. 1 is a block diagram for explaining the principle of the present invention. The input / output control device is shown in Fig. 1 (A).
As shown in FIG. 3, the trace memory 13 for storing trace data indicating the processing process executed by the processor 11 is provided.

Based on the information stored in the first storage means 14 for storing the information for extracting the necessary trace data from the trace data stored in the trace memory 13, and the information stored in the first storage means 14. A second storage unit 15 for storing the extracted trace data, and the trace extracted from the trace data stored in the trace memory 13 based on the information stored in the first storage unit 14. The data is stored in the second storage unit 15.

Further, the input / output control device, as shown in FIG. 1 (B), is provided with a trace memory 13 for storing trace data showing a processing process executed by the processor 11.
Then, from the trace data stored in the trace memory 13, the first storage means 14 for storing the information for extracting the necessary trace data and the information stored in the first storage means 14 are extracted. A pair of second storage means 15 for storing trace data, and a first storage means 16 for storing information for extracting necessary trace data from the trace data stored in the trace memory 13; This first storage means 1
The second storage means 17 for storing the trace data extracted on the basis of the information stored in 6 is paired, and further, from the trace data stored in the trace memory 13,
A pair of a first storage unit 18 for storing information for extracting necessary trace data and a second storage unit 19 for storing the trace data extracted based on the information stored in the first storage unit 18 As a plurality of pairs.

Then, the trace data extracted from the trace data stored in the trace memory 13 based on the information stored in the first storage means 14 is stored in the second storage means 15 forming a pair. The trace data extracted based on the information stored in the first storage unit 16 is paired with the trace data extracted based on the information stored in the first storage unit 18 in the second storage unit 17 forming a pair. The second storage means 19 is stored separately.

[0019]

With the above-described structure, important trace data can be extracted from the trace memory 13 and stored in the second storage means 15, 17, and 19.
It is not erased by writing the trace data to the trace memory 13.

Therefore, of the trace data stored in the trace memory 13, only the necessary trace data can be left.

[0021]

2 is a block diagram of a circuit showing an embodiment of the present invention, and FIGS. 3 to 5 are diagrams for explaining the operation of FIG.

In FIG. 2, the same reference numerals as those in FIG. 8 indicate the same functions. The processor 11 operates by reading the program stored in the control memory 21, and sequentially stores the trace data in the trace memory 13 as described with reference to FIG.

The trace data is composed of 4-byte data as shown in the trace memory 13 of FIG. 3, for example, and the hexadecimal number 100B0 in the start address area.
000 is the hexadecimal number 110A in the second address area
1011 is the hexadecimal number 120C0 at the third address
001 is the hexadecimal number 130A in the fourth address area
0100 is the hexadecimal number 140D1 at the fifth address
110 is written.

The addresses of channels 1 to 4 are stored in the second byte of this trace data. That is, the address of channel 1 is 0A in hexadecimal, the address of channel 2 is 0B in hexadecimal, the address of channel 3 is 0C in hexadecimal, and the address of channel 4 is 0D in hexadecimal.

When no error occurs, the register 22 and the extended trace memory 23 store the initial value hexadecimal FF in the initial state as shown in the register 22 and the extended trace memory 23 of FIG. Has been done.

The processor 11 reads the data in the register 22 each time the trace data is written in the trace memory 13, and if the register 22 remains in the initial state, the trace data is written in the extended trace memory 23. Absent.

Here, for example, if an error occurs while data is being transferred between the channel 1 and the disk device 6, the processor 11 notified from the data transfer control circuit 9 of the occurrence of the error Since an error occurs during access from the channel 1, the address 0A of the channel 1 is written in the register 22 as shown in the register 22 of FIG.

As described above, the processor 11 registers each time the trace data is written in the trace memory 13 with the register 22.
When the address 0A of the channel 1 is stored in the register 22 when the data of No. 2 is read out and the trace data of which the second byte address is 0A is extracted from the trace data stored in the trace memory 13, The extracted trace data is written in the extended trace memory 23.

That is, as shown in the extended trace memory 23 of FIG. 4, the trace data 110A1011 and 130A0100 stored in the second and fourth address areas of the trace memory 13 are written in the extended trace memory 23. To be crowded.

The processor 11 uses the extended trace memory 23.
When the writing of the trace data for the above is completed, an error is reported to the channel 1, and the initial value FF is stored in the register 22 as shown in the register 22 of FIG.

The channel 1 which has reported the error reports an error to the central processing unit, and when the central processing unit instructs the retry of the command, the channel 1 again sends the command to the processor 11 and requests the retry.

The processor 11 executes the requested retry and writes the trace data in the trace memory 13 each time as described with reference to FIG. Further, the processor 11 operates by accessing from the channel 2 or 3 or 4,
The trace data is sequentially written in the trace memory 13. Then, when the trace data is written up to the final address of the trace memory 13, the trace data is written from the start address.

Therefore, as shown in the trace memory 13 of FIG. 5, the head address area of the trace memory 13 is rewritten as 220B1001 and the second address area is rewritten as 230C1100. Therefore, the trace data of channel 1 when an error occurs, 110A10
11 disappears, but as shown in the extended trace memory 23 of FIG.
It is left in 3.

FIG. 6 is a flow chart for explaining the operation of FIG. The processor 11 creates trace data in step (1) and writes the trace data created in step (2) in the trace memory 13.

The processor 11 then proceeds to step (3).
It is checked whether an error has occurred, and if no error has occurred, the process proceeds to step (4) and the register 22 is checked for an initial value.

If the register 22 is the initial value, the step
Returning to the processing of (1), if the register 22 is not the initial value,
After the initial value is stored in the register 22 in step (5), the process returns to step (1).

If an error occurs in step (3), the processor 11 checks in step (6) whether the register 22 is an initial value, and if it is an initial value, registers 22 in step (7).
Write the address of the channel being accessed to
When the trace data corresponding to the channel designated by the address of the register 22 is extracted from the trace memory 13 and written in the extended trace memory 23 in (8), the process returns to step (1).

If the register 22 is not the initial value at the step (6), the processor 11 shifts to the processing at the step (9), and the trace data corresponding to the channel indicated by the address of the register 22 is stored in the extended trace memory 23. When is extracted from the trace memory 13 and written, the process returns to step (1).

FIG. 7 is a block diagram of a circuit showing another embodiment of the present invention. FIG. 7 shows a plurality of registers 22 and 24.
And a plurality of extended trace memories 23 and 25 are provided. For example, by storing the channel 1 address in the register 22 and the channel 3 address in the register 24, the extended trace memory 23 is The trace data related to channel 1 can be extracted and written, and the trace data related to channel 3 can be extracted and written to the extended trace memory 25.

By doing this, a plurality of types of important trace data can be stored in correspondence with the number of registers and extended trace memories that form a pair.

[0041]

As described above, according to the present invention, important trace data can be extracted from the trace memory and saved in the extended trace memory, so that the trace data is written beyond the capacity of the trace memory. It is not erased by being overwritten by.

Therefore, necessary trace data can be left in the trace data stored in the trace memory.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation of FIG. 2 (No. 1)

FIG. 4 is a diagram for explaining the operation of FIG. 2 (No. 2)

FIG. 5 is a diagram (part 3) explaining the operation of FIG. 2;

FIG. 6 is a flowchart illustrating the operation of FIG.

FIG. 7 is a block diagram of a circuit showing another embodiment of the present invention.

FIG. 8 is a block diagram illustrating an example of a conventional technique.

[Explanation of symbols]

 1 to 4 channels 5, 20 disk control device 6, 7 disk device 8, 10 interface circuit 9 data transfer control circuit 11 processor 12, 21 control storage 13 trace memory 14, 16, 18 first storage means 15, 17, 19 Second storage means 22, 24 Registers 23, 25 Extended trace memory

Claims (2)

[Claims] 1. An input / output control device comprising a trace memory (13) for storing trace data indicating a processing process executed by a processor (11), the trace data being stored in the trace memory (13). From the first storage means (14) for storing information for extracting the necessary trace data, and a second storage means for storing the trace data extracted based on the information stored in the first storage means (14). A storage means (15) is provided, and the trace data extracted from the trace data stored in the trace memory (13) based on the information stored in the first storage means (14) is An input / output control device characterized by storing in the second storage means (15). 2. An input / output control device comprising a trace memory (13) for storing trace data indicating a processing process executed by a processor (11), the trace data being stored in the trace memory (13). From the first storage means (14) (16) (18) for storing the information for extracting the necessary trace data, and the information stored in the first storage means (14) (16) (18). Second storage means for storing the trace data extracted based on
(15) (17) (19), and a plurality of pairs are provided as a pair, and the trace memory (13)
Trace data extracted based on different information stored in the first storage means (14) (16) (18) from the trace data stored in the second storage means forming a pair.
(15) An input / output control device characterized by being stored separately in (17) and (19).