JPH05161014A - Binarization circuit - Google Patents

Abstract

PURPOSE:To binarize an image signal with a very simple circuit configuration without needing shading correction and surface density correction. CONSTITUTION:An image sensor output is inputted to a differentiation circuit 2 via a buffer 1. The differentiation circuit 2 detects the switching point of a while picture element and a black picture element. A window comparator 3 detects respectively the rising pulse and the falling pulse of a differentiation output. A binarization pulse generating circuit 4 generates and outputs a binarized pulse having a pulse width from the falling pulse till the rising pulse. When a black picture element proceeds, a white/black level discrimination circuit 6 detects it to activate an inverting circuit 7, thereby inverting the binarization pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binarization method for binarizing an image signal obtained by an image input device such as an image scanner.
Regarding the digitization circuit.

[0002]

2. Description of the Related Art Conventionally, in the case of binarizing an image signal, for example, a peak value of a document level is resistance-divided to determine a threshold level, or a FET gain is controlled based on the peak value of the document level. The level of the image signal is adjusted to a predetermined threshold level. However, these methods cannot eliminate the influence of shading caused by variations in the image sensor sensitivity and the light source output.

On the other hand, it has been conventionally performed to correct the shading of the image signal based on the signal (shading waveform) obtained by reading the white reference plate.
In the case of binarization, it is difficult to determine the optimum threshold level because the density level of the white reference plate differs from the background density level of the actual document. Therefore, in order to perform favorable binarization, it is necessary to perform shading correction and background density correction on the image signal and then compare the corrected image signal with a predetermined threshold level.

[0004]

As described above, the conventional two
In the binarizing circuit, shading correction and background density correction must be performed on the image signal in order to adapt the image signal to a constant threshold level. Therefore, there is a problem that a shading document such as a white reference plate is required, and a prescan for shading correction and a prescan for background density correction are required, which complicates the circuit configuration and processing.

The present invention has been made in view of the above problems, and provides a binarization circuit capable of binarizing an image signal with an extremely simple circuit configuration without requiring shading correction and background density correction. The purpose is to do.

[0006]

A binarizing circuit according to the present invention includes a differentiating circuit for differentiating an image signal, a comparator for separately detecting a rising pulse and a falling pulse of the output of the differentiating circuit, and A binarized pulse generation circuit for generating a binarized pulse having a width ranging from at least one of the rising pulse and the falling pulse to the other is provided.

In addition to the above-mentioned structure, another binarizing circuit according to the present invention further comprises a delay circuit for delaying the binarizing pulse, and either the rising pulse or the falling pulse. A leading pulse determination circuit that determines whether or not
And an inverting circuit that inverts the output of the delay circuit based on the discrimination result of the preceding pulse discrimination circuit.

[0008]

According to the present invention, the image signal obtained by the scanner is first differentiated by the differentiating circuit. As a result, the influence of shading and background density level is eliminated, and only the black and white inversion part of the image signal is extracted in the form of the rising pulse or the falling pulse. The rising pulse and the falling pulse obtained by the differentiating circuit are separately detected by the comparator, and the binarizing pulse generating circuit generates a binarizing pulse having a width from at least one of the rising pulse and the falling pulse to the other. Since it is generated, this binarized pulse can be used as a binarized output.

Generally, an image signal is preceded by a white pixel, but it is conceivable that a black pixel is preceded. Therefore,
The binarized pulse is delayed by, for example, one line by a delay circuit, the leading pulse discriminating circuit discriminates which of the rising pulse and the falling pulse is leading, and the delay circuit is based on the discrimination result. By inverting the output of, even if the black pixel precedes, the correct 2
The digitized output can be obtained.

As described above, according to the present invention, an appropriate binary output can be obtained by eliminating the influence of shading and background density by a very simple method of differentiating an image signal.

[0011]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a second embodiment according to the present invention.
It is a circuit diagram which shows the structure of a digitization circuit. For example, A0-A4
An analog image signal supplied from a line image sensor (not shown) capable of reading a size document is stored in the buffer 1
Is input to the differentiating circuit 2 via. The differentiating circuit 2 is composed of a series circuit of a capacitor C and a resistor R and differentiates the analog image signal. The image signal differentiated by the differentiation circuit 2 is
It is input to the window comparator 3. The window comparator 3 includes two comparators 3 arranged in parallel.
1 and 32, and a reference voltage generation circuit configured by connecting resistors R1 to R4 in series for supplying threshold voltages VTH and VTL to the reference voltage terminals of these comparators 31 and 32, respectively. Comparator 3
1 detects the rising pulse of the output of the differentiating circuit 2, and the comparator 32 detects the falling pulse of the output of the differentiating circuit 2.

The output of the window comparator 3 is supplied to the binarized pulse generation circuit 4. The binarized pulse generation circuit 4 includes D-type flip-flops (hereinafter, referred to as D-FF) 41 and 42, an exclusive OR gate (hereinafter, referred to as EX-OR gate) 43 that gates the output thereof. It consists of The D-FF 41 has a comparator 31.
The output of is divided and the inverted output is output. D-FF42
Outputs the frequency-divided output of the comparator 32. EX
The OR gate 43 outputs a binarized pulse that becomes 0 level only during the period corresponding to the phase shift of these frequency-divided outputs. The binarized pulse is input to the shift register 5. The shift register 5 functions as a delay circuit that delays the binarized pulse by one line.

On the other hand, the outputs of the comparators 31 and 32 are
It is supplied to the preceding pulse discrimination circuit 6. The preceding pulse discrimination circuit 6 includes D-FFs 61 and 62 and these D-FFs.
An OR gate 63 for reset controlling 61, 62,
64 and a latch circuit 65 for timing synchronization for outputting the output of the D-FF 61 in the period of the next line. The preceding pulse discrimination circuit 6 changes the output of the D-FF 61 with the output c of the comparator 31
-Reset the FF62 and the comparator 3
The output of D-FF62 is changed by the output d of 2
The output 1 is reset, and the output rises only when the output c precedes the output d.

The output of the shift register 5 is supplied to the inverting circuit 7. The inverting circuit 7 includes AND gates 71 and 7
2 and the OR gate 73, the logical value of the output of the shift register 5 is inverted only when the output of the preceding pulse discrimination circuit 6 is active. Then, the inverting circuit 7 outputs a binarized output.

Next, the operation of the image input apparatus according to this embodiment having the above structure will be described. FIG. 2 is a waveform diagram of each part of the binarization circuit. FIG. 2A shows the case where the leading pixel is a white pixel, and FIG. 2B shows the case where the leading pixel is a black pixel.

(1) When the first pixel is a white pixel The sensor output a output from the image sensor and amplified by the buffer 1 has the highest level in the central portion due to the effect of shading, as shown in the figure. Moreover, the average level is also uncertain due to the influence of the background density. When the sensor output a is differentiated by the differentiating circuit 2, the differentiating circuit 2 sets the time constant to an appropriate value so that it does not follow a gradual change such as shading, and the white pixel and the black pixel are separated from each other. It is possible to obtain the differential output b that follows only the point at which changes. The differential output b becomes a signal that falls at the portion where the white pixel switches to the black pixel and rises at the portion where the black pixel switches to the white pixel.

When the differential output b is input to the window comparator 3, the comparator 31 turns on the threshold VT.
Detection signal c of pulse exceeding H, that is, rising pulse
Is output, and the comparator 32 outputs the threshold VTL.
The detection signal d of a pulse falling below, that is, a falling pulse is output. When these signals c and d are input to the binarized pulse generation circuit 4, these signals c and d are output to the D-FF 4
It is divided by 1,42. Since the D-FFs 41 and 42 take out mutually inverted outputs, the EX-OR gate 43 has a 0 level only during a period in which the levels of both outputs match, that is, a period corresponding to a phase shift of both outputs. The output e will be obtained. This output e becomes a binary output of the sensor output a. This binarized output is delayed by one line in the shift register 5 and output to the outside through the inversion circuit 7.

(2) When the start pixel is a black pixel By the way, as shown in the sensor output a of FIG. 2B, when the start pixel is a black pixel, a rising pulse is generated first, so that the comparators 31 and 32 are operated. The phase relationship between the outputs c and d is opposite to that in the case of FIG. 2A. In this case, 2
The output of the binarization pulse generation circuit 4 has an inverse relationship to the case of FIG. 2A, and a correct binarized output cannot be obtained.

Therefore, in this circuit, after the preceding pulse discriminating circuit 6 is reset by the line signal, the Q output of the D-FF 61 rises only when the first pulse is the output c. This Q output is latched in the latch circuit 65 by the next line signal. As a result, the AND gate 72 in the inverting circuit 7 becomes effective, the output of the shift register 5 is inverted, and a correct binary output is obtained.

As described above, according to the binarization circuit of the present embodiment, the sensor output a is differentiated and the pulse having the width from the falling edge to the rising edge is generated, so that the shading is performed with an extremely simple circuit configuration. It is possible to obtain a binary output that has been corrected and the background density of the original document has been corrected.

[0021]

As described above, according to the present invention, the effect of shading and background density can be eliminated by a very simple method of differentiating an image signal to obtain an appropriate binary output. Produce an effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a binarizing circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of each part of the same circuit.

[Explanation of Codes] 1 ... Buffer, 2 ... Differentiation circuit, 3 ... Window comparator, 4 ... Binary pulse generation circuit, 5 ... Shift register,
6 ... Leading pulse discrimination circuit, 7 ... Inversion circuit.

Claims (2)

[Claims] 1. A differentiating circuit for differentiating an image signal, a comparator for separately detecting a rising pulse and a falling pulse of the output of the differentiating circuit, and a width from at least one of the rising pulse and the falling pulse to the other. And a binarization pulse generation circuit for generating the binarization pulse of 1. 2. A delay circuit for delaying the binarized pulse, a leading pulse discriminating circuit for discriminating which of the rising pulse and the falling pulse precedes, and a discrimination result of the preceding pulse discriminating circuit. The binarization circuit according to claim 1, further comprising an inverting circuit that inverts the output of the delay circuit based on the above.