JPH05151314A - Method and system for constituting layout block - Google Patents

Abstract

PURPOSE:To easily obtain an optimal layout block by constituting one layout block, respectively by a logical hierarchy corresponding to graphics of each group for designating one or more graphics. CONSTITUTION:Each logical hierarchy in logical connecting information 15 expressed hierarchically of an integrated circuit is expressed by a graphic, respectively, an arrangement of those graphics is determined by an interactive graphic processing, one or more graphics are designated as a group, and by the logical hierarchy corresponding to graphics of each group, one layout block is constituted, respectively. That is, the arrangement of the graphics corresponding to each logical hierarchy in the logical connecting information 15 is determined by a graphic operation processing, those graphics are grouped, and each group is set as one layout block. In such a way, the constitution of the layout block can be understood directly, and the constitution of an optimal layout block is facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout block construction method and system, and more particularly, to a layout block construction method and system capable of constructing a layout block by interactive graphic operation in the layout design of an integrated circuit. Regarding

[0002]

2. Description of the Related Art In logic design, hierarchical design is performed in which logic circuits having small functions are sequentially assembled. Therefore, what is obtained by the logical design is the logical connection information expressed in a hierarchical manner. On the other hand, in the layout design, the logical connection information obtained in the logical design is converted into a set of layout blocks and automatically laid out by a layout program.

Here, the following two methods are known as methods for converting the logical connection information into a set of layout blocks. The first is a method in which conversion instruction information describing the layout block configuration is created by text editing, the conversion instruction information is input to a conversion execution program, and conversion is executed. The second is a method of automatically converting the logical connection information into a set of layout blocks using a predetermined evaluation function (see Japanese Patent Laid-Open No. 63-78566).

[0004]

The way of arranging the layout blocks has a great influence on the chip size and operating speed of the integrated circuit. Therefore, it is desired to optimally configure the layout block.

However, in the above-mentioned first conventional method, since the layout block configuration is described by text editing, it is difficult to understand it directly, and the optimal layout block configuration becomes difficult. There is a point. on the other hand,
The above-mentioned second conventional method has a problem that it is difficult to select an evaluation function and the layout block is not always configured optimally.

Therefore, an object of the present invention is to provide a layout block construction method and system which can easily construct an optimum layout block.

[0007]

According to a first aspect of the present invention, according to the present invention, each logical hierarchy in logical connection information expressed hierarchically of an integrated circuit is expressed by a graphic, and the layout of the graphic is interactive. (EN) A layout block configuration method characterized in that one layout block is determined by graphic operation processing, one or more graphics are designated as a group, and one layout block is configured by a logical hierarchy corresponding to the graphics of each group.

According to a second aspect of the present invention, the present invention expresses each logical hierarchy in the logical connection information expressed hierarchically of an integrated circuit by a graphic and arranges or moves the graphic corresponding to the specified logical hierarchy at a specified position. Arrangement of logical hierarchy
The correction processing means, the coupling degree display processing means for displaying the strength of coupling between the designated logical layer and another logical layer or layout block, and the graphic corresponding to the designated logical layer and another logical layer or layout block. A connection degree graphic display process that graphically displays the strength and direction of the connection between the shapes,
Layout block configuration / modification means that configures the logical hierarchy corresponding to the graphic included in the specified area as one layout block, and the area of the layout block that estimates the necessary and sufficient area of the specified layout block and graphically displays the area. There is provided a layout block configuration system comprising an estimation processing means.

[0009]

In the layout block construction method of the present invention according to the first aspect described above, the layout of the graphics corresponding to each logical hierarchy in the logical connection information is determined by interactive graphics operation processing, these graphics are grouped, and each group is grouped. Is one layout block. Therefore, it is possible to directly understand the configuration of the layout block, and it becomes easy to configure the optimal layout block.

In the layout block construction system of the present invention according to the second aspect, the layout block construction method of the present invention can be preferably realized, and the optimum layout block construction can be easily realized.

[0011]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. The present invention is not limited to this.

FIG. 1 is a block diagram of an example of a chip layout system for implementing the layout block construction method of the present invention. The chip layout system 1 includes a keyboard 11, a mouse 12, a display device 13,
It is composed of a central processing unit 14, an input information storage unit 15, and an output information storage unit 16.

The keyboard 11 is a command input device for inputting an instruction by a character string. The mouse 12 is a point input device for inputting layout position information of a graphic.

The input information storage device 15 stores logical connection information created by logical design. An example of the logical connection information is shown in FIG. The output information storage device 16 stores layout block configuration instruction information obtained by the layout block configuration instruction method of the present invention.

The central processing unit 14 has a command input processing means 21, a chip floor plan processing means 22, and a display output processing 23.

The command input processing means 21 is a program that receives a command input by the designer and transfers control to the corresponding process, and also receives the layout position information of the graphic input by the designer and passes it to the corresponding process.

The chip floor plan processing means 22 is a program for executing processing corresponding to a command, and includes a layout block configuration instruction processing means 30 and a block arrangement / block arrangement / processing means.
It comprises a correction processing unit 40. The layout block configuration instruction processing means includes a logical hierarchy arrangement / correction processing 31 for arranging a logical hierarchy on a chip, a coupling degree display processing 32 for displaying a signal connection relationship between the logical hierarchy and blocks, and a logical hierarchy. And a layout block area estimation process 34 for estimating the size of a layout block configured in a logical hierarchy. The block placement / correction processing means 40 is a program for changing the definition and placement of a layout block already defined and placed.

The display output processing means 23 is a program for outputting and displaying the processing result on the display device 13.

The commands entered by the designer are as follows. 1. Command corresponding to logical hierarchy arrangement / correction processing 31 (1) ADCL [logical hierarchy name] [arrangement position] Example. ADCL I11 (Xa, Ya) Arranges the area of the logical hierarchy specified by [logical hierarchy name] such that the reference position (for example, lower left) of the area is at the coordinates specified by [arrangement position]. (2) MVCL [logical hierarchy name] [movement position] Example. MVCL I11 (Xb, Yb) Moves the area of the logical hierarchy specified by [logical hierarchy name] so that the reference position of the area is at the coordinates specified by [movement position]. (3) SWCL [logical hierarchy name 1] [logical hierarchy name 2] Example. SWCL I11 I2 [logical hierarchy name 1] position of logical hierarchy and [logical hierarchy name 2]
Swap the position of the logical hierarchy of.

2. Command corresponding to coupling degree display processing 32 (1) VCOM [logical hierarchy name or layout block name] Example. The number of signal lines between the logical hierarchy or layout block specified by VCOM I11 [logical hierarchy name or layout block name] and another logical hierarchy or layout block is displayed as the strength of coupling. (2) VTRM [logical hierarchy name or layout block name] Example. VTRM I11 The signal line between the logical hierarchy or layout block specified by [logical hierarchy name or layout block name] and another logical hierarchy or layout block is displayed by radial wiring.

3. Command corresponding to layout block configuration / change processing 33 (1) DFBL [layout block name] [area] Example. DFBL A X1, Y1, X2, Y2 All logical layers included in the designated area are made into one layout block designated by [layout block name]. The area may be designated using the mouse 12.

4. Layout block area estimation processing 3
Command for 4 (1) VEST [ALL or layout block name] Example. VEST A Estimate the necessary and sufficient area of all layout blocks or the layout block specified by [layout block name].

Next, the procedure for constructing the layout block will be specifically described with reference to the flow chart of FIG.
Steps S1 to S5 are a series of processes for arranging the logical hierarchy on the chip. Also, step S6
~ Step S9 is a series of processes for making an optimum layout block. The logical connection information is assumed to be loaded from the input information storage device 15 into the central processing unit 14.

In step S1, the ROM and RA whose layouts are manually designed and whose shapes / configurations have been determined in advance.
The designer arranges layout blocks such as M using the block arrangement / correction processing 40. An initial screen of the display device 13 is illustrated in FIG. Further, a screen after arranging the layout blocks of the ROM is illustrated in FIG.

In step S2, the designer determines the logical hierarchy to be arranged next by using the VCOM command of the coupling degree display processing 32. For example, after arranging the layout block of the ROM, if VCOM ROM is input, the coupling degree display processing 32 calculates the number of signals from the signal table of FIG. 13, and as shown in FIG.
As a coupling degree between the layout block of the OM and another logical hierarchy or layout block, the display device 1
Display in 3. From the display of FIG. 5, it can be seen that the logical hierarchy IU1 has the highest degree of coupling with the layout block ROM.
Therefore, the designer next decides to place the logical hierarchy IU1 near the layout block ROM.

In step S3, the designer determines the placement position of the logical hierarchy to be placed next by the VT of the coupling degree display processing 32.
Determined using the RM command. For example, if the logical layer to be arranged next is IU1, if VTRM IU1 is input, the coupling degree display processing 32 calculates the number of signals and the position of the terminal from the signal table of FIG. 13, and as shown in FIG. The logical hierarchy IU1 is temporarily arranged in the upper right corner, and the connection of the signal line between the terminal of the logical hierarchy IU1 and the terminal of another logical hierarchy or layout block is displayed on the display device 13 by the radial wiring. From the display of FIG. 6, the logical hierarchy I
It will be understood that U1 may be arranged at the upper right of the layout block ROM. Therefore, the designer decides to place the logical hierarchy IU1 in the upper right of the layout block ROM.

In step S4, the designer determines the logical layer to be arranged next by AD in the logical layer arrangement / correction process 31.
Place it using the CL command. For example, if the position where the logical hierarchy IU1 to be arranged next should be arranged is the upper right coordinates (XIU1, YIU1) of the layout block ROM, if ADCL IU1 (XIU1, YIU1) is input, the logical hierarchy arrangement / correction processing 31 is executed. , Fig. 7
As shown in FIG.
It is arranged on the upper right of the OM and displayed on the display device 13.

In step S5, the above steps S2 to S4 are repeated to arrange another logical hierarchy.
Display device 13 after arranging the logical hierarchy IU10
Is shown in FIG.

In step S6, the designer uses the DFBL command of the layout block configuration / change processing 33 to perform grouping of logical layers. For example, if the logical hierarchy IU1 and the logical hierarchy IU10 are to be one layout block LAY1, DFBL LAY1 is input, and the area including the logical hierarchy IU1 and the logical hierarchy IU10 is designated by the mouse 12, and the layout block configuration is changed. The change processing 33, as shown in FIG. 9, sets the logical hierarchy IU1 and the logical hierarchy IU10 into one layout block LAY1 and displays it on the display device 13.

In step S7, the layout block designer created so far estimates the necessary and sufficient area of the grouped layout block using the VEST command of the layout block area estimation processing 34. For example, in order to estimate the area of the layout block LAY1, if you input VEST LAY1, the layout block area estimation processing 34
However, as shown in FIG. 10, the layout block LAY1
The area before the area estimation and the area after the area estimation are displayed on the display device 13. The area estimation of the layout block is calculated by the linear expression (ax + b) of the logical amount x forming the layout block. Experimental values are used for the coefficients a and b.

In step S8, the designer determines whether or not the layout block displayed on the display device 13 has a good configuration, and if there is a bad point, the designer proceeds to step S9.
If it is good, the process of the layout block configuration method is ended. For example, if the layout block configuration is displayed as shown in FIG. 11A, since an invalid area exists, the process proceeds to step S9, and the layout block configuration is changed by the MVCL and SWCL commands. Return to step S7. This process is repeated, and when the configuration of the optimum layout block as shown in FIG. 11B is reached, the processing is ended. The optimized layout block configuration information is stored in the output information storage device 16 according to a designer's instruction. FIG. 14 shows an example of the layout block configuration information.

According to the above embodiment, the coupling degree display processing 3
2 and the layout block area estimation process 34 can be used while visually recognizing the layout block configuration planning work, and the optimal layout block configuration can be determined without error in a short time. Further, since the layout block configuration can be planned by the chip floor plan processing, the layout block configuration considering the entire chip can be determined and a high quality LSI chip can be designed.

In another embodiment, lines having different thicknesses or lines having different colors are used to display the strength of connection between logical layers, between layout blocks, or between logical layer layout blocks. ..

[0034]

According to the layout block construction method and system of the present invention, since the layout block construction is determined by interactive graphic operation processing, the layout block construction can be directly understood, and the layout block construction can be optimized. The layout block can be easily configured.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of a chip layout system that implements a layout block configuration method of the present invention.

FIG. 2 is a flowchart of a processing procedure example according to the layout block configuration method of the present invention.

FIG. 3 is a view showing an example of an initial screen.

FIG. 4 is a view showing an example of a screen after the manual blocks are arranged.

FIG. 5 is a view showing an example of displaying the execution result of a coupling degree display command.

FIG. 6 is a view showing an example of displaying an execution result of an inter-terminal connection display command.

FIG. 7 is a view showing an example of a display of execution results of a logical hierarchy arrangement command.

FIG. 8 is a view showing an example of a display of execution results of another logical layer placement command.

FIG. 9 is a view showing an example of displaying the execution result of a layout block configuration command.

FIG. 10 is an exemplary diagram showing a display of an execution result of a layout block area estimation command.

FIG. 11 is an explanatory diagram showing a block arrangement state on a chip.

FIG. 12 is a view showing an example of logical connection information.

FIG. 13 is an exemplary diagram of a signal table.

FIG. 14 is a view showing an example of layout block configuration information.

[Explanation of symbols]

 1 Chip Layout System 31 Logical Hierarchy Arrangement / Modification Processing 32 Coupling Degree Display Processing 33 Layout Block Configuration / Change Processing 34 Layout Block Area Estimation Processing

Claims (9)

[Claims] 1. A logical hierarchy in the logical connection information expressed hierarchically of an integrated circuit is expressed by a graphic, respectively.
A layout characterized in that the layout of these figures is determined by interactive figure manipulation processing, one or more figures are designated as a group, and one layout block is formed by a logical hierarchy corresponding to the figures in each group. Block configuration method. 2. The layout block constructing method according to claim 1, wherein the graphic operation processing includes logical layer arrangement / correction processing of arranging or moving a graphic corresponding to a specified logical hierarchy at a specified position. A layout block construction method characterized by: 3. The layout block constructing method according to claim 1, wherein the graphic manipulation processing displays a coupling degree display processing for displaying a coupling strength between the designated logical hierarchy and another logical hierarchy or layout block. A layout block configuration method comprising: 4. The layout block configuring method according to claim 1, wherein the graphic operation processing is performed between a graphic corresponding to a designated logical hierarchy and a graphic corresponding to another logical hierarchy or layout block. A layout block construction method comprising a degree-of-coupling graphic display processing for graphically displaying the strength and direction of the connection. 5. The layout block constructing method according to claim 4, wherein the degree-of-coupling graphic display processing uses a line connecting a graphic corresponding to a designated logical hierarchy and a graphic corresponding to another logical hierarchy or layout block. A layout block configuration method, wherein the connection between the lines is displayed, the strength of the connection is displayed according to the number or the display form of the lines, and the direction of the connection is displayed according to the position where the line emerges from the figure. 6. The layout block configuring method according to claim 1, wherein an area is designated, and a logical hierarchy corresponding to a graphic included in the area is set as one group. Layout block configuration method. 7. The layout block configuring method according to claim 1, wherein the necessary and sufficient area of the specified layout block is estimated and the area is displayed graphically. Layout block configuration method. 8. Arrangement of a logical hierarchy in which each logical hierarchy in logical connection information expressed hierarchically of an integrated circuit is expressed by a graphic and a graphic corresponding to the specified logical hierarchy is arranged or moved at a specified position. The correction processing means, the coupling degree display processing means for displaying the strength of coupling between the designated logical layer and another logical layer or layout block, and the graphic corresponding to the designated logical layer and another logical layer or layout block. Coupling degree graphic display processing for graphically displaying the strength and direction of connection between figures, layout block configuration / change means for configuring one layout block as a logical hierarchy corresponding to the figures included in the designated area, and designated layout A layout block area estimation processing means for estimating a necessary and sufficient area of the block and graphically displaying the area. Layout block configuration system. 9. A layout block configuration system, wherein each processing means of the layout block configuration system according to claim 8 is provided as part of a chip floor plan processing means for determining the layout of layout blocks on a chip. ..