JPH05145573A - Atm exchange node system - Google Patents

Abstract

PURPOSE:To attain optional combination of input and output communication lines by applying speed conversion to an inputted cell flow, giving the result to an ATM switch as a highest bit rate, implementing switching, applying speed conversion to the cell and outputting the result. CONSTITUTION:A bit flow from a 2/4 Gbps line 13k of an input communication line is given to a line terminator 106K, in which frame synchronization and cell synchronization are taken and the result is inputted to an ATM switch 101 as the 2/4 Gbps cell flow. A routing tag designating a path is added by the switch 101, the cell is transferred accordingly and a VPI/VCI is rewritten so as to be suitable for an output communication line, the tag is eliminated and the result is inputted to a line terminator 106K. The equipment 106K implements scramble of an information part of a cell and rewrites an HEC section and outputs the result to the output communication line. Thus, the input communication line and the output communication line at various bit rates are combined optionally with simple hardware.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a B-I using an ATM.
The present invention relates to an ATM switching node system for constructing an SDN (Broadband Integrated Services Digital Network).

[0002]

2. Description of the Related Art In recent years, as a method of transferring information by packet transmission, STM (Sync
hronous Transfer Mode; instead of
ATM (Asynchronous Transfer Mode) is drawing attention, and research and development is proceeding toward practical use.

ATM divides all information into fixed-length blocks called cells and adds an identification header to each cell to carry out unified information transmission, and each communication terminal uses a communication network as needed. It is a transfer mode characterized by passing cells, that is, using the information transfer capability of the communication network when the communication terminal requires it. Therefore, the ATM has an advantage that it can provide the communication terminal with an arbitrary information transfer rate required by the communication terminal, as compared with the STM in which the information transfer capability required for communication is secured at the time of call setup. From such characteristics,
ATM is in the limelight as a basic technology for constructing B-ISDN, which is a communication network that can centrally handle information such as voice, data, and moving images.

In order to construct a B-ISDN by ATM, an operation of transferring cells delivered from a plurality of input communication channels to a desired output communication channel according to the route information of the cells (this is called cell switching) It is necessary to realize a system for performing the above, that is, an ATM switching node system. In B-ISDN, 150 Mbps, 600 Mbps,
Communication channels of various bit rates such as 2.4 Gbps are used. However, in the conventional technique, there is a problem that the circuit scale becomes very large and the cost becomes high because the ATM switching node system is provided for each of the communication paths having different bit rates.

[0005]

As described above, since the conventional ATM switching node system is provided corresponding to each of the communication paths of different bit rates, the circuit scale is increased and the cost is also increased. There was a problem.

Therefore, an object of the present invention is to provide an ATM switching node system capable of accommodating an input communication path and an output communication path of various bit rates in an arbitrary combination.

[0007]

In order to solve the above problems, the present invention accommodates a plurality of input communication paths and output communication paths having different bit rates, and a cell input from each input communication path is set to the cell. In an ATM switching node system for outputting to a desired output communication path according to the added route information,
The cell flow from the highest bit rate input channel can be switched, and the cell flow from the highest bit rate input channel is input from the first input port to the highest bit rate output channel. Is connected to the switching means (ATM switch) that outputs from the first output port and the second input port of this switching means, and the cell flow from the input communication path with the highest bit rate can be concentrated. Means (ATM multiplexer),
A first stream conversion means is provided in the input section of the concentrator for converting the bit rate of the cell stream input to the input communication path excluding the input communication path of the highest bit rate into the bit rate of the output communication path of the highest bit rate. A speed converting means, a shunting means (ATM demultiplexer) connected to the second output port of the switching means and capable of shunting the cell stream of the bit rate of the output communication path of the highest bit rate, and the output of this shunting means. And a second speed conversion means provided in the section for converting the bit rate of the cell stream shunted from the shunt means into a bit rate of a desired output communication path excluding the output communication path of the highest bit rate. Is characterized by.

In the present invention, at least one of the switching means and the diversion means may have a copy function for outputting the cell flow from the common input communication path to the plurality of output communication paths.

In the present invention, the input communication path and the first
A line terminating device for supplying a cell flow and a clock for bit transfer to the corresponding first speed converting means may be provided between each of the speed converting means and each of the speed converting means.

Further, in the present invention, the cell flow from the corresponding second speed converting means is received between the output communication path and the second speed converting means, and bit transfer is performed to the corresponding second speed converting means. Each may have a line terminating device for providing a clock for use.

[0011]

As described above, according to the present invention, a cell flow from a plurality of input communication paths having different bit rates is appropriately subjected to speed conversion so that a predetermined common bit rate (the input communication path with the highest bit rate is obtained. Cell rate) of a plurality of output communication paths having different bit rates by performing a uniform switching here and then performing a speed conversion as necessary according to the speed. Output to the output communication path of any bit rate.

Further, since the ATM switch and the ATM demultiplexer include the copy function, the cell flow from any input communication path can be copied to any plurality of output communication paths and output.

Further, a line terminating device that gives cells to the first speed converting means gives a bit transfer clock to the first speed converting means, or a line terminating device that receives cells from the second speed converting means. By applying the bit transfer clock to the second speed converting means, the operating speed of the input section of the ATM multiplexer and the operating speed of the output section of the ATM demultiplexer can be specified from the line terminating device. As a result, it is possible to realize the function of connecting the line terminating device of an arbitrary speed to the input of the ATM multiplexer and the output of the ATM demultiplexer, that is, a so-called port-free function.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an ATM switching node system according to an embodiment of the present invention. As a plurality of input communication paths having different bit rates, a 150 Mbps line 11i (i = 1 to m) and a 600 Mbps line 12j ( j =
1-n) and 2.4 Gbps line 13k (k = 1-r)
In addition, an example of accommodating a 150 Mbps line 14i, a 600 Mbps line 15j, and a 2.4 Gbps line 16k as output communication paths having different bit rates is shown.

This ATM switching node system comprises an ATM switch 101 which is a switching means capable of switching a cell flow having a bit rate of 2.4 Gbps and an ATM multiplexer which is a concentrating means capable of concentrating a cell flow having a bit rate of 2.4 Gbps. (ATM-MUX) 102 and an ATM demultiplexer (ATM-DEM) which is a shunting unit capable of shunting a cell stream having a bit rate of 2.4 Gbps.
UX) 103 as a main component.

Each of the lines 11i, 12j and 13k of the input communication path has a 150 Mbps line terminator 104i, 60.
The 0 Mbps line terminating device 105j and the 2.4 Gbps line terminating device 106k are respectively connected, and the lines 14i, 15j and 16k of the output communication path are also 15
0 Mbps line terminator 104i, 600 Mbps line terminator 105j and 2.4 Gbps line terminator 106k
Are connected respectively. In the figure, line terminators 104i, 105j and 1 of each bit rate are shown.
Although 06k is shown separately, this is because the line terminators on the input communication path side and the output communication path side are shown separately, and here the input communication path side and the output communication path side are collectively referred to as the line terminator. To

Here, a 150 Mbps line terminating device 104i and a 600 Mbps line terminating device 105 on the input communication path side.
The output of j is connected to the input of the 2.4 Gbps ATM-MUX 102, and the output of the 2.4 Gbps line terminating device 106k is connected to the first input port of the 2.4 Gbps ATM switch 101. 2.4 Gbps ATM-MUX1
The output of 02 is connected to the second input port of the 2.4 Gbps ATM switch 101.

On the other hand, a 150 Mbps line terminating device 104i and a 600 Mbps line terminating device 105j on the output communication path side.
Is connected to the output of the 2.4 Gbps ATM-DEMUX 103, and the input of the 2.4 Gbps line terminating device 106k is connected to the first output port of the 2.4 Gbps ATM switch 101. 2.4 Gbps ATM-DEM
The input of UX103 is 2.4 Gbps ATM switch 10
1 to the second output port.

Also, as will be described later, 2.4 Mbps ATM
-The input unit of the MUX 102 has 150M on the input communication path side.
The first rate converter 112 for converting the bit rate of the cell stream output from the bps line terminating device 104i and the 600 Mbps line terminating device 105j into 2.4 Gbps.
Is provided. Also, in the same manner, 2.4 Mbps ATM-
The output section of the DEMUX 103 outputs a cell flow bit rate of 2.4 Gbps to the output channel 150 Mbps line terminator 104i and 600 Mbps line terminator 10.
150 Mbps and 600 M, which are the bit rates of 5j
A second speed converter 113 for converting to bps is provided.

Next, the operation of the ATM switching node system of this embodiment will be described. In this embodiment, the maximum bit rate accommodated is 2.4 Gbps, and therefore the ATM switch 101 operates at 2.4 Gbps.

First, a method of switching cells delivered from the 2.4 Gbps line 13k will be described. The bit stream delivered from the 2.4 Gbps line 13k of the input communication channel on the STM-16c frame structure is 2.4.
After the frame synchronization and the cell synchronization are established by the Gbps line terminating device 106k, the 2.4 Gbps cell flow is 2.4 Gbps.
s It is input to the ATM switch 101.

In the 2.4 Gbps ATM switch 101,
First, traffic monitoring is performed, and then a routing tag that specifies a route inside the ATM switch 101 is attached. After that, the cell is transferred to a desired output side according to the routing tag, and VPI (Virtual Path Identifie
r; virtual path identifier) / VCI (Virtual Channe
l Identifier; virtual channel identifier) is rewritten to that on the output communication path, the routing tag is removed, and the 2.4 Gbps line terminator 106k is again used.
Entered in.

The 2.4 Gbps line terminator 106k is
When a cell is received from the TM switch 101, the information section of the cell is scrambled and HEC (Header Error Contro
The part (l) is rewritten, the cell is put on the frame structure of STM-16c, and the result is output to the output communication path.

Next, the 2.4 Gbps line terminating device and the 2.4 Gbps ATM switch, which are blocks involved in switching cells on the 2.4 Gbps line, will be described in more detail. FIG. 2 shows the configuration of the 2.4 Gbps line termination device. In FIG. 2, the optical receiver module (OU
R) 201 is a functional element that performs photoelectric conversion.

The frame deassembler (FDA) 202 is a functional element that synchronizes the frame of the STM-16c frame according to the system defined by CCITT and outputs the payload of the frame as a bit stream.

The cell synchronization establishment unit (CSD) 203 is an FDA.
Is a functional element that detects the beginning of each cell while detecting / correcting a bit error in the header part of the cell using the HEC in the header part of the cell according to the method defined by CCITT from the bit stream given by .. CSD20
At the same time, 3 descrambles the information part of the cell according to the method defined in CCITT.

Network management cell add / drop unit (OMDI) 20
4 is OAM (Operation and Maintenance)
It is a functional element that performs cell branching, insertion, and loopback. Unlike the conventional STM switching system, in the ATM switching system in which there is no fixed time slot, the test of the cell communication path is performed by inserting a test cell called an OAM cell, and confirming that the OAM cell is normally handled. O
It is general to check the AM cell by branching or looping it back. Also in this embodiment, the cell communication path is tested by such a method. OMDI204
Are the functional elements provided for this test. OM
DI204 is the most ATM switch 10 of the line termination equipment.
It is provided at a position close to 1. As a result, the test of the link between the adjacent nodes by the loopback of the OAM cell between the adjacent nodes and the test of the ATM switch in the system can be realized by inserting, branching and looping back the OAM cells.

Cell Information Scrambler (CIS) 205
Is output from the ATM switch 101 and the OMDI 204
It is a functional element that scrambles the information part of the cell that has passed through according to the method defined in CCITT. At the same time as this scrambling, the CIS 205 sets a value in the HEC field of the header part of the cell according to the method defined in CCITT.

The optical transmission module (OUS) 207 is a C
The cell output from the IS 205 is mapped to the payload portion of the STM-16c frame format defined by CCITT and output.

FIG. 3 shows a 2.4 Gbps ATM switch 101.
Shows the configuration of. ATM switch 101 described here
The AT included in the ATM switching node system facilitates the setting of a virtual path or a virtual channel that is a logical path through which cells are transferred inside the B-ISDN.
The M switch has a configuration that takes into consideration the fact that it is desirable to have a simple configuration.

As shown in FIG. 4, the 8 × 8 crossbar switch 301 is composed of 8 × 8 crosspoints and a circuit capable of setting ON / OFF of the crosspoints by information input in advance from each input port. .. When ON / OFF of each cross point is set in advance and a cell is input from the input port, the cell is output from the output port according to the state of the cross point. Here, multiple cross points connected to one input port are turned on at the same time.
Then, the same cell is simultaneously output from a plurality of output ports. Thereby, the copy connection can be easily realized.

The SW interface 3 is provided before the input port and after the output port of the 8 × 8 crossbar switch 301.
As 031 to 3038, a cell processing function as described in 1) to 6) below is added.

1) Traffic Measurement / Policing Function This function is realized by the traffic monitoring / violation detection unit (TOVA) 305 and TOVA RAM 304. As the parameter measured here, for example, while the virtual path VP or the virtual channel VC is set, the number of cells belonging to the VP / VC that has passed through the TOVA 305 or the TOVA 305 during a predetermined cycle period is set. Passed VP or V
The number of cells for each C can be considered. The count values of these cell numbers are held in the TOVA RAM 304. The TOVA 305 extracts the VPI or VPI + VCI of the cell each time the cell passes by one, reads the word of the TOVA RAM 304 in accordance with it, increments it, and writes it to the same address. When the incremented result becomes larger than a predetermined value, the passing cell is discarded as a violation of the agreement, or a policing operation such as attaching a violation tag to the cell is performed. Here, when counting the number of cell passages for each VP / VC within a predetermined cycle period, TO counts at the beginning of the cycle period.
It is necessary to reset the VA RAM 304, and the TOV
Although there is a possibility that it cannot be realized due to insufficient throughput of the A RAM 304, this problem can be solved by using the RAM with reset.

2) Routing Tag (ATM Switch Routing Information) Addition Function This function is realized by the routing tag addition unit (RTA) 307 and the roofing tag table (RTT) 306. The RTA 307 extracts the VPI or VPI + VCI from the passing cell, and the VPI or VPI +
The VCI is used to look up the RTT 306 and obtain the information designating the output port to which the cell should be output, that is, the routing tag. In order to support the copy connection, the routing tag adopts a so-called bitmap method that specifies whether or not to output the cell for each output port.

Further, in order to support the copy connection, VPI or VPI + VC on the output communication path side
The I value must be rewritten on the output side of the ATM switch 101. Therefore, in the RTA 307, in addition to the routing tag, the identifier attached to the SW interface is added to the cell.

3) Switch input buffering function This function is realized by the input buffer (IBUF) 308 provided in the input port of the ATM switch 101. To ensure the throughput of the ATM switch 101,
It is desirable that the cell transfer rate in the 8 × 8 crossbar switch is about twice the cell transfer rate on the input / output communication path. In the ATM switch 101 of this embodiment, 4.8G is used.
A cell transfer rate of bps is desirable. The cells are buffered at the input of the switch for this speed conversion. Further, when a state where head cells of a plurality of IBUFs head toward the same output port, so-called HOL blocking, occurs, which IBUF the cell is to be output from is determined by the contention control circuit as described later, IB
The UF also notifies the contention control circuit of information necessary for the contention control circuit to detect HOL blocking and determine the output cell, that is, a routing tag, and also has a function of temporarily suppressing the cell output according to the determination by the contention control circuit. Have both.

4) Switch output buffering function This function is realized by the output buffer (OBUF) 309 provided in the output port of the ATM switch 101. As described above, cells are transferred at 4.8 Gbps inside the ATM switch 101. This OBUF 309 is provided in order to convert this to a cell transfer rate on the output communication path, that is, 2.4 Gbps. 5) Header (VPI / VCI) conversion function This function is realized by the header rewriting unit (HRW) 310 and the header conversion table (HTT) 311. In HRW310, the VPI or VP of the cell
The operation of changing I + VCI from the value on the input communication path to the value on the output communication path is performed. From the passing cell, VP
A new VP on the output communication path by referring to the HTT 311 with I or VPI + VCI and the one added to the input side and the identifier of the SW interface added as a key
Obtain the value of I or VPI + VCI and overwrite these on the passing cell.

6) Routing tag deletion function This function is (routing tag deletion unit) RTD311.
It is realized by. In the RTD 311, the routing tag added by the RTA 307 and the identifier of the SW interface are deleted, and the cell format is transformed into the cell length standardized by CCITT.

On the other hand, the contention control circuit 302 is the IBU of each SW interface 3031 to 3038 as described above.
It has a role of detecting the state where the leading cell of F collides and determining from which buffer the cell is output.

FIG. 5 shows how a routing tag is given from each input buffer to the contention control circuit 302. As shown in the figure, the routing tags are provided to the conflict control circuit 302 in order from the bit indicating whether or not to output the cell from each input port to the output port 1 to the bit for the output port 8.

FIG. 6 shows a configuration example of the competition control circuit 302. This configuration is a so-called systolic array, and is designed so that the competition control operation can be realized by sequentially flowing the data shown in FIG. 5 from left to right in the figure.

In FIG. 6, the priority control 8 × 8 crossbar switch 601 replaces the routing tags given from the input buffers 1 to 8 by the value of the priority control counter 602 as follows. Change the order of replacement by AT
It is performed at every beginning of a cell cycle, which is a cycle in which the M switch 101 transfers one cell.

1) In order from the top in FIG.
The routing tags from 2, ... 8 are output respectively. 2) The input buffers 2, 3, ...
Output the routing tags from each. 3) In FIG. 6, the input buffers 3, 4, ...
The routing tags from 1 and 2 are output respectively. 4) In order from the top in FIG. 6, the input buffers 4, 5, ...
The routing tags from 1, 2 and 3 are output respectively. 5) In FIG. 6, the input buffers 5, 6, ...
The routing tags from 1, 2, ... 4 are output respectively. 6) In order from the top in FIG. 6, the input buffers 6, 7, 8, 1, 1
The routing tags from 2, ... 5 are output respectively. 7) In order from the top in FIG. 6, the input buffers 7, 8, 1, 2,
The routing tags from 6 are output respectively. 8) In order from the top in FIG. 6, the input buffers 8, 1, 2, ... 7
Output the routing tags from each. afterwards,
Return to 1).

According to the contention control algorithm to be described later, it becomes difficult to obtain the transmission permission from the upper side to the lower side of FIG. 6 on the output side of the 8 × 8 crossbar switch 601 for priority control. Can be changed to make the cell transmission opportunities from each input buffer uniform.

At the output part of the priority control 8 × 8 crossbar switch 601, a 1-bit free area is inserted after each bit of the routing tag. This empty area is a cell array that follows the priority control 8 × 8 crossbar switch 601, and is used for reservation of an output buffer. The information held in this empty area is called output buffer allocation information. The output buffer allocation information will be described below assuming that a logical value of 0 is entered as an initial value.

The center of the competition control circuit is the array cell 603.
i and 604jk. Array cells 603i and 604j
As shown in FIG. 6, k is diagonal to the array cell 603i,
Array cells 604jk are arranged in the other portions, respectively, and form a square matrix. In the square matrix, communication paths that allow data to pass from left to right in the figure are between adjacent array cells in each row, and communication paths that allow data to pass from the upper left to lower right in the figure are diagonally adjacent. Each is provided between array cells. By using these communication paths to flow the data from the 8 × 8 crossbar switch for priority control to the square matrix in a pipeline manner, when the data comes out from the square matrix, the competitive control is terminated, that is, The decision to transfer the cell from the input buffer to the output buffer is complete.

Next, the data processing performed by this square matrix will be described in more detail. This square matrix represents a cell cycle in which cells are transferred on the crossbar switch 301 shown in FIG.
Double, that is, it operates every cycle divided into 16 pieces. This cycle is called a reservation cycle.

On the communication path provided between the adjacent array cells in each row of the square matrix, 2-bit information is transferred from left to right in FIG. 6 for each reservation cycle. On the communication path provided between adjacent array cells on the diagonal of the square matrix, 1-bit information is transferred from the upper left to the lower right for each reservation cycle.

The array cell 604jk is simply a shift register having a 2-bit length, and operates to output 2-bit information received from the left adjacent cell at the start of a certain reservation cycle to the right adjacent cell at the start of the next reservation cycle. To do. The array cell 603i is a functional element that performs the following main part of the operation of determining the cell to be transferred to the output port, and is called a buffer reserved cell here.

That is, if at the start of the reservation cycle, the bit received from the upper left neighbor cell is 1, and one of the two bits received from the left neighbor cell is 1 in the routing tag, , At the start of the next reservation cycle, pass the following data to the lower right and adjacent cells on the right. 1) Right adjacent cell: 1 bit in the routing tag is 1, and output buffer reservation information is also 1.

2) Lower right neighbor cell: 0 otherwise, the right neighbor cell receives the information received from the left neighbor cell at the beginning of the previous reservation cycle,
The information received from the upper left adjacent cell at the start of the previous reservation cycle is directly output to the lower right adjacent cell.

The meaning of this operation is as follows. The information that the buffer reserved cell receives at the beginning of the reservation cycle has the following meaning. (A) 1 bit received from the upper left array cell: 0 if it has been determined that there is a cell to be output to the output buffer of interest, and it is determined that there is a cell to be output to the output buffer of interest. 1 if not. This information is called output buffer allocation information.

(B) 2 bits received from the left array cell: 1 bit received first is 1 bit of the routing tag. The next received 1 bit is output buffer reservation information indicating whether or not the output buffer is reserved for outputting the cell having the routing tag.

Therefore, the operation of the buffer reserved cell in each reservation cycle will be described below. If the received output buffer allocation information indicates that the cell to be transferred to the output buffer has not been allocated yet, and the bit to be transferred to the output buffer is not allocated to the output buffer which is not allocated yet due to 1 bit of the routing tag. If, on the other hand, the cell was shown to be output, then reserve the transfer of that cell towards its output buffer. Further, setting the output buffer reservation information to 1 notifies each array cell on the right side of the square matrix that the output buffer is reserved to transfer the cell, and sets the output buffer allocation information to 0 to the lower left of the square matrix. To each output array cell that its output buffer has already reserved a cell to be transferred.

When a square matrix is formed as shown in FIG. 6 by the array cell operating in this way and information as shown in FIG. 5 is flown from the left side of the square matrix, it operates as shown in FIGS. 7 to 22. Here, it is assumed that 1 is always input to the array cell at the upper left of the square matrix as the output buffer allocation information to be sent toward the diagonal of the matrix.

Here, the information flowing in each row of the square matrix is
It is the routing tag of the leading cell of a certain input port, that is, information indicating whether or not to output for each output port, and information inserted after each bit of the routing tag. Therefore, if the buffer reservation cell 603i operates as described above, after the information input to the square matrix passes through the square matrix, the output buffer reservation information following the bit set to 1 in the routing tag flowing in each row. Is all 1
If only cells with routing tags flowing in that row are transferred to the output buffer, then multiple input ports are not connected to a single output port on the crossbar switch shown in FIG. It can be seen that it can be guaranteed that no collision will occur.

Further, from the upper left of the array cell at the upper left of the square matrix at the start of each reservation cycle, as output buffer allocation information, if the respective output buffers are not full, 1,
If it is full, 0 is sequentially given at the timings described below, and if the output buffer is full, control that does not transfer cells to that buffer, that is, flow control can be realized.

At the start of the first reservation cycle: input of output buffer 1 is full / not input At the start of second reservation cycle: input of output buffer 2 is full / not input At the start of third reservation cycle: output Buffer 3 full / no input At the start of the 4th reservation cycle: Output buffer 4 full / no input At the start of the 5th reservation cycle: Output buffer 5 full / no input 6th At the start of the reservation cycle: Input the output buffer 6 full / not input At the start of the 7th reservation cycle: Input the output buffer 7 full / not input At the start of the 8th reservation cycle: Output buffer 8 full Enter Yes / No

The routing tag containing the output buffer reservation information that has passed through the square matrix formed by the array cells 603i and 604jk is input to the array cell 605i at the output of each column of the square matrix. In this array cell, the input routing tag and output buffer reservation information are observed, and if the output buffer reservation information after the bit of the routing tag that is 1 is all 1, then the following 8 × 8 crossbar switch for priority control 1 is output to 606, and 0 is output otherwise. That is, the information for returning the result of the competition control in the square matrix to each input buffer is created. This array cell is called a determination circuit.

8 × 8 crossbar switch 606 for priority control
Refers to the value of the priority control counter 602 and guides the information output from the determination circuit to a desired input buffer. The input buffer can receive this information and know whether or not it can output the first cell in the next cell cycle.

Next, a method of accommodating lines other than the 2.4 Gbps line in this embodiment will be described in detail. In this embodiment, as described above, it is considered to accommodate 600 Mbps lines and 150 Mbps lines as lines other than the 2.4 Gbps lines.

FIG. 23 shows a 150 Mbps line terminating device 104.
i, FIG. 24 shows the configuration of the 600 Mbps line terminating device 105j. As shown in FIGS. 23 and 24, 150M
The bps line terminator 104i and the 600 Mbps line terminator 105j have almost the same configuration. Practically, OUR which is an opto-electric converter, OUS which is an electro-optical converter,
Except for FDA which is (STM-1 / STM-4c) frame deassembler and FAS which is (STM-1 / STM4c) frame assembler, all LSIs developed for 600 Mbps line terminating device 105j are for 150 Mbps line terminating device 104i. It can be diverted to. Therefore, the line terminal devices 104i and 105j will be collectively described.

150 Mbps / 600 Mbps input communication path 1
The optical signal input from 1i / 12j is photoelectrically converted into an electrical signal by the optical receiving module OUR and output to the frame deassembler FDA. This signal is 1
If 50Mbps, 600M of STM-1 frame structure
If it is bps, it is assumed that a cell is mapped to each bay road portion of the STM-4c frame structure.

In the frame deassembler FDA, the electric signal received from the optical receiving module OUR is frame-synchronized, the payload portion is cut out and input to the cell synchronization establishment unit CSD.

In the cell synchronization establishment unit CSD, the CCITT is selected from the bit string received from the frame deassembler FDA.
According to the method standardized by CCITT, while knowing the head of the cell according to the method standardized by, the cell head is marked and input to the cell branching / insertion unit OMDI,
The information part of the cell is descrambled and output to OMDI. The cell drop / insert unit OMDI drops / inserts an OAM cell for testing a cell communication path.

As shown in FIG. 1, 150 Mbps / 600
The Mbps lines 11i and 12j are connected to the ATM switch 1 through the ATM-MUX 102 and the ATM-DEMUX 103.
Housed in 01. Therefore, the cells on the plurality of input communication paths are concentrated on one input port (second input port) of the ATM switch 101. In order to distinguish the virtual path and the virtual channel VP / VC on another input channel on the second input port, 150 Mbps / 6
00 Mbps line termination devices 104i and 105j ATM-
At the exit portion to the MUX 102, the header rewriting units HRW and HRW RAM temporarily rewrite each VPI / VCI identifier.

As will be described later, the ATM-DEMU
Since the cell is copied also in X103, ATM-D
HRW, HRW again at the entrance of 150 Mbps / 600 Mbps line terminator 104i, 105j of EMUX 103
The VPI / VCI is once rewritten by the RAM. A
Since the TM-DEMUX 103 has only one input port, the VPI / VCI of the copied cell has the same ATM.
-Each line termination device 104 connected to the DEMUX 103
It is always unique on the cell sending side of i, 105j. Therefore, as compared with the HRW and HRW RAM used in the SW interface of the ATM switch shown in FIG.
0 Mbps / 600 Mbps line terminator 104i, 105
The HRW, HRW RAM used in j is simple.
That is, in the HRW and HRWRAM used in the SW interfaces 3031 to 3028 of FIG. 3, VPI / VC
In addition to the old VPI / VCI for I rewriting, the input port of the switch to which the cell is input is VPI / VCI.
It must be used as a key to refer to the table, but 150
Mbps / 600 Mbps line terminator 104i, 105j
In the HRW and HRW RAM used in the above, only the old VPI / VCI may be used as a key for referring to the VPI / VCI table in order to rewrite the VPI / VCI.

The cell stream input from the ATM-DEMUX 103 is subjected to VPI / VCI conversion by the HRW, dropped / inserted by an OAM cell by the cell branch / insertion unit OMDI, and then C by the cell information section scrambler CIS.
The HEC is calculated in accordance with the method standardized by CITT, the HEC field of the header part is rewritten, and at the same time, the information part of the cell is scrambled and then output to the frame assembler FAS.

When the frame assembler FAS receives the cell flow from the cell information section scrambler CIS, the frame assembler FAS determines the cell flow as STM-1 / STM-4c defined by CCITT.
It is mapped to the payload part of the frame structure of and is output to the optical transmission module OUS. Optical transmitter module OU
S converts an electric signal input from the frame assembler FAS into an optical signal and outputs the optical signal to the output communication path.

The operation of the ATM-MUX 102 will be described in detail with reference to FIGS. 25, 26 and 27. FIG. 25 shows the overall structure of the ATM-MUX 102,
FIG. 26 is a diagram showing a configuration of the multiplexer MX2 which is a component of the ATM-MUX 102.

As shown in FIG. 25, the ATM-MUX10
2 is an ATM multiplexer (MX2) 2 with 2 inputs and 1 output
It has a configuration in which 51 to 254 are connected in a tree shape. As shown by the dotted line, flow control is applied from the input unit of the root multiplexer 254 to the output unit of the leaf multiplexer 251 to prevent cell discard in the ATM-MUX 102. Leaf multiplexer 251
The bit rate of the cell flow to the input section of is 150 Mbps, and that from the line terminating device 104i is 150 Mbps.
600 Mbps from the line terminating equipment 105j is 600
It becomes Mbps. On the other hand, from the output part of the leaf multiplexer 251 to the output part of the root multiplexer 254, a cell stream having a bit rate of 2.4 Gbps is handled. Therefore, the leaf multiplexer 251 has 15
It has the first speed converter 112 shown in FIG. 1 for performing speed conversion of 0 Mbps / 600 Mbps → 2.4 Gbps.

FIG. 26 shows the 2-input 1-output A shown in FIG.
The structure of a TM multiplexer (MX2) is shown. The buffers 261 and 261 are independently provided to the two input ports A and B, respectively.
62 is provided. The selector 263 alternately extracts cells from these buffers 261 and 262 and outputs them. The buffers 261 and 262 are the first speed converter 1
261 and 263 to the buffer to operate as 12
Cell input is synchronized with the data CK supplied from the input ports A and B, while cell output from the buffers 261 and 262 is synchronized with the data CK output from the output port. The buffers 261 and 262 change the clocks. In this way, if cell input is performed in synchronization with the clock given from the input port,
150 Mbps line terminator 104i and 600 Mbps
Any of the line terminators 105j is an arbitrary ATM-MUX.
There is also an advantage that it can be connected to the input port of 103, that is, a port-free structure can be realized for the ATM-MUX 103.

Further, multiplexers 251 to 254
In order to realize flow control in the ATM-MUX 103 (control not to send cells when the destination buffer is full), the function to receive the flow control information from the output port and the flow control information from the input port are provided. Each has a function to send out.

The multiplexer (MX2) shown in FIG.
FIG. 27 shows an example of operation states of 251 to 254. The figure shows 6
00 Mbps line terminator 104i = 3, 150M
This is an operation when n = 4 bps line terminators 105j are connected,

1) If only one of the buffers holds a cell, the cell is output from that buffer. 2) If both buffers hold the cell, the cells are alternately output from those buffers. 3) It is assumed that the cell transmission is stopped if the destination buffer is full. As shown in FIG. 27, 2.4G having one cell on the 150 Mbps line 104i and the 600 Mbps line 105j.
You can see how the lines are being concentrated on the bps line. Also, from the figure, it is understood that when the 150 Mbps line terminating device 104i and the 600 Mbps line terminating device 105j are connected, the buffer of each input port of the multiplexers 251 to 254 requires at least 3 cells. Furthermore, if there is a buffer of three cells or more and the flow control is performed, it is understood that the buffer is not required on the side of the line terminating device.

Next, the operation of the ATM-DEMUX 103 will be described with reference to FIGS. 28, 29 and 30. FIG. 28 is a diagram showing the overall configuration of the ATM-DEMUX 103, and FIG. 29 is a diagram showing the configuration of the demultiplexer DX2 which is a component of the ATM-DEMUX 103.

As shown in FIG. 28, the ATM-DEMUX
103 is a 2-input 1-output ATM demultiplexer (DX
2) 281 to 284 are connected in a tree shape, and the ATM-DEMUX 10 is connected to the input side of the root demultiplexer 281.
A routing tag addition unit (RTA) 285 for adding a routing tag for designating a passage route of cells in the cell 3 is arranged, a routing tag table (RTT) 286 is connected to the RTA 285, and an output of the leaf demultiplexer 284. The routing tag added by RTA286 on the side is deleted, and the cell flow of 2.4 Gbps is set to 1
An output buffer (OBUF) 289 is arranged as the second speed converter 113 of FIG. 1 for speed conversion into a cell flow of 50 Mbps or 600 Mbps.

The cell stream output from the ATM switch 101 in FIG. 1 is first converted by the RTA 285 into a cell format with a routing tag added in the ATM-DEMUX 103 as shown in FIG. RTA
At 285, the VPI or VPI + of the input cell
The header conversion table (HTT) is referenced with the VPI as a key, and the routing tag obtained thereby is added to the cell and output.

The cell stream output from the RTA 285 passes through the tree formed by the demultiplexers (DX2) 281-284 and is transferred or copied toward a desired output communication path.

FIG. 29 shows the demultiplexer (DX2) 2
81 to 284 are shown. The cell flow input from the input port is output by the selector 291 to one or both of the output ports A and B. The output port that is output is analyzed by the routing tag analysis unit 292 that receives the routing tag of the cell. The routing tag analysis unit 292 selects the selector 291 based on the analysis result.
To control.

As shown in FIG. 30, the routing tag has a bit designating whether to output a cell to the output port A and a bit designating whether to output a cell to the output port B of the tree. The configuration is such that it is specified for each depth node. If you want to copy the cell at a certain depth, turn both of these bits ON.

In the output buffer (OBUF) 289 provided in the output section of the ATM-DEMUX 103, the cell flow that has passed through the tree of the demultiplexers (DX2) 281 to 284 is temporarily held, and the routing tag attached by the RTA 285 is added. Removed, 150 Mbps or 60
The speed is converted to 0 Mbps and output. here,
The cell output from the OBUF289 is used for each line termination device 104.
Bit CK given from i, 105j and 106k
If it is performed in synchronism with the above, like the port on the line terminating device side of the ATM-MUX 102, 150M can be set to an arbitrary port.
It is possible to realize a so-called port-free function that can connect both the bps line terminal device 104i and the 600 Mbps line terminal device 105j.

Considering to reduce the hardware scale of the demultiplexer (DX2), it is desirable not to place a buffer in DX2. However, if no buffer is placed in DX2, ATM-DEMUX203
Since the flow control cannot be applied within the output buffer (O
Cell discard may also occur at the output of BUF) 289. Therefore, the OBUF289 needs to have a scale capable of holding a relatively large number of cells (about 256 cells).

By the way, if the demultiplexer DX2 having the structure in which the buffer 293 is arranged as shown in FIG. 31 is used, the OBUF 289 to the ATM-DE are used.
Flow control can be applied to the path to the MUX 104. Within the ATM switching node system, ATM-DEM
OB of the ATM switch 101 from the output of the UX 103
If the flow control is applied up to the UF, the buffers inside the system operate in cooperation with the flow control, so that a better discard characteristic can be obtained with the same buffer amount.

Here, an 8 × 8 ATM switch, which is created by combining unit switches 321 with 2 inputs and 2 outputs as shown in FIG. 32, such as a Banyan network, is used instead of the 8 × 8 crossbar switch. Then, ATM-MU
Multiplexer (MX2) and A constituting X102
The demultiplexer (DX2) forming the TM-DEMUX 103 can also be realized by this unit switch, and the types of LSIs forming the system are reduced. 32, 322 and 323 are buffers and 324.
Is a transfer control unit. As the unit switch 321 having 2 inputs and 2 outputs, the present inventors have previously proposed Japanese Patent Application No. 1-135881.
Demultiplexer (DX) of the cell switch disclosed in No. 9
It is more desirable to adopt the cell copy function added in 2) because the throughput of the switch network composed of the unit switches 321 is improved.

[0086]

As described above, according to the present invention, the cell flow from a plurality of input communication paths having different bit rates is appropriately subjected to speed conversion so that the predetermined maximum bit rate of the input communication path is obtained. A cell stream having the same bit rate is given to the ATM switch, and after performing uniform switching here, speed conversion of the bit rate is appropriately performed so that any bit of a plurality of output communication paths having different bit rates can be obtained. The rate can be output to the output channel. That is, the ATM switching node system of the present invention can accommodate an arbitrary combination of input communication paths and output communication paths of various bit rates with a simple hardware configuration.

Further, by incorporating a copy function in the ATM switch and the ATM demultiplexer, the cell flow from the input communication path of an arbitrary bit rate is copied and output to a plurality of output communication paths of an arbitrary bit rate. You can

Further, the line terminating device that gives cells to the first speed converter gives a bit transfer clock to the first speed converter, and the second line terminating device receives cells from the second speed converter. It is possible to specify the operating speed of the input part of the ATM multiplexer and the operating speed of the output part of the ATM demultiplexer from the line terminator by applying the bit transfer clock to the speed converter of
A line terminator of any speed can be connected to the input section of the ATM multiplexer or the output section of the ATM demultiplexer.
A port-free function can be realized.

As described above, since the ATM switching node system according to the present invention can accommodate lines of various bit rates, the number of virtual paths VP or virtual channels VC that can be set at the same time is set for each line of each speed. It is possible to consider the choice of setting differently or the same. For example,
Considering that 4096 VPs or VCs can be set simultaneously on a 2.4 Gbps line, 150 Mbps / 600 Mbps
s Do you think you can set 4096 lines on the line as well?
Alternatively, on a 150 Mbps line, 1/16 on a 2.4 Gbps line, that is, 256 VPs or VCs can be set at the same time, and on a 600 Mbps line, 1/4 on a 2.4 Gbps line, that is, 1024 lines. VP
Alternatively, it may be considered that VC can be set at the same time.

Considering that the same number of VCs or VPs as 2.4 Gbps lines can be set on a line having a lower bit rate than 2.4 Gbps lines, the number of VCs or VPs set is limited to 2.4 Gbps lines only. Flexible VP
Alternatively, the VC can be set. On the other hand, 2.4G
If it is possible to set only a smaller number of VPs or VCs than the bps line, it is necessary to manage the number of VPs or VCs set at two places on the ATM switch input port and each line termination device when setting VPs or VCs. ,
It lacks flexibility when setting VP or VC,
The effect that the capacity of various tables of the line termination device can be reduced is obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an ATM switching node system according to an embodiment of the present invention.

FIG. 2 is a diagram showing an overall configuration of a 2.4 Gbps line terminating device in FIG.

FIG. 3 is a diagram showing a configuration of an ATM switch in FIG.

FIG. 4 is a diagram showing a configuration of an 8 × 8 crossbar switch in FIG.

5 is a diagram showing a format of input information to the competition control circuit in FIG.

FIG. 6 is a diagram showing a configuration of a competition control circuit.

FIG. 7 is a diagram for explaining the operation of the competition control circuit.

FIG. 8 is a diagram for explaining the operation of the competition control circuit.

FIG. 9 is a diagram for explaining the operation of the competition control circuit.

FIG. 10 is a diagram for explaining the operation of the competition control circuit.

FIG. 11 is a diagram for explaining the operation of the competition control circuit.

FIG. 12 is a diagram for explaining the operation of the competition control circuit.

FIG. 13 is a diagram for explaining the operation of the competition control circuit.

FIG. 14 is a diagram for explaining the operation of the competition control circuit.

FIG. 15 is a diagram for explaining the operation of the competition control circuit.

FIG. 16 is a diagram for explaining the operation of the competition control circuit.

FIG. 17 is a diagram for explaining the operation of the competition control circuit.

FIG. 18 is a diagram for explaining the operation of the competition control circuit.

FIG. 19 is a diagram for explaining the operation of the competition control circuit.

FIG. 20 is a diagram for explaining the operation of the competition control circuit.

FIG. 21 is a diagram for explaining the operation of the competition control circuit.

FIG. 22 is a diagram for explaining the operation of the competition control circuit.

23 is a diagram showing a configuration of a 150 Mbps line terminating device in FIG.

24 is a diagram showing a configuration of a 600 Mbps line terminating device in FIG.

25 is a diagram showing the configuration of the ATM-MUX in FIG.

FIG. 26 is a diagram showing a configuration of a multiplexer MX2 in FIG.

27 is a diagram for explaining the operation of the ATM-MUX in FIG. 25.

28 is a diagram showing the configuration of the ATM-DEMUX in FIG.

29 is a diagram showing the configuration of the demultiplexer DX2 in FIG. 28.

FIG. 30 is a routing tag addition unit RT in FIG.
Figure for explaining cell format conversion in A

FIG. 31 is a diagram showing another configuration of the demultiplexer DX2.

FIG. 32: Multiplexer MX2, demultiplexer D
The figure which shows the structure of 2x2ATM switch which can be used as a unit switch which comprises X2 and an ATM switch.

[Explanation of symbols]

11i ... 150 Mbps line (input communication line) 12j ... 600 Mbps line (input communication line) 13k ... 2/4 Gbps line (input communication line) 14i ... 150 Mbps line (output communication line) 15j ... 600 Mbps line (output communication line) 16k ... 2 / 4 Gbps line (output communication path) 101 ... 2.4 Gbps ATM switch (switching means) 102 ... 2.4 Gbps ATM multiplexer (concentrating means) 103 ... 2.4 Gbps ATM demultiplexer (shunt means) 104i ... 150 Mbps line terminating device 105j ... 600 Mbps line terminating device 106k ... 2.4 Gbps line terminating device 112 ... First speed converter 113 ... Second speed converter

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9076-5K H04Q 11/04 B

Claims (2)

[Claims] 1. A plurality of input communication channels and output communication channels having different bit rates are accommodated, and a cell input from each input communication channel is output to a desired output communication channel according to route information added to the cell. In the ATM switching node system, it is possible to switch the cell flow from the input channel with the highest bit rate, the cell flow from the input channel with the highest bit rate is input from the first input port, and the highest bit The cell flow to the rate output communication path is connected to the switching means for outputting from the first output port and the second input port of this switching means,
Concentrating means capable of concentrating the cell flow from the input communication path of the highest bit rate, and the cell flow input to the input communication path other than the input communication path of the highest bit rate provided at the input part of the concentrating means. A first speed converting means for converting a bit rate into a bit rate of an output communication path having a highest bit rate; and a second output port of the switching means,
A shunt means capable of shunting the cell stream having the bit rate of the output communication path having the highest bit rate, and a bit stream of the cell stream shunted from the shunt means provided at the output part of the shunting means. An ATM switching node system comprising: a second speed converting means for converting a bit rate of a desired output communication path excluding the output communication path. 2. A bit transfer clock for receiving a cell stream from a corresponding second speed converting means between the output communication path and the second speed converting means and transmitting the cell flow to the corresponding second speed converting means. 2. The ATM switching node system according to claim 1, further comprising a line terminating device for providing each.