JPH0513561A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent noise interference, between circuit blocks by connecting a power line which supplies power to a plurality of circuit regions divided mutually through an isolation region to different power supply terminals. CONSTITUTION:A trench 5 which forms an isolation region with its bottom in contact with an insulating film 2 is formed on the insulating film 2 which is made of SiO2 formed on a supporting substrate 1. Circuit regions 3, 4 are arranged at both sides with the trench 5 between, and a circuit block is formed at each of the circuits 3, 4. Power is supplied to both circuit blocks through each power line 9 which is connected to each of different power supply terminals 11. Thereby, it is possible to prevent noise interference generated between circuit blocks which are formed in each circuit region through a power line of each circuit region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI semiconductor integrated circuit, and in particular, this SOI semiconductor integrated circuit is suitable as a semiconductor integrated circuit for analog / digital mixed mounting.

In recent years, there has been an increasing demand for analog / digital mixed semiconductor integrated circuits in which analog circuits and digital circuits are formed on the same substrate. In such an analog / digital mixed circuit, it is particularly necessary to prevent noise interference from the digital circuit to the analog circuit.

[0003]

2. Description of the Related Art Conventionally, there has been an example in which noise interference that sneak from a power supply line is prevented by separately dividing both power supply circuits between different types of circuit blocks, for example, between an input / output circuit block and an internal circuit block. In such analog / digital mixed semiconductor integrated circuits, prevention of such noise interference is required between the analog circuit block and the digital circuit block. However, there are the following circumstances in separating the respective power supplies of the plurality of circuit blocks formed on the same substrate from each other.

FIG. 7 is a schematic cross-sectional view of a semiconductor integrated circuit having two circuit regions A and B on which different types of circuit blocks are respectively formed on the same substrate. This integrated circuit is, for example, a CMOS semiconductor integrated circuit, and is shown in FIG.
Shows the case where the substrate is an n-type substrate, and FIG. 9B shows the case where the substrate is a p-type substrate.

In FIG. 1A, an n-type substrate is formed and n
-P-channel transistors in which circuit areas A and B are formed on the substrate 1 forming the area, and the high-potential power supply VDD1 or VDD2 is supplied to both circuit areas A (3) and B (4), respectively. A large number of parts 31, 41 and N-channel transistor parts 32, 42 formed in the p-well and supplied with the low potential power supply VSS1 or VSS2, respectively, are provided in the circuit regions A and B of both of them. The power supply lines and the power supply lines are different from each other. However, one of the power supply lines 9b and 9d for supplying the high potential power supply VDD1 and VDD2 supplies power to the common n − region, respectively, and is electrically connected to each other through the n-type substrate 1. Therefore, they are not completely electrically separated.

In the circuit of FIG. 7A, both circuit blocks have a structure in which they are electrically connected to each other in the power supply lines 9b and 9d for supplying a high-potential power, but in FIG. 7B, the substrate is p-type. It is composed of the substrate 1, and in this case, unlike the case of FIG. 1A, the power supply lines 9a and 9c for supplying the low potential power supplies VSS1 and VSS2 are electrically connected to each other. As described above, the power supplied to different types of circuit blocks formed on the same substrate is electrically connected to the power supply line of one of the power supply lines even if they are separated by the power supply terminals.

Regarding the above-mentioned power supply separation, one of the power supply lines is electrically connected to each other by conduction through the conductive portion on the substrate through a resistance higher than that of the metal wiring. Therefore, the impact was considered to be small and was not a problem.

[0008]

In recent years, in semiconductor integrated circuits, the degree of integration and the speed of operation have dramatically increased, which has resulted in an increase in the current density in the power supply line. Especially in a digital circuit, the power supply line is activated when each element is operated. The noise that occurs in the can no longer be ignored. Therefore, for example, in the analog / digital mixed circuit, even if the power supply systems of both circuit blocks are separated from each other, noise interference via one power supply line that is conducted through the substrate, In particular, there remains a risk of noise interference from the digital circuit to the analog circuit. However, there has been no particular problem with respect to this point in the past, and there has been no known method for simply preventing such noise interference in the structure of the semiconductor integrated circuit, and there has been no solution to this point.

Therefore, the present invention is based on the conventional analog
In view of the problem of noise interference from a digital circuit to an analog circuit in a digital mixed circuit, it is an object of the present invention to provide a semiconductor integrated circuit that can generally prevent noise interference between circuit blocks via a power supply line with a simple structure. And

[0010]

FIG. 1 is an example of a sectional view of a semiconductor integrated circuit according to an embodiment of the present invention. In the figure, 1 is a support substrate, 2 is an insulating film, 3 and 4 are circuit regions on the element substrate, respectively, 5 is a trench forming an isolation region, 9 is a power supply line, and 11 is a power supply pad. Note that 1 and 2 form an insulating substrate.

In order to achieve the above object, the semiconductor integrated circuit of the present invention, as shown in FIG. 1, has an isolation region (5) formed on an insulating substrate in contact with the bottom of the insulating substrate, and A plurality of circuit areas (3, 4) formed on an insulating substrate and partitioned from each other through the separation area, and a power supply line (9) for supplying power to each of the circuit areas (3, 4)
Is provided for each of the circuit regions (3, 4) by being connected to mutually different power supply terminals (11).

As a semiconductor integrated circuit of the present invention, an insulating film 2 is formed on a supporting substrate 1 made of a conductive material as illustrated in FIG.
In addition to the SOI semiconductor integrated circuit in which the circuit region is formed on the insulating substrate formed with, the SOI semiconductor integrated circuit in which the circuit region is formed on the insulating substrate made of an insulating material is also included.
The conductivity type of the circuit region forming the element substrate formed on the insulating (supporting) substrate can be either p-type or n-type.

Further, the isolation region may be configured as a partition well other than the trench shown in FIG.

[0014]

The isolation regions of the SOI semiconductor integrated circuit, whose bottoms are in contact with each other, isolate the circuit regions from each other, and the power supply lines for supplying power to these circuit regions are respectively connected to different power supply terminals. With this configuration, it is possible to prevent noise interference that occurs between the circuit blocks formed in each circuit area via the power supply line of each circuit area.

Conventionally, it has been known that the SOI semiconductor integrated circuit has characteristics such as low parasitic capacitance, high insulation resistance, and low power consumption. However, the SOI semiconductor integrated circuit should be constructed as in the present invention. Then, the insulating substrate of the SOI semiconductor substrate circuit is used as a part of the insulation between the circuit regions, and the power supply lines are separated from each other by a simple structure in which the bottom of the well or trench is formed so as to be in contact with the insulating substrate. Nothing was known about the separation structure.

[0016]

The present invention will be described in more detail with reference to the drawings. In the cross-sectional view of the semiconductor integrated circuit of the first embodiment of the present invention shown in FIG. 1, in the SOI semiconductor integrated circuit of this embodiment, on the insulating film 2 made of SiO ₂ formed on the support substrate 1, A trench 5 is formed in contact with the bottom of the insulating film 2 to form a separation region, and an insulating film is formed on the surface of the trench 5 inside.

Circuit regions 3 and 4 are arranged on both sides of the trench 5 with the trench 5 sandwiched therebetween, and circuit blocks are formed in both circuit regions 3 and 4, respectively. Both circuit blocks have
Power is supplied through the respective power supply lines 9 that are respectively connected to different power supply terminals 11.

FIG. 2 is a schematic sectional view of the semiconductor integrated circuit of the second embodiment. In the figure, the isolation region is different from the trench 5 of FIG. 1 and is configured as a partition well 5a of one conductivity type. The partition well 5a has a conductivity type different from that of each of the circuit regions 3 and 4. There is. Other configurations are the same as those in FIG.

FIG. 3 is a sectional view showing in detail the structure of the semiconductor integrated circuit of the first embodiment shown in FIG. In the figure, a SiO ₂ oxide film 2 is formed on a silicon substrate 1 which is a support substrate through thermal oxidation, and an n-type element substrate is formed on the SiO ₂ oxide film 2 by a method such as recrystallization of polysilicon (polycrystalline Si). N-circuit regions 3 and 4 are formed. A deep and narrow trench 5 is formed between both n-circuit regions 3 and 4 through RIE (reactive ion etching), and an oxide film made of SiO ₂ is formed inside the trench 5. In this case, it is also possible to adopt a configuration in which an SiO ₂ insulating film is formed only on the groove surface, polycrystalline Si is filled from the SiO ₂ insulating film, and then planarized by an etch back method. Both n − circuit regions 3 and 4 are insulated from each other by this trench and a circuit block is formed inside each.

The n-circuit area 3 constitutes a circuit area A in which an analog circuit block is formed, and a large number of p-wells 6, one of which is illustrated in the drawing, are further provided. One or more NMOS transistors are formed in each via ion implantation or the like. Also, this NMOS
A p + diffusion region 7 forming a guard ring is formed in the p-well 6 of the transistor portion, and the p + diffusion region 7 is connected to the first low potential power supply line 9a made of a metal electrode (Al) to form a p + diffusion region 7. It is connected to one low potential power supply VSS1 (not shown). In addition, a large number of PMOSs are ion-implanted into the other part of the n-circuit region 3 adjacent to the p-well 6.
A transistor is formed, and the n + region 8 forming the guard ring of the PMOS transistor portion is connected to the first high potential power supply VDD through the first high potential power supply line 9b made of Al material.
Connected to 1.

The n-circuit region 4 constitutes a circuit region B in which a digital circuit block is formed, and like the n-circuit region 3, a large number of NMOS and PMOS transistors are formed respectively. The digital circuit block is connected to the second high-potential and low-potential power supplies VDD2 and VSS2 via the second high-potential and low-potential power lines 9d and 9c, respectively.

Power supply lines 9a of both circuit blocks,
One end of 9b, 9c and 9d is phospho-silicate glass
The corresponding diffusion region portions 7 in the contact holes forming the peeled portions of the cover film 10 formed of (PSG),
8 and a contact is formed, and the other end is connected to the power supply pad and connected to the external terminal.

FIG. 4 is a schematic plan view of the semiconductor integrated circuit of the first embodiment. In the figure, in this semiconductor integrated circuit chip, the entire analog circuit region 3 in which the analog circuit block is formed is surrounded by a trench 5 whose bottom is in contact with the SiO ₂ insulating film of the SOI substrate. The high-potential and low-potential power lines 9b and 9a forming the first power line for supplying power to this analog circuit block are on the PSG formed above the digital circuit region 4 in which the digital circuit block is formed. And are connected to the pad portions 11b and 11a respectively arranged near the chip sides facing each other. Similarly, a second power supply line 9 for supplying power to the digital circuit block
c and 9d are also connected to the corresponding pad portions 11c and 11d, respectively.

FIG. 5 is a block diagram showing the power supply configuration of the semiconductor integrated circuit of the first embodiment. As shown in the figure, in the semiconductor integrated circuit of this embodiment, the analog circuit is supplied with power from the first power supply lines 9a and 9b, and the digital circuit is supplied with power from the second power supply lines 9c and 9d. And both power supply lines 9a, 9b; 9c,
9d is a pair of pad portions 11a, 11b; 11c, 1
It is configured to be connected to different power supply devices (not shown) via 1d.

As described above, the first and second power supply lines 9
a, 9b; 9c, 9d are respectively connected to the circuit regions 3, 4
By separating each other through the trench, noise generated in a digital circuit due to, for example, a through current flowing through the CMOS transistor when the CMOS transistor is operating, enters the analog circuit through the power supply line and causes noise interference. Is prevented. In this case, the wirings interposed between the digital circuit and the analog circuit are only the signal lines 13 and 14, and the noise generated in the signal lines 13 and 14 is the power supply lines 9a, 9b and 9
Since it is extremely small compared to the noise generated in c and 9d,
Noise interference from a digital circuit to an analog circuit, which may occur in a conventional semiconductor integrated circuit, is reduced.

In the above embodiment, the example of forming the SiO ₂ insulating film in the trench 5 forming the isolation region is described, but it is not always necessary to dispose SiO ₂ in the trench.

FIG. 6 is a sectional view showing in detail the structure of the semiconductor integrated circuit of the second embodiment shown in FIG. In the case of the figure, in place of the trench 5 having the SiO ₂ insulation therein in the previous embodiment, a division well 5a forming a dummy p-well region is formed by ion implantation, and analog and analog wells are formed through this division well 5a. By separating the digital circuit areas 3 and 4 from each other, both power supply lines 9a and 9b are separated.
And 9c and 9d are separated. In the case of this semiconductor integrated circuit, a plurality of analog circuit areas 3 and a plurality of digital circuit areas 4 are provided respectively, and the power supply lines of the analog circuit areas 3 and the power supply lines of the digital circuit areas 4 are respectively provided with common power supply pads 11a to 11a. It is connected to 11d.

The partition well 5a is connected to the GN via the power source line 9e and the pad 11e connected to the power source line 9e.
It is connected to D (ground). The pad 11e is used for each of the power supply lines 9a of the digital and analog circuit areas 3 and 4.
It is provided separately from the power supply pads 11a to 11d to which 9d is connected. In this way, the compartment well 5a is
By maintaining the ND potential, the GND potential is extremely stable, so that noise interference that occurs between the two circuit regions is extremely effectively prevented.

In addition to the above power supply configuration, the partition well 5a
Power supply line 9e of the digital circuit area power supply line 9c
It can be connected to the common pad 11c with (VSS2). In the case of this configuration, the noise reduction effect is slightly inferior to the case where the pad of the partition well 5a is separately provided. That is, the noise generated in the power supply line 9e is transmitted to the digital side via the power supply line. However, since the digital circuit is less susceptible to the influence of noise, the influence is small, and the noise transmitted to the analog circuit can be prevented, so that the object of the present invention can be substantially achieved.

Contrary to FIG. 6, when the element substrate of each of the circuit regions 3 and 4 is formed as a p-type substrate and therefore the partition well 5a is formed as an n-well, the power supply line 9e is independent. Is connected to a high-potential power supply separated from the power supplies of both circuit areas via the pad 11e of the above, or is commonly connected to the high-potential power supply line 9d of the digital circuit area at the power supply pad 11d. In this case, the noise reduction effect is slightly inferior to the example connected to the GND.

The partition well 5a does not necessarily need to be connected to the power supply line itself regardless of whether it is formed as a p-well or n-well conductive type well. By preventing the floating of and keeping it at a predetermined potential,
It is possible to prevent capacitive coupling between the partition well 5a and both circuit regions 3 and 4, and effectively prevent noise interference between circuit blocks via the capacitive coupling.

The constitutions and materials of the respective portions such as the substrate material, the insulating film, the well, the trenches and the like described in the respective embodiments can be replaced by well-known constitutions and materials, respectively. Substitutions from the examples are also included in the scope of the present invention.

[0033]

As described above, according to the semiconductor integrated circuit of the present invention, noise interference occurring between circuit blocks can be prevented with an extremely simple structure, and the semiconductor integrated circuit is embodied in a digital / analog mixed semiconductor integrated circuit. If
By preventing noise interference, the signal accuracy of the analog circuit can be improved, which is a remarkable effect.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor integrated circuit of an embodiment for explaining the principle of the present invention, which is an example in which an isolation region is formed as a trench.

FIG. 2 is a schematic sectional view of a semiconductor integrated circuit according to a second embodiment of the present invention.

3 is a structural cross-sectional view of the semiconductor integrated circuit of FIG.

FIG. 4 is a plan view of the semiconductor integrated circuit of FIG.

5 is a block diagram showing a power supply configuration of the semiconductor integrated circuit of the embodiment of FIG.

6 is a structural cross-sectional view of the semiconductor integrated circuit of FIG.

FIG. 7 is a schematic cross-sectional view of a conventional semiconductor integrated circuit,
(A) shows an n-type substrate, and (b) shows a p-type substrate.

[Explanation of symbols]

1: Support substrate 2: Insulating film (insulator) 3,4: Circuit area 5: Isolation region (trench) 5a: division well 6: Well 9: Power line 11: Power supply terminal (pad)

Claims (6)

[Claims] 1. An isolation region (5) formed on an insulating substrate in contact with the bottom of the insulating substrate, and an isolation region (5) formed on the insulating substrate and partitioned from each other through the isolation region (5). And a plurality of circuit areas (3, 4)
A semiconductor integrated circuit characterized in that a power supply line (9) for supplying power to 4) is connected to mutually different power supply terminals (11) and provided for each of the circuit regions (3, 4). 2. The isolation region is configured as a trench having an insulating film formed on the surface thereof.
The semiconductor integrated circuit described. 3. The isolation region is formed as a partition well (5a) of one conductivity type, and each of the circuit regions (3, 4) is formed in a conductivity type opposite to the one conductivity type. The semiconductor integrated circuit according to claim 1. 4. The circuit area (3, 4) includes an analog circuit area (3) having an analog circuit formed therein and a digital circuit area (4) having a digital circuit formed therein. Item 3. The semiconductor integrated circuit according to items 1 to 3. 5. The partition well (5a) is arranged independently of the power supply terminals (11a-11d) to which the power supply lines (9a-9d) of both circuit regions (3, 4) are connected. 4. The semiconductor integrated circuit according to claim 3, wherein the semiconductor integrated circuit is connected to a terminal (11e) to be connected. 6. The circuit region (3, 4) includes an analog circuit region (3) in which an analog circuit is formed and a digital circuit region (4) in which a digital circuit is formed, and in the partition well (5a). 4. The semiconductor integrated circuit according to claim 3, wherein the connected power supply line (9e) is commonly connected to one of the power supply lines (9c, 9d) of the digital circuit area (4).