JPH05135595A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To optimize an erase time by monitoring the drain currents of storage blocks and by controlling the applying time of erase voltages to each of the storage block based on the monitored results. CONSTITUTION:Erase voltage applying means A1-Am, erase condition discrimination means B1-Bm and inhibiting means C1-Cm are provided for each of storage blocks D1-Dm which contain plural nonvolatile storage devices. And a prescribed potential of an erase voltage is applied to the source electrodes of nonvloatile storage devices, which have floating gates FGs, by the means A1-Am. When the drain currents ID of the nonvolatile storage devices become more than a prescribed current, the means B1-Bm judge the devices to become completely erased conditions and inhibit the voltage applying operations of the means A1-Am by the means C1-Cm. Having this arrangement, erase time of each block of the storage space which is divided into plural blocks is optimized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device using a FLOTOX (floating gate tunnel oxide) type or MNOS (metal nitride oxide semiconductor) type memory element. Regarding Generally, a magnetic disk is often used as an external storage device such as a CPU. However, since the magnetic disk mechanically seeks a head to read and write data, there is a limit to improvement of the reading and writing speed. Therefore, there is a demand for a non-volatile semiconductor memory device that can read and write purely electrically and that can hold data for a long period of time without power backup.

[0002]

2. Description of the Related Art FIG. 4 is a structural diagram of a storage element of a stack gate type flash memory suitable for use in such a non-volatile semiconductor memory device, and 1 is a semiconductor substrate of one conductivity type (for example, p conductivity type), 2 is a tunnel oxide film, 3 is a floating gate (hereinafter also referred to as FG), 4 is an insulating film, 5
Is a control gate, 6 is a source region of another conductivity type (for example, n conductivity type), 7 is a drain region of another conductivity type, and the control gate electrode C from the control gate 5, the source region 6 and the drain region 7, respectively.
G, the source electrode S, and the drain electrode D are drawn out.

In the memory element having such a structure, the threshold voltage Vth can be changed by injecting or extracting electrons into the floating gate 3. When, for example, 0V is applied to the substrates 1 and S, + 12V is applied to CG, and + 6V is applied to D, so-called avalanche breakdown (electron avalanche breakdown) occurs, and high-energy electrons and positive electrons are generated near the drain region 7. A large number of holes are generated, and some of the electrons pass through the tunnel oxide film 2 and are injected into the floating gate 3. As a result, the floating gate 3 is charged with a negative charge (for example, -2V), S is 0V and CG is +5.
Even if +1 V is applied to V and D, the drain and the source are not conducted and the drain current ID does not flow. Hereinafter, this state is referred to as a logic 0 holding state for convenience.

On the other hand, when 0 V and D are opened to the substrate 1 and CG and +12 V is applied to S, a so-called tunnel phenomenon occurs, and electrons of the floating gate 3 are extracted to the source region 6. If the amount of electrons extracted is optimized, the electric charge of the floating gate 3 becomes almost zero, and S is 0 V.
When 5 V is applied to CG and 1 V is applied to D, the drain and the source are electrically connected and the drain current ID flows. Hereinafter, this state is referred to as a logic 1 holding state for convenience.

Generally, setting the storage content to logical 0 is called data writing, and setting the storage content to logical 1 is called erasing data. FIG. 5 is a conceptual diagram of a memory cell array using the above-described memory element, which is an example of a cell array having a matrix arrangement of n columns × 2 rows. T _{1,1 to} T _{n, 1} and T
_{1, 2 to} T _{n, 2} are nonvolatile storage elements (hereinafter, storage elements), and control gates C of the storage elements for each row
G is connected in common to word lines WL ₁ and WL ₂ , and
The drain electrodes D of the storage elements in each column are commonly connected to the bit lines BL _{1 to} BL _n, and the source electrodes S of all the storage elements in the array are commonly connected to the source line SL.

That is, if the cell array is A columns × B rows, it is equipped with A bit lines and B word lines, and
It has one source line regardless of the matrix. 2 in FIG.
FIG. 3 is a configuration diagram of a memory cell array M of columns × 2 rows and its peripheral circuits. The peripheral circuit includes a write circuit 100, a read circuit 200, and an erase circuit 300. Since these have the same configurations as those of the embodiments described later, a detailed description thereof will be given in the embodiments. Here, input / output will be described. Only decided to do.

When the write enable signal WE is logic 1 and the write data WDT is logic 0, the write circuit 100 generates a write voltage of + 12V. This write voltage (+ 12V) is selected as the bit line selection. By applying to the drain electrode D of the memory element in the first column (or second column) of the memory cell array M via the selection transistor T _SEL1 (or T _SEL2 ) turned on by the signal S _BL1 (or S _BL2 ). , Word line selection signal S
Electrons are injected into the floating gate of one storage element selected by _WL1 (or _SWL2 ).

The read circuit 200 uses the erase command signal ER.
When S is logic 0, the drain current ID of the storage element is monitored through the selection transistor T _SEL1 (or T _SEL2 ) and outputs read data RDT which becomes logic 1 if ID flows and logic 0 if ID does not flow. To do. The erase circuit 300 has a read / write enable signal R / W.
When E is logic 1, a voltage of 0V is generated, while when an external erase command signal ERS is logic 1, a voltage of + 12V (hereinafter, erase voltage) is generated. These voltages are used for the memory cell array M. Source electrodes D of all memory elements
Is applied to the write or read mode when 0V, and the erase mode when + 12V.

In the conventional non-volatile semiconductor memory device, an erase voltage (+ 12V) is generated in response to an erase command signal ERS from the outside, and this voltage is applied to the source electrode of the memory element. Therefore, if the erase command signal ERS is too short, for example, the extraction of electrons from the floating gate is insufficient (relative to the injection amount), resulting in incomplete erase. There is a problem that it is over-erased by being pulled out to more than the injection amount).

In particular, in the case of excessive erasing, the floating gate is positively charged and the threshold voltage Vth moves to the negative voltage side, so that a drain current ID of a certain value or more flows regardless of the control gate voltage. Therefore, even if an attempt is made to read out a cell of logic 0, there is a disadvantage that the cell cannot be read out normally. As a countermeasure against this, for example, an erasing operation and a reading operation are alternately repeated at minute intervals until all the memory elements that are in a conductive state (logic 0) by writing are brought into a conductive state (logic 1). Type semiconductor memory device is known.

[0011]

However, in the conventional non-volatile semiconductor memory device adopting such a measure, the erase voltage is applied to all the memory elements until all the memory elements become conductive. Therefore, there is a problem in that it is inevitable to excessively erase the storage element that has reached the conduction state immediately.

Therefore, an object of the present invention is to optimize the erase time for each block of a storage space divided into a plurality of blocks.

[0013]

In order to achieve the above-mentioned object, the present invention provides a predetermined erase command signal to a source electrode S of a nonvolatile memory element having a floating gate FG as shown in the principle diagram of FIG. and erase voltage application means _{a 1, a 2, ......,} a m giving erase voltage of a predetermined potential in response to,
Erase state determining means B ₁ , B ₂ , ..., B _m for determining when the drain current ID of the non-volatile memory element exceeds a predetermined current as a complete erase state, and the erase state determining means for the complete erase state. When it is determined that the prohibition means C ₁ for prohibiting the voltage application operation by the erase voltage application means,
It is characterized in that C ₂ , ..., C _m are provided for each of the memory blocks D ₁ , D ₂ , ..., D _m including a plurality of nonvolatile memory elements.

[0014]

In the present invention, each memory block D ₁ ,
The drain current ID of D ₂ , ..., D _m is monitored, and the application time of the erase voltage applied to each memory block is controlled by the result. Therefore, for example, if the ID flows in one storage block as soon as possible, application of the erase voltage to the storage block is prohibited, and excessive erasure is avoided.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. 2 and 3 are views showing an embodiment of the nonvolatile semiconductor memory device according to the present invention. In FIG. 2, M is a memory cell array (memory block D described in the gist of the present invention).
_{1 to} D _m ), 100 is a writing circuit, 200
Is a read circuit (corresponding to one of the erased state determination means B _{1 to} B _m described in the gist of the invention), and 300 is an erased circuit ( ₁ of the erase voltage application means A _{1 to} A _m described in the gist of the invention). Equivalent to one). These circuit configurations are almost the same as those in FIG.

That is, the memory cell M is composed of four nonvolatile semiconductor memory elements (hereinafter, memory elements) T _1,1 , T _2,1 , T _1,2 and T arranged in a matrix of 2 columns × 2 rows. comprising a _2,2, the storage elements of each row (T _{1, 1} and T _2,1, T _{1, 2} and T _2,2)
Control gates CG are commonly connected to word lines WL ₁ and WL ₂ , respectively, and drain electrodes D of storage elements (T _1,1 and T _1,2 , T _2,1 and T _2,2 ) for each column are connected. Are commonly connected to the bit lines BL ₁ and BL ₂ , respectively, and the source electrodes S of all storage elements are commonly connected to the source line SL.

The write circuit 100 has write data W.
An inverter gate 101 that inverts the logic of DT, an AND gate 102 that ANDs the output of the inverter gate 101 and the write enable signal WE, and a transistor 103 that is conductive when the output of the AND gate 102 is logic 1. When the transistor 103 is turned on, a writing voltage of a predetermined potential (for example, + 12V) is generated.

The read circuit 200 has an inverter gate 201 which inverts the logic of an erase command signal ERS from the outside.
And a transistor 202 which is conductive when the output of the inverter gate 201 (inversion erasing instruction signal ERSX) is in the logic 1 period (hereinafter, read period), and a diode-connected transistor interposed between the transistor 202 and the power supply V _CC. A selection transistor T _{SE L1} provided with 203 and an inverter gate 204 that inverts the intersection potential of both transistors 202 and 203 and outputs it as read data RDT, and is made conductive selectively by the bit line selection signal S _BL1 (or S _BL2 ). (Or T _SEL2 ), the drain current ID of the memory element is monitored, and if ID does not flow (if data is written), RDT is set to logic 0,
If it flows (if the data has been erased), RDT is set to logic 1.
And

The erase circuit 300 includes a transistor 301 which conducts when the read / write enable signal R / WE is logic 1, and an erase operation prohibition / permission signal ERI which will be described later.
A transistor 302 that is conductive when / E is a logic 1, and when the transistor 301 is conductive, an erase voltage of 0 V and a predetermined potential (for example, +12 V) when the transistor 302 is conductive is applied to the source of all the storage elements via the source line SL. Apply to the electrode S.

Here, 400 is a flip-flop and 50
Reference numeral 0 is a set signal generation circuit, 600 is a reset signal generation circuit, and 700 is an AND gate which outputs an erase operation prohibition / permission signal ERI / E, and these are integrated as a prohibition means C ₁ described in the gist of the present invention. corresponds to one of -C _m. The flip-flop 400 includes four transistors 401 to 404 connected in a cross and two sets / transistors.
This is a well-known flip-flop including reset transistors 405 and 406. When the set transistor 405 conducts, it enters a set state in which a logic 0 is output, and when the reset transistor 406 conducts, it enters a reset state in which a logic 1 is output.

The set signal generation circuit 500 includes an inverter gate 501 which inverts the inversion erase command signal ERSX,
Integrator circuit 50 that integrates the output of the inverter gate 501
2 and AND gate 5 which takes the logic of ERSX and integral output
3, and outputs a set pulse signal having a signal width Wd determined by the time constant of the integrating circuit from the start time t ₀ of the logic 1 period (reading period) of ERSX, as shown in FIG.

The reset signal generating circuit 600 has an inverter gate 601 for inverting the read data RDT, an output of the inverter gate 601 and an inversion erasing command signal ERS.
Equipped with an AND gate 602 which takes an AND logic of X,
When the logic of RDT becomes 0 during the logic 1 period (reading period) of RSX, the reset signal which rises to logic 1 is output.

Here, the memory cell array M constitutes one memory block. The feature of this embodiment is that at least the read circuit 20 is provided for one storage block.
0, erase circuit 300, flip-flop 400, set signal generation circuit 500, and reset signal generation circuit 600 are provided exclusively. That is, if there are a plurality of storage blocks, the number of read circuits 20 corresponding to the number of the blocks.
0, an erase circuit 300, a flip-flop 400, a set signal generation circuit 500, and a reset signal generation circuit 600 are provided.

Next, the operation will be described. If the write enable signal WE is logic 1 and the write data WDT is logic 0, the write circuit 100 outputs a write voltage of + 12V. This write voltage is applied to the two storage elements T _1,1 and T _1,2 via, for example, T _SEL1 which is made conductive by the bit line selection signal S _BL1 (or S _BL2 ).
Given to the drain of. Now, the word line selection signal _SWL1
If the word line WL ₁ is activated with the potential of
Number of the storage elements T _{1, 1} and T _{1, 2,} 1 pieces of the storage elements connected to WL ₁ T _{1, 1} is selected, the voltage (R / WE from cancellation circuit 300 to the source electrode S Since it is active, 0V) is applied.

Therefore, 0 V is applied to the source electrode S of the selective storage element T _1,1 and the activation potential of the word line is applied to CG (for example, +
12V), + 6V, for example, are applied to D, so-called avalanche breakdown (electron avalanche breakdown) occurs, a large amount of high-energy electrons and holes are generated in the vicinity of the drain region 7, and some of these electrons are It is injected into the floating gate FG through the tunnel oxide film. As a result, the floating gate FG has a negative charge (for example, −).
2V) is charged and data is written.

When the erase command signal ERS is externally applied after writing the above data, during the period of the logic 1,
The transistor 302 of the erase circuit 300 is turned on, and +12 V is applied to the source electrodes S of all the memory elements of the memory cell array M, in other words, all the memory elements of one memory block.
Erase voltage is applied. When the ERS shifts to the logic 0 period, the inverted signal ERSX of the ERS shifts to the logic 1 period. ERSX logic 1 period (readout period)
Then, the transistor 202 of the read circuit 200 is turned on to monitor the drain current ID, and if the ID does not flow (if the erasing is incomplete), the read data RDT of logic 0 is output, or if the ID flows. Read data RDT of logic 1 is output (if erase is complete).

On the other hand, in the logic 1 period of ERSX,
Since the set pulse signal is output from the set signal generation circuit 500 at the beginning of the period, the flip-flop 400
Are set to a set state (logic 0 is output), but if the RDT is logic 0 (erasure insufficient) at this time, the reset signal becomes logic 1, and the flip-flop 400 is immediately reset (logic 1 is output). The output of the AND gate 700 becomes logic 1 and the erase operation is continued. On the contrary, if the RDT is logic 1 (complete erase), the reset signal becomes logic 0 and the flip-flop 400 is not reset, so the output of the AND gate 700 becomes logic 0 and the erase operation is stopped (inhibited).
To be done.

That is, when a certain amount of time has passed and sufficient electrons have been extracted from the floating gate FG, the drain current ID begins to flow, the RDT changes to logic 1, the reset signal changes to logic 0, and the flip-flop 400 is turned on.
The set state of (outputting logic 0) is continued, and the erasing circuit 3
As a result of the transistor 00 of No. 00 changing to the non-conducting state, the application of the erase voltage is stopped (in other words, prohibited).

Therefore, according to this embodiment, the erase operation for each memory block (memory cell array M) is monitored, and when a sufficient amount of electrons are extracted, the application of the erase voltage to the memory block is stopped ( Therefore, it is possible to obtain a peculiar effect that it is possible to avoid excessive erasing of a memory block whose erasing is completed promptly. In addition,
Storage block is one storage device (memory chip)
May be divided into a plurality of blocks, or a physical storage space composed of several memory chips may be divided into a plurality of blocks.

Further, the smaller the scale of each memory block is, the more preferable it is in terms of prevention of excessive erasure, and it is desirable that one memory block is configured with as few memory elements as possible, as long as the design cost allows.

[0031]

According to the present invention, since the erase voltage applying means, the erase state determining means, and the inhibiting means are provided for each memory block including a plurality of nonvolatile memory elements, a storage space divided into a plurality of blocks is provided. It is possible to optimize the erase time for each block.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 is a waveform diagram of a set signal generation circuit according to an embodiment.

FIG. 4 is a structural diagram of a storage element of a stack gate type flash memory.

5 is a conceptual diagram of a memory cell array using the memory device of FIG.

FIG. 6 is a configuration diagram of a conventional example.

[Explanation of symbols]

FG: Floating Gate S: source electrode ID: a drain current A ₁ to A _m: erasing voltage applying means B ₁ ~B _m: erase state determination means C ₁ -C _m: inhibiting means D ₁ to D _m: storage block

Claims (1)

[Claims] 1. Erase voltage applying means (A ₁ , A _{2) for} applying an erase voltage of a predetermined potential to a source electrode (S) of a nonvolatile memory element having a floating gate (FG) in response to a predetermined erase command signal. , ..., A _m ) and erase state determination means (B ₁ , B ₂ , ..., B) for determining the complete erase state when the drain current (ID) of the nonvolatile memory element exceeds a predetermined current. _m ) and prohibiting means (C ₁ , C ₂ , ..., C _m ) for prohibiting the voltage application operation by the erase voltage applying means when the complete erase state is determined by the erase state determining means. Storage block (D ₁ ,
A non-volatile semiconductor memory device characterized by being provided for each D ₂ , ... D _m ).