JPH05135588A - High-speed address comparing circuit for memory having redundant address specifying constituent member - Google Patents

Abstract

PURPOSE: To simplify circuit constitution by providing two elements for respective bit positions and performing constitution by two serially connected FETs inside the respective elements. CONSTITUTION: Representative elements T10 and T11 are constituted of the two FETs for receiving an address bit A0 and a complement address bit F0B, the other representative elements T12 and T13 are constituted of the FETs for receiving the complement address bit A0B and the address bit F0 and input is inputted to the gate of the FET. When all the address bits A0-A9 match, all the FETs are turned OFF, nodes N1 and N2 are separated, the capacitance of the node N1 is connected to a Vcc by a latch circuit 12, the node N2 is grounded by the latch circuit 14 and a high level is outputted. When a non- matching address bit is present, one of the elements is conducted, the two nodes are turned to the same level and a low level is outputted through an inverter 16. Thus, this comparator circuit 15 simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address circuit for a static memory of a data processor, and more particularly, the present invention compares an address supplied to the memory with a permanent address to address an alternate memory word line. Circuit for producing a match signal for

[0002]

BACKGROUND OF THE INVENTION It is useful to revisit the example of a memory that uses address matching circuits to select redundant word lines. The memory has binary storage cells located at the intersections of the matrix of word lines and bit lines. The cells along the word line form the bit positions of the memory word. When a select voltage is applied to a particular word line, each cell along that line is made available for read or write operations. Consider, for example, a simple memory with only 16 words. Each of these 16 lines is 1
It is identified by one of the six addresses, 0000-1111 in binary and 0-15 in decimal. The address decoding circuit receives 4 address bits and outputs 1
Generate the select signal on the corresponding one of the six word lines.

Some memories have a second, redundant, set of word lines. If one of the normal word lines is found to be defective, a redundant line is used at that location. (Usually this test for defective word lines is only done during manufacturing.) Generally,
The address of the incomplete line is placed in permanent storage and at each memory access this address is compared to the address supplied to memory (this is simply called the "memory address"). In the example of a memory with 16 word lines, the permanent address also has 4 bits, which form a register for the permanent address of the incomplete word line. Permanent storage is generally in the form of a fusible link that can be selectively opened when the word line test is initiated. The address comparison circuit receives the address in the permanent memory and the memory address and compares the two bits at each bit position. If a match is found at each bit position, the comparison circuit issues a signal indicating that the corresponding redundant word line is selected instead of the incomplete line.

Bit compare circuits are well known, but it is useful to present an example that will be used later. Address bits applied to the address decoder are indicated by the letter "A" with a number for the bit position, and the bit for permanent storage is also the letter (of fuse) ".
It is indicated by F ″. For bit position 0, the element of the comparison circuit is the logical sum (A0 * F0) + (A0B
* F0B), that is, A0 and F0 are both up or both down. Note that the symbol B in the suffix indicates the complement.

One of two logical products (for example, A0 * F0)
Is two Fs connected in series between the output of the bit comparison circuit and the potential point representing binary 1 (positive in the example of this specification).
Realized by ET. When both FETs in one element conduct, the potential point pulls up the output line to indicate a logic one. A simple comparator circuit has two of these series circuits, one for each product in the logic function. One of these circuits is called the "comparator circuit element" or simply the "element".

Generally, such a comparison circuit has four F
ET is further included, and the complementary comparison function (A0 * F0B) + (A
0B * F0) operation is realized, and these FETs pull down the output line when a mismatch indicating a logic 0 occurs.

The outputs of all match circuits are combined into a logical function to detect when a match occurs at each bit position. The complement of this bit matching function is called the exclusive OR function. Since many logic gates in a combinational circuit have a complement function, the address comparison circuit can be implemented at the logic gate level with an exclusive OR circuit or a non-exclusive OR circuit.

An embodiment of a conventional address comparison circuit is a non-exclusive OR circuit for each bit position, an AND inversion circuit for each set of non-exclusive OR circuits, and an OR which receives all outputs of the AND inversion circuit as inputs. An inverting circuit.
These consecutive logic stages slow down the operation of the circuit and multi-bit addresses require additional stages.

As has been described, the memory has a permanent memory for one address and can be substituted for only one defective line. Memory
It will be appreciated that in order to operate the memory with more defects, circuits associated with registers and several permanent addresses are provided.

Although the memory address circuit of this example is considerably simplified, in general the memory address circuit is complex and the memory has several levels of selection, each of which has a bit of bits in the entire address register. Respond to a specific set. From a more general point of view, address bits in permanent storage are associated with addressing levels that have redundancy. When the addresses in the permanent memory match, the memory access circuit operates using the corresponding redundant component.

[0011]

SUMMARY OF THE INVENTION A simple bit comparison circuit includes four FETs, and conventional comparison circuits typically also include four FETs. One object of the present invention is to eliminate the need for both these pairs of circuit elements.

Conventional address comparison circuits have consecutive logic stages which slow down the circuit and multi-bit addresses require additional stages. One object of the present invention is to
The aim is to provide a comparison circuit which requires only a small number of stages, the number of stages being less dependent on the width of the address.

The bit position comparison circuit used in the present invention has two elements for each position and two FETs connected in series within each element.
Both true and complement values of the address bits are provided and the FETs of each element are connected to two registers and both conduct when a mismatch occurs. All of the elements of the address comparison circuit are connected so that the two nodes are conductive.

A circuit with two latches charges and discharges the capacitance of two nodes. When a "match" occurs (no element is conducting), one node is discharged to approximately ground level and the other node is charged to near the potential of the power supply terminal. During the "mismatch", at least one element is conducting, causing the two nodes to be at approximately the same potential. (The potentials differ by the conduction voltage drop of the FET in one element.) The components in the two latches form a voltage divider, which gives the two nodes the potential of about half of the power terminals, whose value is It is easily distinguished from the voltage to indicate a match.

The output stage responds to the voltage difference between the two nodes and produces a signal which activates the redundant word line select circuit when a match is found.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows an address comparison circuit 11 in which representative elements are arranged in a column between two lines N1 and N2. The upper set of components in the figure is the upper latch circuit 1.
2 and the lower set of components in the figure is called the lower latch circuit 14. The input to the address comparison circuit is
Memory address bits A0 through A9, corresponding permanent address bits F0 through F9, and their complements indicated by suffix B. These inputs are FE in the comparison circuit.
It is connected to input to the gate of T.

Line 15 carries the output and is formed by the output circuit 16 shown to the right of lines N1 and N2.
The circuit has a power supply terminal represented by Vcc and circuit ground. In the preferred circuit, Vcc is positive and it is convenient to use this polarity in the discussion because it corresponds to the up and down signal levels shown above.

The semiconductor chip that realizes this circuit is usually F
Although there are conducting wires N1 and N2 extending on both sides of the array of ETs, the wires N1 and N2 and the comparison element being shown in the figure, more generally the wires N1 and N2 are simply nodes. ,
The components connected to these lines receive the same potential.

A typical bit comparison circuit for bit positions A0 and F0 has four FETs T10 through T13. FETs T10 and T11 are address bits A0 and F
Corresponding to 0B, when A0 is up and F0 is down,
Both FETs T10 and T11 conduct between nodes N1 and N2. (As will be explained later, the line with respect to node N2, ie node N1 is always positive.) Similarly, F
ET T12 and T13 receive address bits A0B and F0 and both are conductive when bit A0 is down and bit F0 is up. Therefore, if bits A0 and F0 do not match, one of the two elements will conduct between nodes N1 and N2.

The elements at the other bit positions similarly receive the address bits and are connected so as to conduct between the nodes N1 and N2. If a mismatch occurs at any bit position, the element at that position in circuit 11 becomes conductive. Conduction of either element brings the nodes N1 and N2 to substantially the same potential. Since there is a threshold voltage across the conducting elements, a low voltage between nodes N1 and N2 will result if there is a mismatch at any bit position.
A high voltage is produced if there is a match at each bit position.

Since the circuit using redundant word lines instead of defective word lines responds only to the match condition at output 15, the mismatch condition also affects the bit compare circuit of FIG. 1 and the circuit connected to its output. On the other hand, make a standby state.

The output circuit 16 includes two FETs T8 and T9.
, Which are connected as a conventional CMOS inverter stage. (The shaded area in the figure is the p-channel FE
T represents a non-hatched n-channel FET. ) The source terminal of the p-channel FET T8 is connected to the node N1 and the gate terminal is connected to the node N2. When a mismatch occurs and nodes N1 and N2 have approximately the same potential, the gate of FET T8 is made slightly more negative than its source and FET T8 is turned off. FE
The potential of the node N2 connected to the gate of T T9 is FE
Turn on T T9. Therefore, the inverter stage output circuit 16 pulls down the output line 15 so as to transmit the mismatch.

When a match occurs (when no element is conducting), nodes N1 and N2 have a potential independent of others, node N2 is low enough to turn off FET T9, and node N1. Potential of FET T
8 is turned on and the level of the output line 15 is made sufficiently high to transmit a match. (As will be described later, more specifically, the upper latch circuit 12 and the lower latch circuit 14 apply the potential Vcc of the power supply to the node N1 and the potential Vground of the ground to the node N2.) FETs T3 and T4 The drain terminal and the gate terminal are crossed and connected to form an upper latch circuit. The drain of the FET T3 is connected to supply current to the node N1,
The drain of T4 is similarly connected to supply current to the node N2. The resistance formed by n-channel FET T1 is connected in the source circuit of FET T4. The corresponding resistor is not connected in the source circuit of FET T3, and the voltage drop due to this resistor will cause node N2 to be more than node N1 when both FETs T3 and T4 would conduct approximately equally. Try to have a low up level. FET T3 is FET
Greater than T4 (width-to-length ratio of T3 is greater than width-to-length ratio of T4) and FET T4 is not important in the description of the charge and discharge circuit.

The FET T2 has its source terminal connected to Vcc and its gate terminal connected to ground, so that it is the first time power is applied to the circuit, regardless of other initial conditions in the circuit. Turn on. FET
The drain terminal of T2 is connected to the drain terminal of FET T3, so that when FET T2 turns on when the power is turned on, it sets the circuit to the set state and sets FET T3 to the turned on state. FET T2 is a small device, sufficient to charge node N1 to its initial state, but sufficient conduction resistance to interfere with the operation of FET T3 charging and discharging node N1 during normal operation of the circuit. Does not have.

In the lower latch circuit, FETs T5 and T6
Have their gates X and drain terminals crossed and connected to form a latch. The drain terminal of the FET T5 is connected to the node N1 and the drain terminal of the FET T6 is connected to the node N2. FET T7 is electrically connected between ground and the common node of the source terminals of FETs T5 and T6. The gate of the FET T7 is connected to the node N1 and becomes conductive according to the potential of the node N1. When a match occurs, FET T3 conducts to pull up node N1, thereby causing FET T3 to
Turn on 2 more fully. The additional conduction of FET T7 helps pull down node N2. FE
T T7 has the opposite effect when a discrepancy occurs. That is, when the level of node N1 drops (in response to the conduction of one or more comparison circuit elements), F
The conduction state of the ET T7 is lowered, which causes the FET
The node N2 is charged at high speed through T3 and the FET of the conductive element.

The drain terminal of each FET of each latch circuit 12 and 14 is connected to the gate terminal of one FET of the other latch circuit through one node. For example, as already explained, the drain terminal of the FET T6 is F
It is connected to the gate X of ET T5, and F of the upper latch circuit
It is also connected to the gate X of ETT3.

The waveform of FIG. 2 shows two cycles of memory access, the output on line 15 (FIG. 1) is shown as MATCH, with down on the left representing a mismatch and up on the right representing a match. Therefore, the waveform on the left side of FIG. 2 shows the state of the component when there is a mismatch, and the waveform on the right side shows the state of the component when there is a match.

The waveform represents the bit position 0 as a representative. Assume that during these two memory cycles, a match occurred at every other bit position in the address. In this example, permanent bit 0 is a logical 1 and bit position F0
And a constant down level of its complement F0B. Therefore, in the circuit of FIG.
T11 is permanently on, and if signal A0 is high and turns on FET T10, it enables the output of the mismatch signal. FET T13 is permanently off, so conversely to the above, A0 is low and its complement A0B
Even if it turns on the FET T12, it prevents the output of the mismatch signal.

In the first cycle (left side) of FIG. 2, signal A
0 is a low level, representing 0 bit at bit position 0,
In the second memory cycle (right), signal A0 is high and represents a 1 at address bit position 0. Therefore, bit 0 causes a mismatch in the first memory cycle. If complement address bit A0B is not otherwise available in the address circuit, the transition occurs later than the transition for signal A0, and the change appears in the subsequent inverter logic stage.

During a match (ie, nodes N1 and N2 are not connected through any element in the compare circuit), as previously explained, the FE of the upper latch circuit.
TT2 turns on, which pulls up node N1. The drain terminal of FET T2 is the other FE
It should be noted that it is only connected to the gate terminal of T and that FET T2 conducts only when the capacitance at node N1 is charged to approximately the voltage Vcc of the power supply terminal. As will be explained later, the other FET also conducts only when charging or discharging the capacitances of the nodes N1 and N2, and then stops conducting.

The up level of the node N1 turns on the FETs T6 and T7 of the lower latch circuit, and these FEs are turned on.
The conduction of T pulls down node N2 to approximately ground level. These waveforms are shown at N1 and N2 in FIG. The up level of node N1 also turns off FET T4. The down level of the node N2 is FETT5
Is turned off, and FET T3 is turned on. From a different point of view, the capacitance of node N1 is charged to the voltage Vcc of the power supply and the capacitance of node N2 is discharged to ground.

When a mismatch occurs, the connection between nodes N1 and N2 discharges the capacitance of these nodes into the circuit of FETs T6 and T7.

It will be apparent that various modifications can be considered without changing the technical idea of the present invention.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an address comparison circuit of the present invention.

FIG. 2 is a waveform diagram showing the operation of each part of the circuit of FIG.

Claims (14)

[Claims] 1. A comparator circuit for comparing corresponding bit positions of a first register and a second register, means for providing true and complement values of bit positions of said two registers, each said The first element for the bit position (T10,
T11) and second elements (T12, T13), each element having a source terminal and a drain terminal of the first
Having two FETs connected in series between a node (N1) and a second node (N2), said FETs being responsive to a mismatch between associated register locations, said FETs of both said one element Has a gate terminal connected to receive the value of the bit of the register to turn on, thereby causing the two nodes to have substantially equal voltage values when a mismatch occurs at any bit position. A first and a second element having a voltage value at the node that is independent of each other when a match occurs at each bit position, and an output voltage (line 15) indicating a match or mismatch An output circuit means (16) connected to respond to a potential difference between the two nodes, for operating the output circuit means in response to a match. To charge the Nsu, comparator circuit including a charging circuit (12, 14) for connecting the two nodes between the power supply terminal and (Vcc) and the ground. 2. The charging circuit has a first FET (T3) and a second FET (T6) of opposite channel type, the first FET having the power supply terminal (Vcc) and the first FET (Tcc).
A drain terminal and a source terminal connected to the second node, and a gate terminal connected to the second node so as to turn on according to the potential of the second node, A second FET has a drain terminal and a source terminal connected between the second node and ground and is connected to the first node so as to turn on in response to the potential of the first node. The comparison circuit according to claim 1, further comprising a gate terminal. 3. The output circuit means comprises a third FET (T8) which has the same channel type as the first FET (T3) and a fourth FET which has the same channel type as the second FET (T6). A CMOS inverter stage (16) having a FET (T9), the third FET having a source terminal connected to the power supply terminal through the first FET, and the fourth FET
Has a source terminal connected to ground, the drain terminals of the third and fourth FETs are commonly connected to provide the output of the comparator circuit, and the gate terminals of the third and fourth FETs are 3. The comparator circuit according to claim 2, wherein the comparator circuit is commonly connected to the second node, and the output of the inverter stage is switched in response to the voltage of the second node. 4. The comparison circuit according to claim 3, wherein the source terminal of the third FET (T8) is connected to the first node. 5. The charging circuit (12, 14) has a drain terminal and a source terminal connected between ground and a source terminal of the second FET, and a gate terminal of the second FET. The second FET having a gate connected thereto
The fifth FET (T6) which has the same channel format as (T6)
7), whereby the second and fifth FETs are configured to conduct together in response to a potential at the first node, wherein the first, second, and fifth FETs are substantially The FETs having the same magnitude and configured during a mismatch to form a voltage divider and provide the first node and the second node with approximately half the voltage of the power supply. 4. The comparison circuit described in 4. 6. A sixth F, wherein said charging circuit (12, 14) is connected to said second FET (T6) in a latch arrangement.
6. The comparison circuit according to claim 5, including ET (T5). 7. The sixth FET (T5) conducts during a mismatch when the voltages at the first and second nodes are approximately equal, and the sixth FET is connected to the second FET (T6). )
7. The comparison circuit according to claim 6, wherein the comparison circuit is configured to be smaller than the second FET so as to avoid interference with the conduction of. 8. The sixth FET (T5) is provided with the second FET.
, A gate X connected to the first node, a drain terminal connected to the first node, and the second FET (T6)
8. The comparison circuit according to claim 7, further comprising a source terminal connected to a common connection point between the source terminal of the fifth FET (T7) and the drain terminal of the fifth FET (T7). 9. The charging circuit (12, 14) includes a seventh FET (T4) of the same type as the first FET (T3) and connected to the first FET in a latch arrangement, 9. The comparison circuit according to claim 8, wherein the seventh FET is configured to be sufficiently smaller than the first FET so as not to interfere with the influence of the conduction of the first FET on the circuit. 10. The seventh FET (T4) is provided with the first FET.
A voltage drop device (T1) having a gate terminal connected to the node and a drain terminal connected to the second node, the charging circuit connecting the source terminal of the seventh FET to the power supply terminal. 10. The comparator circuit according to claim 9, wherein the second node is configured so that it cannot rise closer to the voltage of the power supply terminal than the first node. 11. The first FET (T3) is better than the seventh FET (T3) to avoid the seventh FET (T4) from interfering with the effect of conduction of the first FET on the circuit. The comparison circuit according to claim 10, which is configured to be large. 12. The charging circuit is connected between the first node and the power supply terminal to charge the first node to an initial state when power is first applied to the comparison circuit. 12. The comparison circuit according to claim 11, including the means of. 13. The means for charging the first node to an initial state comprises a source terminal connected to the power supply terminal, a gate X connected to ground, and the first node (N1). An eighth channel having the same channel type as the first FET (T3), having a drain terminal connected to
FET (T2), wherein the eighth FET is the first FET
13. The comparator circuit of claim 12, configured to be sufficiently smaller than the first FET to avoid interfering with the switching action of the FET (T3) of FIG. 14. The first register stores a memory address for a word line and the second register stores an address of a defective word line.
The described comparison circuit.