JPH05135581A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the influence of capacity generated between the selected data lines without increasing the pattern area of a semiconductor integrated circuit. CONSTITUTION:A semiconductor integrated circuit contains plural data line pairs DB1a/DB1b-DB4a/DB4b which produce the complementary potentials of phases opposite to each other. Then the selected data lines DB1a, DB1b, DB3a and DB3b and other non-selected data lines DB2a, DB2b, DB4a end DB4b are arranged alternately to each other. Then the non-selected data lines are kept at the initial. potentials. Thus the capacities generated among the selected data lines are equivalently set at 0. Then the adverse influences caused by these capacities can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit such as a semiconductor memory device having a plurality of data line pairs, and more particularly to an arrangement structure of the data lines.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there is one described in Japanese Patent Laid-Open No. 2-9086, and its configuration will be described with reference to the drawings.

FIG. 2 is a schematic circuit diagram of a conventional semiconductor memory device which is one of semiconductor integrated circuits.

This semiconductor memory device is a dual port type device, and has dual port complementary data lines (eg, bit lines) BL1a and BL1 having ports A and B, respectively.
It has a pair of 1b (port A) and a pair of complementary data lines (for example, bit lines) BL2a and BL2b (port B) adjacent thereto, and the pair of bit lines BL1a, BL1b and B.
The ground shield line SL1 is arranged between the pair of L2a and BL2b. Bit line pair BL1 of ports A and B
a ・ BL1b, BL2a ・ BL2b and ground shield line S
The combination with L1 is arranged across the ground shield lines SL2 and SL3.

Bit line pair BL1a.BL1b, BL2a
BL2b has port A word line WLA and port B
And the word lines WLB are crossed and the memory cells 10 are connected to the respective crossing points. Each memory cell 10 has two N-channel MOS transistors (hereinafter referred to as NMOS) 11 and 12 for charge storage, which are connected in a crossed manner, and the NMOSs 11 and 12 are
Transfer NMO gated by word line WLA
It is connected to the pair of bit lines BL1a and BL1b via S13 and 14, respectively, and is further connected to the pair of bit lines BL2a and BL2b via transfer NMOSs 15 and 16 whose gate is controlled by the word line WLB.

A sense amplifier 20 is connected to the pair of bit lines BL1a and BL1b of the port A, and a bit line BL2 of the port B.
A sense amplifier 30 is connected to each pair of a and BL2b. The sense amplifier 20 is activated by the sense amplifier activation signal SA, and the bit lines BL1a and BL1 are activated.
It is a circuit for amplifying a minute potential difference on the pair b, and is composed of two NMOSs 21 and 22 which are cross-connected and an NMOS 23 whose gate is controlled by the sense amplifier activation signal SA.
It consists of and. Similarly, the sense amplifier 30
The bit line BL2a, the sense amplifier activation signal SB,
A circuit that amplifies a minute potential difference on the BL2b pair, and two NMOSs 31 and 32 that are cross-connected and an NMOS that is gate-controlled by a sense amplifier activation signal SB.
33 and 33.

Bit lines BL1a, BL1b, BL2a,
BL2b has parasitic capacitances C1, C2, C3 and C4, respectively, and further has a line capacitance C5 between the bit lines BL1a and BL1b and a line capacitance C6 between the bit lines BL2a and BL2b. .. Also, the bit line BL
There is an inter-line capacitance C7 between 1a and the ground shield line SL1, and the bit line BL2a and the ground shield line SL.
There is also a line capacitance C8 between 1 and 1. Since the opposite-phase charges are stored in the line capacitances C7 and C8, the bit line BL1
The line capacitance between b and BL2a does not equivalently exist because they cancel each other out.

Next, the operation will be described. The bit line pair BL1a / BL1b, BL2a / BL2b of the ports A and B is in a pre-initialized state, and the memory cell 10 has "1".
Is stored. First, the word line W of port A
When LA is activated (“H” level), a slight potential difference is generated between the pair of bit lines BL1a and BL1b of port A due to the stored data “1” of the memory cell 10. Next, the sense amplifier activating signal SA activates the sense amplifier 20, and the sense amplifier 20 activates the bit line BL1.
The minute potential difference between the pair a and BL1b is amplified, and the amplified data is output to the data bus via a transfer gate (not shown).

When the word line WLB of the port B is activated when a minute potential difference occurs between the pair of bit lines BL1a and BL1b, the pair of bit lines BL2a and BL2b are connected to the memory cell 10 as in the case of the port A. The stored data "1" causes a minute potential difference. Where port A
The sense amplifier activation signal SA at the sense amplifier 2
When it is input to 0, the sense amplifier 20 makes the bit line BL1
a, a small potential difference between the pair of BL1b and the bit line BL
The level difference between the “H” level and the “L” level of the pair of 1a and BL1b is determined.

Then, the level of the bit line BL2a is lowered due to the influence of the line capacitance between the bit lines BL1b and BL2a, the polarity of the potential difference between the bit lines BL2a and BL2b is reversed, and erroneous data reading is performed. There is a risk that However, since the ground shield line SL1 is provided between the bit lines BL1b and BL2a and the line capacitance between the bit lines BL1b and BL2a is equivalently 0, the bit line BL2a is affected by the bit line BL1b. No
The potential difference on the pair of bit lines BL2a and BL2b is accurately amplified by the sense amplifier 30.

As described above, even when an opposite phase potential is generated between the bit lines BL1b and BL2a, the ground shield line S
Since L1 is provided, the bit lines BL1b and BL1
The influence of the line capacitance between 2a can be reduced.

[0012]

However, in the circuit having the above configuration, the bit line BL1a and BL1b, and B
Since an opposite-phase potential is always generated between L2a and BL2b, between the bit line pairs BL1a / BL1b and BL2a / BL2b, the line capacitance C5 existing respectively between them.
And the effect of C6 cannot be reduced. Therefore, the bit line BL
Small potential difference between 1a and BL1b, and BL2a and BL2
In the case where each of the sense amplifiers 20 and 30 respectively amplifies a minute potential difference between b, there is a problem that the amplification speed becomes slow and the data transmission speed decreases.

To solve this problem, the bit line BL1
A shield line is provided between a and BL1b, and bit line B
It is conceivable to provide a shield wire also between L2a and BL2b. However, this increases the number of shield lines and increases the pattern area of the semiconductor integrated circuit. Therefore,
The line capacitance C between the bit lines BL1a and BL1b and between the bit lines BL2a and BL2b without increasing the pattern area.
It was difficult to reduce the influence of 5 and C6.

The present invention solves, as a problem of the prior art, a problem that it is difficult to reduce the influence of the line capacitance between bit lines in a bit line pair without increasing the pattern area. An integrated circuit is provided.

[0015]

In order to solve the above-mentioned problems, the present invention is provided with a plurality of pairs of data lines consisting of two data lines in which complementary potentials of opposite phases are generated. In a semiconductor integrated circuit such as a semiconductor memory device that selects and transmits data on the selected data line, the selected data line and other non-selected data lines are alternately arranged,
In addition, the non-selected data line is held at the initial potential.

[0016]

According to the present invention, since the semiconductor integrated circuit is configured as described above, by arranging the selected data lines and the non-selected data lines alternately and by keeping the non-selected data lines at the initial potential, A non-selected data line is arranged between the data lines, and the non-selected data line equivalently cancels the line-to-line capacitance between the selected data lines to 0, so that the adverse effect due to the line-to-line capacitance can be prevented. Therefore, the above problem can be solved.

[0017]

1 is a layout diagram of data lines in a semiconductor memory device which is one of semiconductor integrated circuits according to an embodiment of the present invention. This data line layout is as shown in FIG.
FIG. 3 is a diagram showing a configuration example of a Y decoder for selecting data of a plurality of bit line pairs and transferring the data to the data line pairs in the semiconductor memory device of FIG.

In the case of a large capacity semiconductor memory device, a large number of Y
Decoders 40-1 to 40-n are arranged. The Y decoder 40-1 includes a plurality of complementary bit line pairs BL10a.
BL10b to BL40a and BL40b and a plurality of complementary data line pairs DB1a, DB1b to DB4a and DB4
b between Y addresses Y0a, Y0b, Y1a to Yn.
A multi-input NAN that is a circuit that is selectively connected by a, and that calculates the NAND of a plurality of Y addresses Y1a to Yna.
It has a D gate 41, and two-input NOR gates 42 and 43 are connected to the output side thereof. NOR gate 42 has N
This is a circuit for obtaining the NOR of the output S41 of the AND gate 41 and the Y address Y0a. The NOR gate 43 is
This is a circuit for obtaining the NOR of the output S41 of the NAND gate 41 and the Y address Y0b. A transfer gate NMOS 44 is provided on the output S42 side of the NOR gate 42.
NOR gate 4 is connected to each gate of -1 to 44-4.
The transfer gate NMOS is also provided on the output S43 side of 3
Gates 44-5 to 44-8 are connected.

The drain / source of the NMOS 44-1 is connected to the bit line BL10a and the data line DB1a. Similarly, the NMOS 44-2 is connected to the bit line BL10b and the data line DB1b, and the NMOS 44-3 is connected to the bit line BL.
30a and data line DB3a, NMOS44-4 to bit line BL30b and data line DB3b, NMOS44-.
5 is an NMO for the bit line BL20a and the data line DB2a.
S44-6 is a bit line BL20b and a data line DB2b.
The NMOS 44-7 is connected to the bit line BL40a and the data line DB4a, and the NMOS 44-8 is connected to the bit line BL40b and the data line DB4a.

That is, in this Y decoder 40-1, NO
Selected data lines selected by the NMOSs 44-1 to 44-8 which are turned on by the outputs S42 and S43 of the R gates 42 and 43 and the other unselected data lines are arranged alternately and are not selected. The data line has a circuit configuration in which it is held at an initial potential (for example, VCC / 2 and VCC are power supply potentials).

Similar to the Y decoder 40-1, the Y decoder 40-2 has a Y address Y0a.Y0b, Y1b, Y2.
a to Yna are decoded, and bit line pair BL11a / BL
11b to BL41a and BL41b and data line pair DB1a
A circuit that selectively connects DB1b to DB4a and DB4b. Similarly, the Y decoder 40-n decodes Y addresses Y0a, Y0b, Y1b to Ynb,
Bit line pair BL1na / BL1nb to BL4na / BL
4nb and data line pair DB1a / DB1b to DB4a / D
This is a circuit for selectively connecting to B4b.

FIG. 3 is an operation waveform diagram of FIG. 1, and the operation of FIG. 1 will be described with reference to this figure.

For example, a conventional memory cell 1 as shown in FIG.
When reading data from 0, the sense amplifier 2
The sense operation of 0 and 30 causes the bit line pair BL1 of FIG.
0a.BL10b to BL40a.BL40b become "H" level or "L" level. At this time, bit line B
Since L10a to BL40a and BL10b to BL40b are complementary, when one becomes "H" level, the other becomes "L" level. After that, Y addresses Y1a to Yn
When a becomes "H" level, the output S41 of the NAND gate 41 becomes "L" level. And Y address Y0
When a or Y0b goes to "L" level, the output S42 or S43 of the NOR gates 42 and 43 goes to "H" level. The solid line in FIG. 3 shows the case where the Y address Y0a and the output S42 of the NOR gate 42 are selected.

When the output S42 of the NOR gate 42 becomes "H" level, the transfer gate NMOS 44-1
To 44-4 are turned on, and the bit lines BL10a, B10
The data of L10b, BL30a, BL30b is the NMO.
Data lines DB1a, DB via S44-1 to S44-4
1b, DB3a, DB3b. At this time, since the transfer gate NMOSs 44-2 to 44-8 are in the off state, the data lines DB2a, DB2b, DB4a,
DB4b maintains the initial state (for example, potential VCC / 2).

On the other hand, when the Y address Y0b is selected, the operation shown by the broken line in FIG. 3 is performed. NAND gate 41
The operation is the same as that described above until the output S41 of the signal goes from "H" level to "L" level.

Next, the Y address Y0a remains at "H" level, but when the Y address Y0b changes from "H" level to "L" level, the output S43 of the NOR gate 43 is output.
Goes to the "H" level, and the output S42 of the NOR gate 42 is output.
Keeps the "L" level. Output S43 of NOR gate 43
Becomes “H” level, NMO for transfer gate
S44-5 to 44-8 are turned on, and the bit line BL
The data of 20a, BL20b, BL40a, and BL40b are transferred to the data line DB through the NMOSs 44-5 to 44-8.
2a, DB2b, DB4a, DB4b. At this time, another transfer gate NMOS 44-1 to
Since 44-4 is in the off state, the data lines DB1a, DB1
b, DB3a, DB3b are in the initial state (for example, the potential VC
Keep C / 2).

In the above description, the Y decoder 40-1 causes the four bit lines BL10a, BL10b, BL30.
a, BL30b or BL20a, BL20b, BL4
Although the case where 0a and BL40b are selected has been described, in the case of a large capacity semiconductor memory device, Y decoders 40-1 to 40
There are cases where four bit lines are selected from -n.

As described above, in this embodiment, the data line D
Of B1a, DB1b to DB4a, DB4b, selected data lines and non-selected data lines are alternately arranged, and the non-selected data lines are kept in the initial state. Since the held non-selected data lines are arranged, the line-to-line capacitance between the selected data lines is canceled by the non-selected data lines existing between them and becomes equivalently zero. Therefore, the influence of the line capacitance between the selected data lines can be reduced, and the data transmission speed can be improved. Moreover, the data line D is the same as the conventional one.
Since no ground shield line is provided between B1a, DB1b to DB4a, DB4b, the pattern area in the semiconductor memory device can be reduced.

The present invention is not limited to the above embodiment,
Various modifications are possible. Examples of such modifications include the following. (A) In the above embodiment, the initial potential of the non-selected data line is set to the potential VCC / 2, but this initial potential may be set to any potential such as the power supply potential VCC or the ground potential.

(B) Although the number of complementary data line pairs is 4 bits in FIG. 1, these can be set to any number. Similarly, the number of bit line pairs of each Y decoder 40-1 to 40-n can be set to any number other than 4 bits. In response, the NAND gate 41 and the NOR gates 42 and 43
The decoder section of may be changed to another circuit configuration. Also, transfer gate NMOSs 44-1 to 44-
8 may be changed to another transistor configuration such as a P-channel type MOS transistor.

(C) In the above embodiments, the wiring structure of the data lines in the semiconductor memory device has been described, but the above embodiments can be applied to various other semiconductor integrated circuits having a plurality of data line pairs.

[0032]

As described above in detail, according to the present invention, the selected data lines and the unselected data lines are alternately arranged, and the unselected data lines are kept at the initial potential. An unselected data line exists between each two complementary data lines, and the line capacitance between the two selected data lines is equivalently zero. Therefore, the effect of the line capacity can be reduced, and the effect of improving the data transmission rate can be expected. Moreover, the non-selected data line provided between the selected data lines is conventionally used as a ground shield line, but since it is used as a data line in the present invention, it does not increase the pattern area of the integrated circuit. , The influence of the line capacitance between the selected data lines can be accurately prevented.

[Brief description of drawings]

FIG. 1 is a wiring configuration diagram of data lines in a semiconductor memory device showing an embodiment of the present invention.

FIG. 2 is a schematic circuit diagram of a conventional semiconductor memory device.

3 is an operation waveform diagram of FIG. 1. FIG.

[Description of Reference Signs] 40-1 to 40-n Y decoder 44-1 to 44-8 Transfer gate NMOS BL10a / BL10b to BL40a / BL40b, B
L11a / BL11b to BL41b / BL41b, BL
1na / BL1nb to BL4na / BL4nb Bit line DB1a / DB1b to DB4a / DB4b Data line Y0a / Y0b to Yna / Ynb Y address

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location // H01L 21/82 9169-4M H01L 21/82 W

Claims (1)

[Claims] 1. A semiconductor integrated circuit comprising: a plurality of data line pairs, each of which is formed of two data lines in which complementary opposite-phase potentials are generated, selecting one of the data lines and transmitting data on the selected data line. A semiconductor integrated circuit characterized in that the selected data lines and the other non-selected data lines are alternately arranged and the non-selected data lines are held at an initial potential.