JPH05130611A - Descrambling circuit - Google Patents

Abstract

PURPOSE:To provide a descrambling circuit prevented from initializing descrambling operation in error even when a signal similar to a scramble identification (ID) signal or a synchronizing pattern signal appears. CONSTITUTION:This descrambling circuit is constituted of a descrambling stability judging circuit 12 for counting up outputs from a scramble signal judging circuit 5 and detecting the stability of descrambling operation, a mask timing generating circuit 13 for triggering the output of the circuit 12 and outputting a masking signal in a period other than the superposed period of a scramble ID signal based upon an output from a descrambling timing signal generating circuit 6 and a scrambling ID signal masking circuit 11 for masking an output from a scramble identifying signal extracting circuit 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cable television (CATV) system, and more particularly to a scrambled signal descrambling technique for realizing a confidential service for a specific subscriber.

[0002]

2. Description of the Related Art In recent years, services for general terrestrial television broadcasting have come to the point that they cannot meet the diversifying needs of viewers in recent years because their channels are limited by the width of the broadcasting band. The number of viewers who subscribe to a CATV system using a cable network is increasing.

The current CATV system is an urban CAT.
The market is expanding centering around a system called a V system, and a paid service is provided only to a specific contractor in this system. The problem with paid services is that they are highly confidential, and for that reason image information is scrambled. That is,
The image information of the pay service is processed by a specific means so that the image cannot be reproduced only by a normal television receiver. In order to reproduce this scrambled signal into the original television signal, descramble processing is performed based on the key signal sent together with the scrambled signal.

An example of the scramble signal and the descramble circuit by the amplitude compression of the vertical and horizontal synchronizing signals will be described with reference to FIGS. 3, 4 and 5.

FIG. 3 shows a timing diagram of the descrambling process. (A) is a scrambled signal, which is compressed to a certain level for a certain period including the horizontal blanking period,
Even if an attempt is made to reproduce a screen on a normal television receiver as it is, horizontal synchronization is not applied and a normal reproduction screen cannot be obtained. (B) is a timing signal for returning the scrambled signal (a) to the original television signal by descrambling, and returns the scrambled signal (a) by a predetermined level. (C) is a signal in which the scramble signal (a) is descrambled based on the descramble timing signal (b), and this signal enables screen reproduction by a normal television receiver.

FIG. 4 is for identifying whether the input signal is a scramble signal, extracting key data for descrambling if it is a scramble signal, and generating the descramble timing signal of FIG. 3 (b). FIG.

FIG. 4A shows a scramble identification signal, a sync pattern signal and key data, which are superimposed in the vertical blanking period of the scramble signal. f is a scramble identification signal for identifying a scramble signal, and is a signal obtained by superimposing a sine wave (for example, about 20 μsec) of a frequency (for example, 2 MHz) in the video band on the scramble signal.

[0008] g is a synchronization pattern signal, and after detecting the scramble identification signal f, by checking a specific bit pattern of 8-bit length (10101001 in the example of Fig. 4), whether this signal is a scramble signal or not And simultaneously activate the counter for generating the descramble timing signal of FIG. 3 (b). h is key data, which is a 16-bit data string including information such as the compression level of the scrambled signal.

FIG. 4B is a scramble identification signal diagram 4
(F) in (a) is extracted by a bandpass filter and the waveform is shaped, and the width of this signal is checked (for example, 1
8 μS or more), the scramble identification signal is detected.

FIG. 4 (c) shows a timing signal for extracting the sync pattern signal g following the scramble identification signal f as a trigger, and FIG. 4 (d) also follows the g with the scramble identification signal f as a trigger. A timing signal for extracting the key data h, i is a synchronization pattern extraction timing signal, and j is a key data extraction timing signal. FIG. 4E shows a sync pattern signal extracted within the sync pattern extraction timing signal i period,
FIG. 4F shows the key data extracted within the period of the key data extraction timing signal j.

FIG. 5 shows an example of the configuration of a conventional descramble circuit. In FIG. 5, reference numeral 1 denotes a scramble identification signal extracting circuit configured by a bandpass filter, a waveform shaping circuit, or the like for extracting the scramble identification signal f.

Reference numeral 2 is a scramble identification signal detection circuit for checking the width in order to distinguish the scramble identification signal extracted by the scramble identification signal extraction circuit 1 from noise, and is composed of a counter or the like.

Reference numeral 3 is a sync pattern extraction timing signal i for extracting the sync pattern signal g and the key data h by using the detection signal of the scramble identification signal detection circuit 2 as a trigger.
And a synchronization pattern key data extraction timing signal generating circuit for generating the key data extraction timing signal j,
It is composed of a counter.

Reference numeral 4 denotes a synchronous pattern extracting circuit for extracting the synchronous pattern signal based on the synchronous pattern extracting timing signal i generated by the synchronous pattern / key data extracting timing signal generating circuit 3, which is composed of a gate circuit or the like. There is.

Reference numeral 5 denotes a scramble signal determination circuit for checking the bit pattern of the synchronization pattern signal extracted by the synchronization pattern extraction circuit 4 to determine whether it is a regular scramble signal, which is a shift register or a comparator. When it is determined that the signal is a regular scramble signal, a descramble start timing signal is output.

Reference numeral 6 denotes a descramble timing signal generation circuit for generating a descramble timing signal by using the descramble start timing signal output from the scramble signal determination circuit 5 as a trigger, which is a horizontal synchronization timing counter or a vertical synchronization timing counter. It is configured.

Reference numeral 7 is a key data extracting circuit for extracting the key data based on the key data extracting timing signal j generated by the synchronization pattern / key data extracting timing signal generating circuit 3, and is composed of a gate circuit or the like. There is.

Reference numeral 8 denotes a key data decoding circuit for decoding the key data extracted by the key data extracting circuit 7, which is composed of a decoder or the like.

A descrambling level generating circuit 9 for determining the descramble level of the scramble signal based on the data decoded by the key data decoding circuit 8 is composed of a flip-flop circuit or the like.

Reference numeral 10 denotes a descramble timing signal generated by the descramble timing signal generating circuit 6,
A descramble processing circuit for descrambling the scramble signal in accordance with the descramble level signal generated by the descramble level generating circuit 9, which is composed of an amplifier circuit and the like.

The above is a description of one configuration example of the conventional descramble circuit. Next, the descrambling operation will be described with reference to FIGS. 3, 4 and 5.

When a scramble signal as shown in FIG. 3A is input to the descramble circuit of FIG. 5, the scramble identification signal extracting circuit 1 of FIG. 5 extracts the scramble identification signal and converts it into a digital signal. A width check is performed by the scramble identification signal detection circuit 2. When it is confirmed that the signal is a regular scramble identification signal, the synchronization pattern / key data extraction timing signal generation circuit 3 is activated, the synchronization pattern extraction timing signal i is transmitted to the synchronization pattern extraction circuit 4, and the key data extraction timing signal j
Is transmitted to the key data extracting circuit 7.

The sync pattern extracting circuit 4 extracts a bit string from the scramble signal within the sync pattern extracting timing signal i period and converts it into a digital signal.

The extracted sync pattern signal is sent to the scramble signal determination circuit 5, and the value of the bit string is checked. When it is confirmed that the synchronization pattern signal is regular, the descramble start timing signal is output and the descramble timing signal generation circuit 6 is activated.

Descramble timing signal generation circuit 6
Sends a descramble timing signal to the descramble processing circuit 10.

The key data extraction circuit 7 extracts a bit string of key data from the scramble signal and the key data extraction timing signal j and converts it into a digital signal.

The key data converted into a digital signal is sent to the key data decoding circuit 8 to read the descramble level from the pattern of the key data bit string,
It is sent to the descramble level generation circuit 9.

The descramble level generation circuit 9 sends a descramble level signal to the descramble processing circuit 10 based on the descramble level data from the key data decoding circuit 8.

In the descramble processing circuit 10, according to the descramble timing signal and the descramble level signal, the gate circuit and the amplifier circuit perform expansion processing during the level compression of the scramble signal to perform a normal television signal. Restore to.

The above is the description of the operation of the conventional descramble circuit.

[0031]

However, in the above circuit configuration, even after the descrambling operation becomes stable,
When a signal that is very similar to the scramble identification signal and the synchronization pattern signal appears on the video signal in the scramble signal, the descrambling operation is initialized from the misrecognition of the regular scramble identification signal and the synchronization pattern signal. However, there is a problem that the display screen is disturbed because the horizontal and vertical descrambling timings are deviated.

In view of the above problems, the present invention erroneously initializes the descrambling operation even after a signal very similar to the scramble identification signal and the sync pattern signal appears on the video signal after the descramble is stabilized. It is intended to provide a descramble circuit that does not exist.

[0033]

A descramble circuit according to the present invention comprises a scramble identification signal extracting circuit for extracting a scramble identification signal which is a trigger for descrambling start superimposed on a scramble signal, and the scramble identification signal extracting circuit. Of the output pulse of the scramble identification signal mask circuit for masking the period other than the timing at which the scramble identification signal is superposed after the output of is descrambled is stable, and the width of the output pulse of the scramble identification signal mask circuit is checked, If so, a scramble identification signal detection circuit for recognizing the scramble identification signal, and a synchronization pattern signal having a prescribed bit pattern having information serving as a starting point of descrambling timing based on the recognized scramble identification signal. Descramble compression A synchronization pattern key data extraction timing generation circuit for generating a timing signal for extracting key data having information such as a descramble mode indicating a bell from the scramble signal, and the synchronization pattern key data extraction timing signal, A sync pattern extracting circuit for extracting a sync pattern signal from the scramble signal and the bit pattern of the sync pattern signal are checked, and if the sync pattern coincides with the prescribed sync pattern, the input signal is determined to be a scramble signal, and the descramble is performed. A scramble signal determining circuit for generating a start timing signal, and a descramble timing for restoring the original television signal by extending the compressed vertical and horizontal blanking periods by using the descramble start timing signal as a trigger. The generated issue,
At the same time, a descramble timing signal generation circuit that generates timing signals for vertical and horizontal blanking periods and the descramble start timing signal are monitored, and when the signal is counted a prescribed number of times or more, the descramble operation is regarded as stable and descramble stable. A descramble stability determination circuit that outputs a detection signal, and a period other than a period in which the scramble identification signal is superimposed by the vertical and horizontal blanking period timing signals from the descramble timing signal generation circuit and the descramble stability detection signal The mask data is generated from the scramble signal by a mask timing generation circuit that generates a mask timing for masking the period of and output to the scramble identification signal mask circuit, and the synchronization pattern key data extraction timing signal. A key data extracting circuit for taking, a key data decoding circuit for decoding the key data to take out the scramble mode and the like, and a descramble for performing expansion corresponding to the compression level of the scramble signal based on the scramble mode. A descramble level generation circuit for generating a level, a descramble timing signal, and a descramble processing circuit for descramble the scramble signal by the descramble level signal.

[0034]

In the structure of the present invention, after the descrambling operation is stabilized, the timing at which the regular scramble identification signal and the sync pattern signal are superimposed even if a signal very similar to the scramble identification signal and the sync pattern signal is received on the video signal. Since the others are masked, the descrambling operation is not accidentally initialized.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, blocks 1 to 10 are the same as those in the conventional example shown in FIG. Reference numeral 11 denotes a scramble identification signal mask circuit that masks the output of the scramble identification signal sampling circuit 1 in a period other than the timing when the scramble identification signal is superimposed on the scramble signal. A descrambling stability determination circuit 12 monitors the output of the scramble signal determination circuit 5, counts the descramble start timing signal that is output, and outputs a descrambling stability detection signal assuming that the descrambling operation is stable when counting the specified number of times. Is. A scramble identification signal 13 is superimposed on the basis of the vertical / horizontal retrace line timing signal output from the descramble timing signal generation circuit 6 by using the descramble stability detection signal output from the descramble stability determination circuit 12 as a trigger. It is a mask timing generation circuit that generates a mask timing signal for masking a period other than the period.

The operation of the descramble circuit configured as described above will be described. Immediately after the input signal is switched to the scramble signal, the descramble stability determination circuit 12 and the mask timing generation circuit 13 are in a stopped state, and the scramble identification signal mask circuit 11 keeps the input signal from the scramble identification signal extraction circuit 1 as it is. Since it is output to the scramble identification signal detection circuit 2, the descramble circuit as a whole of FIG. 1 starts the descramble operation in the same process as the conventional example. Here, the descramble start timing signal from the scramble signal determination circuit 5 is used as a trigger to activate the descramble timing signal generation circuit 6, but at the same time, this descramble start timing signal becomes an input to the descramble stability determination circuit 12 and is descrambled. Stability determination circuit 12
Counts how many times the descramble start timing signal is generated. When the count value reaches the specified number, the descrambling stability determination circuit 12 regards the descrambling operation as a steady state and outputs the descrambling stability detection signal.

The mask timing generation circuit 13 is activated by the descramble stability detection signal as a trigger. After the start-up, the mask timing generation circuit 13 outputs the vertical timing output from the descramble timing signal generation circuit 6.
A mask timing signal for masking a period other than the period in which the scramble identification signal is superimposed is generated based on the horizontal blanking period timing signal. The scramble identification signal masking circuit 11 masks the output of the scramble identification signal extracting circuit 1 by the mask timing signal output from the mask timing generating circuit 13 and outputs the masked output to the scramble identification signal detecting circuit 2.

Next, after the descramble operation is stabilized, a signal in which the frequency and the appearance period of the scramble identification signal and the generation timing and bit pattern of the synchronization pattern signal are very similar to each other appear during the video signal period. The descrambling operation of the embodiment of the invention will be described with reference to FIG.

In FIG. 2A, a normal scramble identification signal f, a sync pattern signal g, and key data h are superimposed on a vertical blanking signal, and a signal r and a sync pattern which are very similar to the scramble identification signal f during a video period. It is a scrambled signal including a signal m that is very similar to the signal g. Figure 2 (a)
2 is input to the descramble circuit of FIG. 1, the scramble identification signal extracting circuit 1 of FIG.
The signal as shown in (b) is output. In FIG. 2B, n is a signal extracted from the regular scramble identification signal f of FIG. 2A by the scramble identification signal extracting circuit 1, and o is a signal extracted from the signal r that is very similar to the scramble identification signal. .. FIG. 2C shows an example of the mask timing signal output from the mask timing generation circuit 13 after the descrambling operation is stabilized. In this case, the timing signal is such that the period other than the horizontal scanning period in which the scramble identification signal f is superimposed is masked in the vertical blanking period. 2D shows a signal obtained by masking the signal shown in FIG. 2B with the mask timing signal shown in FIG. 2C by the scramble identification signal mask circuit 11. Here, the mask timing signal of FIG.
(B) A signal that is very similar to the scramble identification signal of o (see FIG. 2).
The signal extracted from r) of (a) is masked and is not output, and the regular scramble identification signal (f of FIG. 2 (a)).
Only the signal extracted from is output. 2 (e) is shown in FIG.
The normal sync pattern signal p and the key data q extracted based on the signal (d).

As described above, in the descramble circuit of the embodiment of the present invention, even if a signal very similar to the scramble identification signal or the sync pattern signal appears in the video signal after the descramble operation is stabilized, the scramble identification signal The masking process distinguishes the regular scramble identification signal and the synchronization pattern signal from each other, and does not initialize the descramble operation at an incorrect timing.

[0042]

As described above, according to the present invention, the scramble identification signal extracting circuit for extracting the scramble identification signal which is the trigger for descrambling start superimposed on the scramble signal and the output of the scramble identification signal extracting circuit are After the scramble is stabilized, the scramble identification signal mask circuit for masking a period other than the timing at which the scramble identification signal is superimposed, and the width of the output pulse of the scramble identification signal mask circuit are checked. A scramble identification signal detection circuit for recognizing that it is a scramble identification signal, and a sync pattern signal and a descramble compression level having a prescribed bit pattern having information serving as a starting point of descramble timing based on the recognized scramble identification signal. Descramble showing A synchronization pattern / key data extraction timing generation circuit for generating a timing signal for extracting key data having information such as a lock mode from the scramble signal, and the synchronization pattern / key data extraction timing signal for the synchronization pattern signal. A synchronization pattern extraction circuit that extracts from the scrambled signal,
A scramble signal determination circuit that checks the bit pattern of the synchronization pattern signal, determines that the input signal is a scramble signal if it matches the prescribed synchronization pattern, and generates a descramble start timing signal, and the descramble start timing signal. To generate a descramble timing signal to expand the compressed vertical / horizontal retrace period to restore the original television signal, and at the same time generate a vertical / horizontal retrace period timing signal. When the scramble timing signal generating circuit and the descrambling start timing signal are monitored and the signal is counted a prescribed number of times or more,
By a descramble stability determination circuit that outputs a descramble stability detection signal as a descramble operation is stable, and the vertical / horizontal retrace period timing signal and the descramble stability detection signal from the descramble timing signal generation circuit. A mask timing generating circuit for generating a mask timing for masking a period other than the period in which the scramble identification signal is superimposed, and outputting the mask timing to the scramble identification signal mask circuit, and the synchronization pattern key data extraction timing signal, A key data extracting circuit for extracting the key data from the scramble signal, a key data decoding circuit for decoding the key data to extract the scramble mode, and a scramble signal of the scramble signal based on the scramble mode. A descrambling level generation circuit that generates a descrambling level for performing decompression corresponding to the compression level, a descramble timing signal, and a descramble processing circuit that descrambles the scramble signal by the descrambling level signal. By providing the descramble operation, it is possible to provide a descramble circuit that does not erroneously initialize the descramble operation even if a signal very similar to the scramble identification signal and the synchronization pattern signal is received on the video signal after the descramble operation is stabilized.

[Brief description of drawings]

FIG. 1 is a block diagram of a descramble circuit according to an embodiment of the present invention.

FIG. 2 is an operation timing chart when a signal very similar to a scramble identification signal / synchronization pattern signal appears during the same video period.

[Fig. 3] Timing diagram of descrambling process

FIG. 4 is a timing diagram of scramble identification signal, sync pattern signal, and key data extraction.

FIG. 5 is a block diagram of a conventional descramble circuit.

[Explanation of symbols]

1 scramble identification signal extraction circuit 2 scramble identification signal detection circuit 3 synchronization pattern / key data extraction timing signal generation circuit 4 synchronization pattern extraction circuit 5 scramble signal determination circuit 6 descramble timing signal generation circuit 7 key data extraction circuit 8 key data decoding circuit 9 descramble level generation circuit 10 descramble processing circuit 11 scramble identification signal mask circuit 12 descramble stability determination circuit 13 mask timing generation circuit

Claims (1)

[Claims] 1. A circuit used for descrambling a CATV scramble signal for performing amplitude compression or sync shift of vertical and horizontal synchronizing signals with respect to a video signal, and further switching the compression level or shift level in plural levels at an indefinite cycle. There is a scramble identification signal extracting circuit for extracting a scramble identification signal which is a trigger for descrambling start superimposed on the scramble signal, and an output of the scramble identification signal extracting circuit for superimposing the scramble identification signal after the descramble is stabilized. The scramble identification signal mask circuit for masking a period other than the specified timing, and the scramble identification signal mask circuit for checking the width of the output pulse of the scramble identification signal mask circuit and recognizing that the scramble identification signal is the above-mentioned width identification A signal detection circuit, and based on the recognized scramble identification signal, a synchronization pattern signal having a prescribed bit pattern having information serving as a starting point of descramble timing, and information such as a descramble mode indicating a descramble compression level. A synchronization pattern / key data extraction timing generation circuit for generating a timing signal for extracting key data from the scramble signal, and a synchronization for extracting the synchronization pattern signal from the scramble signal by the synchronization pattern / key data extraction timing signal. Check the pattern sampling circuit and the bit pattern of the synchronization pattern signal,
A scramble signal determination circuit that determines the input signal to be a scramble signal if it matches the specified synchronization pattern, and generates a descramble start timing signal,
The descramble start timing signal is used as a trigger to generate a descramble timing signal for expanding the compressed vertical / horizontal retrace period to restore the original television signal, and at the same time, to generate the vertical / horizontal retrace period timing. A descramble timing signal generating circuit that generates a signal and the descramble start timing signal are monitored, and when the signal is counted a specified number of times or more, a descramble stabilization detection signal is output as if the descramble operation is stable. A decision circuit,
The vertical / horizontal retrace period timing signal from the descramble timing signal generation circuit and the descramble stability detection signal generate mask timing for masking a period other than the period in which the scramble identification signal is superimposed. A mask timing generation circuit for outputting to the scramble identification signal mask circuit; and a key data extraction circuit for extracting the key data from the scramble signal by the synchronization pattern / key data extraction timing signal, and decoding the key data. A key data decoding circuit for extracting the scramble mode and the like, a descramble level generation circuit for generating a descramble level for performing expansion corresponding to the compression level of the scramble signal based on the scramble mode, and the descrambling level generating circuit. Descramble circuit having a crumble timing signal, and a descrambling circuit for descrambling the scrambled signal by said descramble level signal.