JPH05130128A - Atm exchange system - Google Patents

Abstract

PURPOSE:To constitute the ATM network in which a cell abort characteristic and delay characteristic are obtained definitely by implementing statistic multiplexing in a frame comprising plural cells in order to facilitate control of a control plane of the ATM network. CONSTITUTION:A buffer selection device 26 selects the changeover of input and output of a cell to buffers 23, 24 storing an inputted cell in the unit of frames based on Stop-and-Go Queueing rules in the unit of frames. A cell outputted from the buffers 23, 24 is given to a cell SW 28 via a cell output device 27 to implement cell switching and when a cell is outputted to a prescribed output link, the cell output device 27 outputs the cell to a cell SW 28 according to the transfer order of the cells decided based on the priority given to each cell stored in the buffers 23, 24.

Description

Detailed Description of the Invention

[0001]

The present invention relates to Stop-and-Go Queueing
The present invention relates to an ATM switching system adopting the method.

[0002]

2. Description of the Related Art Recently, an ATM (Asynchronous Transfer Mode) switching network has been put into practical use as a network for realizing multimedia communication that integrates voice, data, still images, moving images and the like.

In such an ATM switching network, information communication is performed using short packets having a fixed length called cells. In this case, the cells are output from the transmission side terminal at arbitrary timing, and other cells are output. It is multiplexed with the cell from the transmitting terminal and is sent to the intended receiving terminal via the ATM switch.

Usually, a large-scale ATM switch is constructed by connecting unit SWs having n inputs and n'outputs in multiple stages. For example, when cross connection is used as the connection method, ATM
There will be multiple forwarding routes for cells in the switch.

For example, when an n-input n-output ATM switch with N = nm is constructed by using m n-input n-unit SWs in parallel, there are m routes in the ATM switch. Therefore, an algorithm for deciding which route to select is needed.

[0006]

However, the conventional AT
In the M switch, once a call is connected, the route is not changed in the switch, so blocking may occur and the throughput of the switch may be significantly reduced. Therefore, in order to solve this problem, the internal speed of the switch is increased, and the parallel degree of the unit SW is increased to increase the internal route. However, it is important to increase the internal speed of the switch from the viewpoint of semiconductor performance. There is a limit, and the unit SW
Increasing the degree of parallelism has the disadvantage that it is economically disadvantageous.

Further, in such an ATM switch, calls having different output trunks may pass through the same unit SW and affect each other. Therefore, when calculating the discard rate and the delay characteristic, the ATM switch may be used. It is necessary to consider the characteristics of all the calls connected to the switch, and the calculation becomes enormous.

Further, since the cells are statistically multiplexed, it is not known where in the buffer the cells will be placed when they arrive at the unit SW. Therefore, when a unit SW having K stages of buffers is used, the buffering delay of the entire ATM switch is 3K stages at the maximum and 0 stages at the minimum. This caused a large fluctuation in cell arrival time from the viewpoint of the receiving terminal.

Further, in the ATM switching network, each transmitting terminal can output a cell at an arbitrary timing, so it is not possible to definitively define the peak value or average value of the cells output from these transmitting terminals. Therefore, the cell discard rate and the delay characteristic can only be obtained stochastically, making call connection control very difficult. Also, IEEE Communicati
In the leaky bucket proposed in ons Magazine Vol.24, No.10 (1986), the peak value and the average value are also measured when polishing is performed to monitor whether the terminal is outputting cells in compliance with the declared parameters. There was also the problem that it could not be confirmed.

The present invention has been made in view of the above circumstances, and is expected to improve efficiency by statistically multiplexing cells, improve SW characteristics and fluctuation characteristics, and expect simpler admission control and policing. It is an object of the present invention to provide an ATM exchange system that can be used.

[0011]

[Means for Solving Problems] By the way, recently, ICC'90
“Congestion-Free Commun described in Proceedings pp. 308.3.1.
As proposed in "ication in Broadband Packet Networks", an ATM switching system in which a frame composed of T cells based on Stop-and-Go Queueing is synchronized in the whole network is considered. The present invention is applied to such an ATM switching system based on Stop-and-Go Queuing.

The present invention is an input in an ATM switching system in which a frame composed of T cells is synchronized in the entire network based on stop-and-go queuing. Buffer for accumulating cells to be stored in frame units, buffer selecting means for selecting input / output of cells to / from the buffer in frame units based on the stop-and-go queuing rule, and performing cell switching and predetermined Cell SW for outputting cells to the output link, unit SW having a cell output device for transferring cells from the buffer to cells SW, and determining the transfer order of cells based on the priority given to the cells accumulated in the buffer It is configured by a cell order configuring unit.

The present invention is also directed to an ATM switching system in which a frame composed of T cells is synchronized in the entire network based on stop-and-go queuing. , Stop-and-Go Qu
N × N multi-stage connection SW in which unit SWs for performing eueing are cross-connected, and first-stage unit SW for frame synchronization
Considering the buffer attached to each incoming line, priority regarding the discard rate added to the cell accumulated in the buffer in the unit SW of the first stage, cell arrival order, terminal that caused the cell, and cell destination address Cell output order configuration device A for determining the output order of cells and the unit S of the first stage
The priority regarding the discard rate added to the cell accumulated in the buffer in W, the terminal that originated the cell, the routing tag addition device that determines the internal route of the cell in consideration of the destination address of the cell, and the second stage A cell output order configuration device B that determines the output order of the cells stored in the buffer in the unit SW, and a cell output order configuration device C that determines the output order of the cells stored in the buffer in the third-stage unit SW
It is composed by.

Further, the present invention is based on Stop-and-Go Queueing.
In an ATM switching system in which frames composed of individual cells are synchronized in the entire network, a cell number measuring means for counting the number of cells in a frame of cells input from a terminal for each call, and at the time of call setting. Declaration parameter storage means for storing the declared peak value declaration parameters, it is determined whether or not the number of cells counted by the cell number measuring means exceeds the peak value declaration parameters stored in the declaration parameter storage means. And a polishing function having a comparison means for performing the above.

[0015]

As a result, according to the present invention, when the traffic in which the image and the voice are multiplexed is taken as an example, in general, the required value for the cell discard characteristic of the image is 10 ^-9 , whereas in the case of the voice. A quality of about 10 ^-3 is sufficient.
In order to efficiently multiplex this different quality of traffic, if a high priority is given to the image and a low priority is given to the voice, it is preferentially transferred from the cell of the high priority, so if the band of the image is allocated at the peak. While maintaining the discard rate of image cells at 0 and the discard rate of voice cells at 10 ⁻³ , efficiency can be realized by statistical multiplexing.

The N × N ATM switch has a unit of S
It is a rearrangeable type with W cross-connected, and since the internal route is set in consideration of the cell output trunk for each frame, it becomes non-blocking, and the N × N ATM switch has a single output. It has the same characteristics as the buffer type switch. This will increase the internal speed of the switch,
This means that it is not necessary to increase the parallelism of the unit SWs in order to increase the number of internal routes, and it is possible to solve the problems such as the limit of increasing the internal speed of the switch and the uneconomicalness due to the use of a large number of unit SWs.

Considering that the N × N ATM switch according to the present invention has the same characteristics as the output buffer type SW, the sum of the peak values of the images multiplexed on each output trunk exceeds the frame length. If it is not, the image cell is not discarded, so that the admission control can be easily performed in the case of the image.

Further, since the frame synchronization is established on the whole network based on the stop-and-go queuing, the fluctuation width can be suppressed by double the frame length, and the fluctuation characteristic can be improved. Therefore, the shaping that was required in the past becomes unnecessary, and it becomes easy to control fluctuation absorption in the terminal.

Furthermore, since the frame synchronization is established in the entire network based on Stop-and-Go Queueing, the peak value can be defined by the maximum number of cells to be sent in the frame, and the polishing of the peak value can be performed. It becomes possible to do it definitely.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows N × N A in an ATM switching system in which a frame composed of T cells based on the above-mentioned Stop-and-Go Queuing is synchronized in the entire network.
The schematic structure of a TM switch is shown. Here 3x
3 units SW are cross-connected to form a 9 × 9 ATM switch.

In the figure, 1 is an input trunk and 2 is a buffer for frame synchronization between the input trunks 1. Each of these buffers 2 is a unit SW.
4 is connected to input link 3. 5 is the unit S of the first stage
The output link of W4 and the input link of the unit SW6 of the second stage, 7 is the output link of the unit SW6 of the second stage, and the input link of the unit SW8 of the third stage, 81 is the unit SW8 of the third stage
Of the ATM switch and the output trunk of the ATM switch.

The routing tag addition device 9 and the cell output order configuration device 10 are connected to the unit SW4 of the first stage, and the cell output order is connected to the unit SW6 of the second stage and the unit SW8 of the third stage. The constituent devices 11 and 12 are connected.

Here, the routing tag adding device 9 has the priority and source address added to the cells stored in the buffers 23 and 24 in FIG. 2 and the buffers 51 and 52 in FIG. 5 in the unit SW of the first stage. ,
The routing tag representing the internal route of the cell is determined based on the destination address and the like. The cell output order configuration devices 10, 11 and 12 determine the output order in consideration of the priorities of the cells stored in the buffers in the corresponding units SW4, 6 and 8, respectively. Next, FIG. 2 shows a schematic configuration of each unit SW 4, 6, 8. In this case, the unit SW has an n × n ′ input buffer format.

In the figure, reference numeral 21 designates an input link, to which cells from the transmitting terminal are inputted in a frame unit composed of T cells.

The input selection link 21 has a buffer selection switch SW2.
2, the buffers 23 and 24, and the buffer selection SW 25 are connected. A buffer selection device 26 is connected to the buffer selection SWs 22 and 25.

The buffer selection device 26 uses the input link 21.
The cell for cell synchronization that represents a frame is recognized among the cells input to the buffer, and the buffer selection SWs 22 and 25 are switched and controlled in frame units based on the rule of Stop-and-Go Queueing. In this case, for example, one frame of cells is buffered through the buffer selection SW22.
3 is being accumulated in the buffer 3, the already selected one-frame cell is output from the buffer 24 via the buffer selection SW 25, and conversely, one-frame cell is accumulated in the buffer 24 via the buffer selection SW 22. When it is present, Stop-and-Go Queueing for outputting one frame of accumulated cells from the buffer 23 via the buffer selection SW 25 is executed.

A cell output device 27 and a cell SW28 are connected to the buffer selection SW25. Here, the cell output device 27 is the unit SW of the first stage shown in FIG.
In the case of 4, the cells are extracted from the buffer 23 or 24 according to the order determined by the cell output order configuration device 10, and in the case of the second unit SW6 in the figure, the order determined by the cell output order configuration device 11. According to buffer 23
Or the cell is extracted from 24 and the unit S in the third row in the figure is
In the case of W8, cells are extracted from the buffer 23 or 24 in the order determined by the cell output order configuration device 12. Then, this extracted cell is referred to as cell S
I am trying to transfer to W28. The cell SW 28 is adapted to perform cell switching based on the routing tag added to the cell by the routing tag adding device 9 shown in FIG.

Next, two types of procedures for determining the internal path of the cell in the ATM switch in the routing tag addition device 9 will be described. For the algorithm shown in FIG.
Buffers 23 and 2 connected to all the input links 21 of the unit SW4 of the first stage of the ATM switch shown in FIG.
A routing tag is added to the cell No. 4 according to the following rules. "For each priority,
Unit SW4 of the first stage for each output trunk number of each cell
The number of cells passing through each output link 5 is equalized. An algorithm for adding a routing tag based on such a rule is shown in FIG.

In this case, in FIG. 3, Pri is the cell priority, j ₁ is the output link number of the unit SW4 of the first stage, and j ^o Is the ATM switch output trunk number, C
(J ₁ , j ^o , Pri) is a routing tag through j ₁ with priority Pri and output trunk number j ^o.
, No represents the call number for distinguishing the call obtained from the source address and the destination address.

Now, the input link 2 of the unit SW4 of the first stage
It is determined whether the head of the cell in the frame unit comes to 1 (step S31). Here, if YES, the process proceeds to step S32, and C (j ₁ , j ^o , Pri) to 0.

When the cell arrives at the buffer 22 or 23 in step S33, the process proceeds to step S34,
Confirm the call number from the source address and destination address,
Append to cell.

Next, in step S35, a sequence number indicating the arrival order of cells is added to each cell for each call, and in the following step S36, j ^o is calculated from the destination address. Is added to the cell. Then, in step S37, the priority Pri of the cell is detected, and these results are used in the next step S37.
At 38, the output link number j ₁ ^* of the first-stage unit SW4 is calculated.

Then, in the next step S39, C (j ₁ ,
j ^o , Pri) is incremented by 1 and the process returns to step S31 to repeat the same operation as described above for the next cell.

The output order of the cells output from the buffer in the unit SW4 of the first stage is determined by the cell output order configuration device 10 so that the cells with higher priority are output before the cells with lower priority.

In this case, each cell passing through each output side link 5 of the unit SW4 of the first stage is considered so that the number of cells becomes equal in each output side link 5 by the calculation of the above step S38. There is.

For the unit SW6 of the second stage, the cell output order composing device 11 determines the output order of the cells of the buffer in the unit SW6 so that the cell having the higher priority is output first, and the output link 7 is selected. Regarding the unit switch SW8 of the third stage which is output, when the algorithm of FIG. 3 is used in the routing addition device 9, the cell having the higher priority is output first and the cell having the smaller sequence number is added to the cell. The cell output order configuration unit 12 determines the output order of the cells of the buffer in the unit SW8 so that the output trunk 81
The cell is output to.

When the algorithm shown in FIG. 4 is used in the routing adding device 9, the cell output order configuration device 12 determines the output order of the cells of the buffer in the unit SW8 so that the cells with higher priority are output first. Then, the cells are output to the output trunk 81. Note that the algorithm shown in FIG. 3 can be used as the routing tag addition algorithm described in FIG.

In this case, in FIG. 4, A (No) indicates = 1 if one or more cells having the call number No arrive in the same frame, and = 0 otherwise. L (N
o) is the output link number of the cell with the call number No, A
It becomes significant when (No) = 1. Other Pri, j ₁ ,
j ^o , C (j ₁ , j ^o , Pri) is the same as described in FIG.

In this case, steps S31 and S33 to step S37 are the same as in FIG. In step 32, C () and A () are cleared to 0. Step S
In step S41 subsequent to 37, it is determined whether A (No) = 0.

If YES is determined here, step S3
8, the output link number j ₁ ^* of the first-stage unit SW4
To calculate. Then, the result is L in step S43.
The output link number j ₁ ^* of the unit SW4 of the first stage is written in (No), A (No) = 1 is set in the next step S44, and the process proceeds to step S39 to C (j ₁ , j ^o , Pri) is incremented by 1 and the process returns to step S31, and the above operation is repeated for the next cell. Then, the process proceeds to step S41 again, and if it is judged NO at this time by judging whether A (No) = 0, the process proceeds to step S42 to set the output link number j ₁ ^* of the next cell to the content of L (No). Will come to a decision.

Further, in the above description, the unit SW is n × n ′.
Although the input buffer format is shown in FIG. 5, an n × n ′ common buffer format as shown in FIG. 5 can be used. In this case, the buffers 51 and 52 are common buffers for multiplexing and accumulating all the input links, and Stop-and-Go Queueing
Is designed to run. Then, the cell SW53
Switches the cell based on the routing tag added to the cell by the routing tag adding device 9 shown in FIG. The switch type in this case is based on the common buffer method. Others are the same as those in FIG. 2, and the same portions are denoted by the same reference numerals and the description thereof will be omitted. Even in this case, the same effect as that of the above-described embodiment can be expected. Next, another embodiment of the present invention will be described with reference to FIG.

In this case, the cell number measuring device 61 is connected to the input trunk 1 side of the above-mentioned ATM switch. The cell number measuring device 61 recognizes the frame of cells flowing through the trunk 1 and counts the number of cells in the frame for each call. Here, the call identifier is No, and the number of cells in the frame counted by the cell number measuring device 61 is N.
(No) Then, the cell number measuring device 61 is connected to the comparing device 62, and the parameter storing device 63 is connected to the comparing device 62.

The parameter storage device 62 stores the declaration parameters of the call existing in the trunk 1. Here, assuming that the peak value of the call cell flow is the number of cells n that can be output in one frame, the parameter storage device 6
In 2, the peak value is stored for each call. This is n (N
o). From this state, the comparison device 20 monitors the peak value according to the following equation. If N (No)> n (No), it is a violation If N (No) ≦ n (No), it is not a violation

Therefore, by doing this, Stop-and-Go Qu
Since the frame is synchronized throughout the network due to eueing, if the peak value is specified by the maximum number of cells to be sent in a frame, whether the terminal outputs cells in compliance with the declared parameters for the peak value. It becomes possible to definitively carry out polishing for monitoring.

[0045]

According to the present invention, in order to multiplex traffics having different qualities, if high priority and low priority are given according to the characteristics of cells, cells with higher priority are preferentially transferred. Therefore, the cell discard rate can be set to an optimum value according to the cell characteristics, and the efficiency can be improved by statistical multiplexing.

Since the N × N ATM switch in which the unit SWs are cross-connected determines the internal path for each frame according to the number of cells in the frame and performs the priority control of the cells, The internal speed is 1x and it is non-blocking without increasing the number of internal links. Therefore, the N × N ATM switch according to the present invention has the same characteristics as the output buffer type SW, which facilitates admission control. In particular, since priority control of cells is internally performed, when allocating a call such as an image with a peak value, it is possible to perform admission control while guaranteeing a discard rate of 0 with a very simple calculation.

Further, since the frame is synchronized in the entire network based on the Stop-and-Go Queueing, the fluctuation width can be suppressed to twice the frame length, and the fluctuation characteristic can be improved. This eliminates the need for shaping, which is conventionally required, and facilitates control of fluctuation absorption and the like at the terminal.

Furthermore, since the frame synchronization is established in the entire network based on the Stop-and-Go Queueing, the peak value can be defined by the maximum number of cells to be sent in the frame, and the polishing of the peak value can be determined. It is also possible to do it automatically.

[Brief description of drawings]

FIG. 1 is an N diagram of an ATM switching system according to an embodiment of the present invention.
The figure which shows the schematic structure of the ATM switch of * N.

FIG. 2 is a unit S used in the ATM switch shown in FIG.
The figure which shows the schematic structure of W.

FIG. 3 is a flowchart showing an algorithm for adding a routing tag.

FIG. 4 is a flowchart showing another algorithm for adding a routing tag.

5 is a diagram showing a schematic configuration of another unit SW used in the ATM switch shown in FIG.

FIG. 6 is a diagram showing a schematic configuration for realizing a polishing function of another embodiment of the present invention.

[Explanation of symbols]

1 ... Input trunk, 3 ... Unit SW input trunk, 2 ...
Buffers 4, 6, 8 ... Unit SW, 5 ... Unit SW6 input trunk and unit switch 4 output trunk, 7 ... Unit SW8 input trunk and unit switch 6 output trunk, 81 ... Output trunk, 9 ... Routing tag Addition device, 10, 11, 12 ... Cell output sequence configuration device, 21 ...
Input link, 22, 25 ... Buffer selection SW, 23, 2
4, 51, 52 ... Buffer, 26 ... Buffer selection device,
27 ... Cell output device, 28, 53 ... Cell SW, 61 ... Cell number measuring device, 62 ... Comparison device, 63 ... Parameter storage device.

Claims (3)

[Claims] 1. An ATM in which frames composed of T cells are synchronized in the entire network on the basis of stop-and-go queuing.
In the switching system, a buffer for accumulating input cells in frame units, a buffer selecting means for switching input / output of cells to / from the buffer in frame units based on the stop-and-go queuing rule, Based on a cell switch that performs switching and outputs a cell to a predetermined output link, a unit switch having a cell output device that transfers a cell from the buffer to the cell switch, and a priority given to the cell accumulated in the buffer An ATM switching system comprising: a cell order configuring means for determining a transfer order of cells. 2. An ATM in which a frame composed of T cells is synchronized in the entire network based on stop-and-go queuing.
In the switching system, a buffer for accumulating input cells in frame units, a buffer selecting means for switching input / output of cells to / from the buffer in frame units based on the stop-and-go queuing rule, A cell switch that performs switching and outputs a cell to a predetermined output link, an N × N multistage connection switch in which unit switches having a cell output device that transfers cells from the buffer to the cell switch are cross-connected, and this multistage connection switch A buffer for frame synchronization attached to each incoming line of the first-stage unit switch, and a priority regarding a discard rate added to cells accumulated in the buffer in the first-stage unit switch of the multi-stage connection switch, Cell arrival order, cell originator, cell destination add A cell output order configuration device that determines the output order of cells in consideration of the cell, and a priority and a cell regarding a discard rate added to the cells accumulated in the buffer in the first-stage unit switch of the multi-stage connection switch. A routing tag addition device that determines the internal route of the cell in consideration of the terminal that occurred and the destination address of the cell, and the output order of the cells accumulated in the buffer in the second-stage unit switch of the multi-stage connection switch. An ATM switching system, comprising: a cell output sequence configuration device; and a cell output sequence configuration device that determines an output sequence of cells accumulated in a buffer in a unit switch of the third stage of the multi-stage connection switch. 3. An ATM in which a frame composed of T cells is synchronized in the entire network based on stop-and-go queuing.
In the switching system, a cell number measuring means for counting the number of cells in the frame of cells input from the terminal for each call, and a declaration parameter storage means for storing the declaration parameter of the peak value declared at the time of call setup, An ATM having a polishing function having a comparing means for judging whether or not the number of cells counted by the cell number measuring means exceeds a peak value declaration parameter stored in the declaration parameter storage means. Exchange system.