JPH05129842A - Fet mixer - Google Patents

Abstract

PURPOSE:To reduce the number of power sources by effectively biasing a gate to an optimum state by impressing a potential, which is positive in respect to a ground plane, to a source terminal. CONSTITUTION:In a parallel circuit, a capacitor C3 is set to capacity sufficiently regarding as a short-circuit state to respective frequencies f1-f3, and an impedance matching circuit is composed of capacitors C1 and C2 and inductor L2 in respect to input signals. However, the gate is grounded by the inductor L1 in the matching circuit. An impedance matching circuit to a frequency converting signal is composed of capacitors C4 and C5 and inductor L2, and an impedance matching circuit to an LO signal is composed of capacitors C6 and C7. In this case, since the gate is set in the manner of a DC by the inductor L1, the gate can be validly negatively biased to the source by impressing the potential, which is positive to the ground plane, to a bias impressing terminal 3 provided at the source of the FET.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is an FET mainly used in microwave communication such as mobile communication and satellite communication.
It is about the mixer.

[0002]

2. Description of the Related Art A GaAs Schottky diode has been generally used as a frequency conversion element used in a microwave band mixer, but in recent years, a mixer using an FET as a frequency conversion element has been actively developed. This is mainly due to the fact that diode mixers always have conversion loss, while FE
Since T is an active element, conversion gain can be expected, and the isolation between the FET gate, drain, and source terminals is superior to that of a diode. Therefore, the peripheral circuit such as an impedance matching circuit can be simplified and designed. It can be said that it is possible to improve the degree of freedom.

The FET mixer is a local oscillation signal (hereinafter referred to as LO
There are several types depending on which terminal of the FET the signal is input from). As one of them, the LO signal is input from the drain of the FET, the signal is input from the gate, and the frequency conversion signal is input from the drain. There is a so-called drain injection type FET mixer that outputs.

FIG. 4 shows a conventional example of the circuit configuration of a drain injection type FET mixer. In FIG. 4, reference numeral 11 is a mixing FET, and G, D, and S represent a gate, a drain, and a source, respectively. Reference numeral 12 is a signal input terminal, 13 is a gate bias application terminal, 14 is an LO signal input terminal, and 15 is a frequency conversion signal output terminal.

The capacitors C15, C16, C17 and the inductor L5 form an impedance matching circuit for the input signal, the capacitors C18, C19 and the inductor L6 form an impedance matching circuit for the frequency converted signal, and the capacitors C20, C21 form the LO signal. It constitutes an impedance matching circuit.

In this circuit configuration, a bias is not applied between the drain and source of the FET, and the drain is in a DC open state. However, even in such a state, the mixer shows good characteristics in 1991. It has been experimentally verified as shown in C-45 of the IEICE Spring National Conference.

As a similar configuration, the source and drain may be grounded in terms of direct current. Further, in order to improve the mixer performance, Japanese Patent Laid-Open No. 63-2467.
As indicated by 64, a bias voltage is applied to the terminal 13 so that the potential between the gate and the source (the potential between the point A in FIG. 4 and the ground) is near the pinch-off voltage of the FET.

[0008]

The mixer is used as a part of a circuit which constitutes a receiver or a transmitter. However, in order to downsize and simplify the circuit, the number of power sources to be supplied to the transmitter / receiver is adjusted. Reduction is one of the important points. FE
If T is an enhancement type, it can be operated by applying a positive bias to the source at the gate. Therefore, when an FET amplifier is connected before and after the mixer, the source of the amplification FET is connected. By resistively dividing the drain bias, which is positively biased against
A desired positive bias can be applied to the gate of the mixer FET, and the number of power sources can be reduced.

However, when the FET is a depletion type, the mixer shown in the conventional example has the following problems. The gate of the mixer FET is negatively biased with respect to the source, but with the above resistance division, a negative bias cannot be applied between the gate and source of the mixer FET.

In addition, an amplifier is often arranged in the front stage or the rear stage of the mixer.
In the case of the ET amplifier, the source is grounded via the resistor R, and the gate is effectively negatively biased with respect to the source by utilizing the voltage drop at the resistor R due to the direct current flowing between the drain and the source. By the so-called self-biasing method that realizes, it is possible to eliminate the need for an external power supply applied to the gate.

However, the self-bias method cannot be applied to the mixer shown in the above conventional example because a direct current does not flow between the drain and source of the FET. Therefore, an external power supply for applying the gate bias is additionally required, and the number of power supplies increases. The present invention has been made in view of the above points, and an object thereof is to provide a novel FET mixer in which the above-mentioned conventional problems are eliminated.

[0012]

In order to solve the above problems, the present invention applies an input signal having a frequency f1 to the gate of an FET and a local oscillation signal having a frequency f2 to the drain, In a drain injection type FET mixer for outputting a frequency conversion signal having a frequency of f3 from
Is grounded by a parallel circuit of a capacitor and a resistor (including an infinite resistance), and the capacitance of the capacitor in the parallel circuit is set to a value that can be regarded as a sufficiently short-circuited state for each of the frequencies f1, f2, and f3. In addition, the gate of the FET is grounded by a conductor (including a resistor) in a direct current manner, and means for applying a positive DC potential to the ground plane is provided at the source end of the parallel circuit. It is configured to set the potential of the gate to a desired value.

[0013]

According to the above-mentioned structure, the source of the FET has frequencies f1, f2, f3 due to the capacitors in the parallel circuit.
However, since it is sufficiently short-circuited, it is equivalent to the source grounded state shown in the conventional example in terms of high frequency. However, since the gate is grounded by the conductor, the gate of the FET is negatively biased with respect to the source by the potential added to the source end of the FET with respect to DC and positive with respect to the ground plane.

When a FET amplifier is connected before and after the mixer, this potential can be obtained by resistance division from a power supply for supplying a drain bias of the FET (supplying a positive potential with respect to the ground plane). So, mixer FET
Since an independent power source for applying the gate bias is unnecessary, the number of power sources can be reduced.

Here, the resistance in the parallel circuit may be used as the potential dividing resistor, or the resistance may be divided only by an external circuit (in this case, the resistance in the parallel circuit is infinite, that is, none). May be). The optimum gate bias is obtained by setting the resistance division ratio to a desired value.
Moreover, the shared power source is not limited to the drain bias of the FET as described above, and may be any power source that supplies a positive potential to the ground plane in the system including the mixer.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. In FIG. 1, 1 is a depletion type FE for mixing.
T, and G, D, and S respectively indicate a gate, a drain, and a source. 2 is an input terminal for a signal having a frequency f1; 4 is an input terminal for an LO signal having a frequency f2; 5 is a frequency f3
It is an output terminal of the frequency conversion signal.

R1 and C3 are a resistor and a capacitor connected in parallel between the source of the FET and the ground plane, and the source is provided with a bias applying terminal 3 for applying a positive potential to the ground plane. Capacitor C3 in the parallel circuit
Is set to a capacitance that can be regarded as a sufficiently short-circuited state for each of the frequencies f1, f2, and f3. An impedance matching circuit for the input signal is formed by the capacitors C1 and C2 and the inductor L1, and the gate is grounded by the inductor L1 in the matching circuit.

Further, the capacitors C4, C5 and the inductor L2 constitute an impedance matching circuit for the frequency converted signal, and the capacitors C6, C7 constitute an impedance matching circuit for the LO signal. Since the gate is DC-grounded by the inductor L1, when a positive potential is applied to the bias applying terminal 3 with respect to the ground plane, the gate can be effectively negatively biased with respect to the source. The FET mixer can be operated with proper bias.

The potential applied to the bias applying terminal 3 is, for example, as shown in FIG. 2, the resistance R from the positive power source P having a positive potential with respect to the ground plane in the system including the mixer.
Since it can be easily obtained by resistance division by 1 and Ra, it is not necessary to add a new power source to the mixer, and the number of power sources can be reduced. In FIG. 2, the parts denoted by the same reference numerals as those in FIG. 1 have the same functions,
The description of the operation is omitted. The present invention is particularly effective in a system including a mixer when there is only a power supply that supplies a positive potential to the ground plane.

FIG. 3 shows a second embodiment of the present invention. In FIG. 3, the drain side and source side circuits of the FET are exactly the same as those in FIG.
In FIG. 3, the impedance matching circuit for the input signal is configured by the capacitors C8, C9, C10, the inductor L3 and the resistor R2, but the point that the gate is grounded by the resistor R2 instead of the conductor like the inductor is shown in FIG. Different from

Since the first purpose of the resistor R2 is to make the gate at the same potential as the ground plane, even if the resistor R2 has a large resistance value that hardly affects the characteristics of the impedance matching circuit with respect to the input signal. Good. That is, the resistance R2
Does not have to be a part of the impedance matching circuit for the input signal, so the degree of freedom in circuit design is higher than in the first embodiment.

[0022]

Since the present invention is constructed as described above,
It is possible to provide an FET mixer that does not require a dedicated power source, and it is possible to reduce the number of power sources in a system using the FET mixer.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

FIG. 3 is a circuit diagram of still another embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional example.

[Explanation of symbols]

 1 Mixing FET C3 Capacitor R1, R2 Resistor L1 Inductor P Positive power supply

Claims (1)

[Claims] 1. A drain injection type FET in which an input signal of frequency f1 is applied to the gate of the FET, a local oscillation signal of frequency f2 is applied to the drain, and a frequency conversion signal of frequency f3 is output from the drain. In the mixer, the FET is configured as a depletion type, and the FET is
Is grounded by a parallel circuit of a capacitor and a resistance (including an infinite resistance), and the capacitance of the capacitor in the parallel circuit is set to a value that can be regarded as a sufficiently short-circuited state for each of the above frequencies f1, f2, and f3. In addition, the gate of the FET is grounded by a conductor (including a resistor) in a direct current manner, and means for applying a positive DC potential to the ground plane is provided at the source end of the parallel circuit. An FET mixer characterized in that the potential of the gate is set to a desired value.