JPH05129272A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a low price semiconductor device and a method for the manufacture thereof by lessening a heat treatment process and reducing photolithographic cycles. CONSTITUTION:A semiconductor device obtained by forming a plurality of elements on a semiconductor substrate which is obtained by forming a buried layer 120 of second conductivity type on a semiconductor 101 of first conductivity type having a face orientation (100) face, and growing an epitaxial layer 102 of first conductivity type thereon. The semiconductor device is so structured that the elements are insulated and isolated through anisotropic etching using alkali solution. In addition the buried layer is electrically floating. The insulation and isolation of the elements are accomplished by simultaneously etching the epitaxial layer and the buried layer in alkali solution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing apparatus. Examples of the semiconductor device of the present invention include a recording head semiconductor device in which an electrothermal converting element and a recording functional element are formed on a substrate, and particularly, a copying machine, a facsimile, a word processor, an output printer of a host computer. It is preferably applied to an inkjet recording device used in a video output printer or the like.

[0002]

2. Description of the Related Art Conventionally, a recording head has a structure in which an electrothermal conversion element array is formed on a single crystal silicon substrate, and a driving circuit for the electrothermal conversion element is provided outside a silicon substrate for driving an electrothermal conversion element such as a transistor array. The functional element is arranged, and the electrical conversion element and the transistor array are connected by a flexible cable or wire bonding.

For the purpose of simplifying the structure of the head structure described above, reducing defects occurring in the manufacturing process, and making the characteristics of each element uniform and improving reproducibility, Japanese Patent Application Laid-Open No. 57-72867. As suggested in
2. Description of the Related Art Ink jet recording apparatuses having a recording head in which an electrothermal conversion element and a functional element are provided on the same substrate are known.
FIG. 6 is a sectional view showing a part of the recording head substrate having the above-mentioned structure. 601 is a semiconductor substrate made of single crystal silicon, 602 is an n-type semiconductor epitaxial region, 603 is a high impurity concentration n-type semiconductor ohmic contact region, 604 is a p-type semiconductor base region, and 6
Reference numeral 05 denotes a high impurity concentration n-type semiconductor emitter region,
These form the bipolar transistor 620. 606 is a silicon oxide layer as a heat storage layer and an interlayer insulating layer, 607 is a heating resistance layer, and 608 is aluminum (A
The wiring electrode 1609 and the silicon oxide layer 609 as a protective layer form the base 630 for the recording head. Here, 640 is the heat generating portion. This base 630
A top plate and a liquid path are formed on the top to form a recording head.

Although the structure described above is excellent, the high-speed driving, energy saving, high integration, low cost, and high cost which are strongly demanded for recording devices in recent years are required. There is still room for improvement to complement credibility.

First of all, a recording head having high reliability must be provided at a low price. For that purpose, it is important to reduce the number of heat treatment steps in manufacturing the functional element for driving the electrothermal converting element.

Particularly, in order to form the p-type diffusion layer 612 forming the junction isolation region and the n-type diffusion layer 611 forming a part of the collector region, heat treatment at high temperature for a long time is required. As an example, when the thickness of the epitaxial layer 602 is 16 μm, the driving condition for the p-type diffusion layer 612 in the isolation region is 1200 ° C. for 6 hours, and the driving condition for the n-type diffusion layer 611 in the collector region is 1150 ° C. for 3 hours. is there. Such a long heat treatment process causes a rise in manufacturing cost.

In the photolithography process, the n-type buried layer 6 is also used.
The p type buried layer 613, the p type buried layer 613, the p type diffusion layer 612, and the n type diffusion layer 611 are required four times in total.

In view of the above situation, it is an object of the present invention to provide a low-priced semiconductor device and a manufacturing method thereof by reducing the number of lengthy heat treatment steps and reducing the number of photolithography steps.

[0008]

The first gist of the present invention is as follows.
A semiconductor device in which a second-conductivity-type buried layer is formed on a first-conductivity-type semiconductor having a plane orientation (100) plane, and a plurality of elements are formed on a semiconductor substrate on which a first-conductivity-type epitaxial layer is grown. In the semiconductor device, the element has a structure in which the element is insulated and separated by anisotropic etching of an alkaline solution, and the buried layer is in an electrically floating state.

The second gist is that a semiconductor layer is formed by forming a buried layer of the second conductivity type on a semiconductor of the first conductivity type having a plane orientation (100) plane, and then growing an epitaxial layer of the first conductivity type. And further forming a plurality of elements on the semiconductor substrate, wherein the epitaxial layer and the buried layer are simultaneously etched with an alkaline solution to isolate the elements. It exists in a method of manufacturing a semiconductor device.

[0010]

1 is a sectional view schematically showing an example of the semiconductor device of the present invention.

Reference numeral 101 denotes a p-type conductivity type semiconductor substrate, for example.
Reference numeral 102 is a p-type epitaxial layer having the same conductivity type as the semiconductor substrate, and 105 is an n-type high-concentration diffusion layer. Reference numeral 106 is an interlayer insulating film made of, for example, a silicon nitride film, 107 is a resistor such as hafnium boride (HfBr), and 108.
Is a low resistance wiring made of aluminum or the like, and 109 is an interlayer insulating film made of, for example, sputtered SiO ₂ . 114
Is a high-concentration diffusion layer for obtaining good contact characteristics with the epitaxial layer 102, and its conductivity type is p-type in the figure. Denoted at 115 is a film insulating film such as silicon thermal oxidation, and 12
Reference numeral 0 is an n-type buried layer, 140 is a cavitation prevention film, and tantalum (Ta) or the like is used as a material.

Regarding the conductivity type, 101, 10
A combination of 2, 105, 114, and 120 having opposite conductivity types may be used.

Considering the correspondence between the structure of FIG. 1 and the conventional example of FIG. 6, it is as follows. The n-type diffusion layer 105 in FIG. 1 corresponds to the emitter region 605 in FIG. Further, the region surrounded by the V-shaped groove in the p-type epitaxial layer 102 of FIG. 1 corresponds to the base region 604 of FIG. Further, the region surrounded by the V-shaped groove in the buried layer 120 of FIG. 1 is 60 in FIG.
It corresponds to the collector regions of 3, 611 and 620. Further, as a method of insulating each transistor, FIG. 1 adopts a method of insulating by using a V-shaped groove that penetrates through the epitaxial layer 102 and reaches a part of the substrate 101, while a conventional example is shown. The insulation method of 6 uses the pn separation method. Hereinafter, the V-shaped insulation method as shown in FIG. 1 is referred to as a general name, air isolation.

In the structure of the bipolar transistor, the diode can be formed by short-circuiting the base and the collector. It is also possible to make the collector electrically floating and form a diode between the emitter and the base. The biggest difference between the present invention and the conventional example in the operation of the device is that the collector region of the present invention is in a floating state, whereas the conventional example is a short circuit state due to the metal wiring between the base region and the collector region. It is that you are. FIG. 2 shows a circuit showing a wiring state of the transistors of FIGS. 1 and 6.

As compared with the base-collector short-circuit type shown in FIG. 2A, the disadvantage of the collector floating type shown in FIG. 2B is that it is more susceptible to the parasitic resistance of the base. For example, the influence of parasitic resistance can be eliminated by making the impurity concentration of the base region have a distribution in the depth direction.

As a result, according to the present invention, as compared with the conventional example, (1) the deep diffusion layers 611 and 612 shown in FIG. 6 are obtained.
Can be omitted, and (2) the photolithography process,
In FIG. 6, the p-type buried layer 613 and the n-type buried layer 62 are shown.
0, p-type diffusion 612, and n-type diffusion layer 611, which had to be patterned four times, can be reduced to one patterning for forming the separation layer.

[0017]

Embodiments of the present invention will be described in detail below with reference to the drawings.

(Embodiment 1) A method of manufacturing a semiconductor device of the present invention will be described with reference to FIG.

A p-type silicon substrate 30 having a plane orientation (100)
1 was implanted with arsenic (As) at a dose of 5 × 10 ¹⁵ dose / cm ² by an ion implantation method, and heat treatment was performed at 1100 ° C. for 120 minutes to form an n-type buried layer 320.

Next, a p-type epitaxial layer 302 was deposited. It is necessary to devise a method for depositing this epitaxial layer. That is, as shown in FIG. 4, in the diode having the structure in which the base and the collector are short-circuited in the conventional example, the main passage of charges is shown by a solid line passing through the n-type buried layer,
The current flowing in the base is negligible. Figure 4
(A) Therefore, the forward parasitic resistance of the diode is almost n.
It depends on the resistance value of the mold burying layer. However, when the collector is floated, as shown in FIG. 4B, the only current flowing across the base is that the forward parasitic resistance of the diode is determined by the parasitic resistance of the base.
Therefore, the p-type epitaxial layer 302 shown in FIG. 3 must be suppressed to a sheet resistance of about 10 to 30 Ω / □, but if the acceptor concentration is simply increased, the reverse breakdown voltage between the emitter and the base decreases. I will invite you.
Therefore, for the p-type epitaxial growth, the first 5 μm deposition is made a high concentration with an acceptor concentration of 10 ¹⁹ / cm ³ , and then an epitaxial layer 8 μm is deposited with a concentration of about 2 × 10 ¹⁶ / cm ^3. did. Thus, the epitaxial layer 302 having a sheet resistance of 20Ω / □ and a thin surface acceptor concentration was formed. The source gas for epitaxial growth is trichlorosilane (SiHCl ₃ )
Was used as the dopant, diborane (B ₂ H ₆ ) was used, and the deposition temperature was 1060 ° C. After the epitaxial growth, a 3000 Å silicon thermal oxide film 315 was formed (see FIG. 3).
(A)).

Next, a resist pattern having a width of 30 μm was formed at a predetermined place by a photolithography process, and the silicon thermal oxide film 315 was etched with a buffer hydrofluoric acid solution using the resist as a mask. After removing the resist, ethylenediamine / catechol / water (138m
1: 25 g: 67 ml) Substrates 301 to 34 in the mixed solution
1 was soaked. The feature of this solution is that it has different etching rate depending on the plane orientation of the silicon crystal,
The etching rate is 50 μm / hr in the (100) direction,
It has 3 μm / hr in the (111) direction and a selection ratio of 16: 1 or more. Therefore, when a silicon substrate having a (100) plane orientation is put in a solution, a groove is formed in a V shape (reference J. Electrochem. Soc. July 1967 issue).
P.965〜970; A Water Amine Complexing Agent Syste
m). The V-shaped groove is formed with a frontage of 30 μm and a depth of about 21 μm. The etching time was about 25 minutes at an etching temperature of 110 ° C. If the thickness of the epitaxial layer 302 is 13 μm and the thickness of the buried layer 320 is 4 μm, V
The groove penetrates to the substrate side by about 4 μm ((b) of FIG. 3).

Next, the silicon oxide film 341 for the mask is removed by a hydrofluoric acid solution, and thermal oxidation is performed at 1050 ° C. for 300 minutes to form a silicon thermal oxide film 315 of 1.5 μm ((c) of FIG. 3). ).

Next, a hole is made in the place where the emitter is to be formed by a photolithography technique, and an n-type diffusion layer 305 is formed by diffusion from phosphor glass. Phosphorus glass was deposited with phosphorus oxychloride (POCl ₃ ), and heat treatment for diffusion was performed in a steam atmosphere at 950 ° C. for 30 minutes ((d) of FIG. 3).

Further, a hole was made in the base region at a position to be contacted by a photolithography technique, and a high concentration p-type diffusion layer 314 was formed by an ion implantation method. The dose type of ion implantation is boron, and the dose amount is 5 ×.
10 ¹⁴ ions / cm ² , accelerating voltage is 70 KeV.
Then, heat treatment was performed at 950 ° C. for 10 minutes in a steam atmosphere to activate the diffusion layer ((e) of FIG. 3).

Then, a contact hole is formed on the emitter diffusion layer 305 and the base contact diffusion layer 314 by a photolithography technique, and 5000 is formed on the entire surface.
Å Aluminum was deposited by sputtering and patterned into a predetermined electrode shape 321 to complete a bipolar transistor in which the collector was in a floating state (Fig. 3).
(F)).

In the manufacturing method of this embodiment, compared with the conventional example,
A long diffusion process for insulation and isolation is not necessary, and the photolithography process required for these is also unnecessary.
We were able to significantly reduce manufacturing costs.

After that, the recording head can be manufactured by forming the heater portion by the method described in, for example, Japanese Patent Laid-Open No. 57-72867.

(Embodiment 2) In the first embodiment, when the air / isolation region is formed, instead of using the ethylenediamine / catechol / water mixed solution, potassium hydroxide / isopropyl alcohol / water mixed solution is used. V
A V-shaped groove was formed. At this time, the mixing ratio of the liquid is 30 g of potassium hydroxide, 30 ml of isopropyl alcohol, and 1 part of water.
It is 00 ml.

(Embodiment 3) According to the manufacturing method of the present invention, it is possible to manufacture a semiconductor device having a structure short-circuited with the base regions 102 and 114 without increasing the number of masks, without making the buried layer 120 in a floating state. it can. In this example,
The method will be described with reference to FIG. In the same manner as in Example 1, V for air isolation having a depth of 21 μm
When forming the V-shaped groove, another shallow V-shaped groove was formed on the inner side of the groove (FIG. 5A). At this time, set the groove width to 18μ
The groove depth was 13 μm. By adopting anisotropic etching, a groove having a depth of 21 μm and a groove having a depth of 13 μm can be formed at the same time only by changing the groove width during the photolithography process. Next, after forming an oxide film 515 having a thickness of 1.5 μm, the oxide film in the emitter region 505 and the shallow groove region 522 of 13 μm is removed, and an n-type impurity is diffused. As a result, the diffusion layer 522 connected to the buried layer 502 is formed at the same time as the emitter region 505 (FIG. 5B).

After forming a higher concentration p-type diffusion layer 514, contact holes were opened in the emitter and base-collector regions, aluminum electrodes were formed, and a diode in which the buried layer 520 and the base were short-circuited was produced (FIG. 5
(C)).

The mask process of this embodiment photolithography is the same as that of the first embodiment, and it is possible to bring the buried layer into a floating state and to set it to the same potential as the base with the same number of masks.

As described above, by adopting anisotropic etching using an alkaline solution, it is possible to reduce the lengthy heat treatment process and further reduce the number of photolithography processes, resulting in low cost. It becomes possible to provide a semiconductor device.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing an example of a semiconductor device of the present invention.

FIG. 2 is a schematic diagram showing an equivalent circuit of an element.

FIG. 3 is a sectional view schematically showing a method for manufacturing a semiconductor device of the present invention.

FIG. 4 is a schematic diagram showing a passage of an electron flow.

FIG. 5 is a sectional view schematically showing another example of the method for manufacturing a semiconductor device of the present invention.

FIG. 6 is a sectional view schematically showing a conventional semiconductor device.

[Explanation of symbols]

101, 301, 501, 601 Substrate (silicon substrate), 102, 302, 502 Silicon epitaxial layer, 105, 305, 505, 605 N-type diffusion layer forming an emitter, 106, 606 Silicon oxide or other interlayer insulating film, 107 , 607 heating resistor such as hamnium boride, 108, 321, 521, 608 wiring such as aluminum, 109, 609 interlayer insulating film such as silicon oxide, 114, 314, 514, 614 p-type diffusion layer for base contact, 115, 315, 515, 615 Silicon thermal oxide film, 120, 320, 520, 620 n-type buried layer, 140 cavitation prevention film, 522 n-type diffusion layer, 602 n-type silicon epitaxial layer, 603 n-type diffusion layer, 604 p-type diffusion layer, 611 n-type diffusion layer, 61 p-type diffusion layer, 613 a p-type buried layer.

Claims (6)

[Claims] 1. A plurality of devices are formed on a semiconductor substrate in which a buried layer of the second conductivity type is formed on a semiconductor of the first conductivity type having a plane orientation (100) plane, and an epitaxial layer of the first conductivity type is further grown. The semiconductor device having the structure according to claim 1, wherein the element has a structure in which the element is insulated and separated by anisotropic etching of an alkaline solution, and the buried layer is in an electrically floating state. 2. The semiconductor device according to claim 1, wherein the alkaline solution is a mixed solution of ethylenediamine / catechol / water. 3. The semiconductor device according to claim 1, wherein the alkaline solution is a solution containing potassium hydroxide (KOH). 4. A second-conductivity-type buried layer is formed on a first-conductivity-type semiconductor having a plane orientation (100) plane, and then a first-conductivity buried layer is formed.
A method of manufacturing a semiconductor device, wherein a semiconductor substrate is produced by growing a conductive type epitaxial layer, and a plurality of elements are further formed on the semiconductor substrate, wherein the epitaxial layer and the buried layer are simultaneously etched with an alkaline solution. A method for manufacturing a semiconductor device, characterized in that an element is isolated. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the alkaline solution is a mixed solution of ethylenediamine / catechol / water. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the alkaline solution is a solution containing potassium hydroxide (KOH).