JPH05128861A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent the erroneous transfer due to the through current between the power and the ground and the difference potential destruction of a bit line by connecting the output contact of a data register with the bit line through a clocked inverter especially, at the time of data transfer between the data register and a memory cell. CONSTITUTION:When data are transferred from a memory cell (c) to a data register part (a) and a control signal phi2 and inversion phi2 are made into each power ground potential, an output contact DO is connected with a bit line inversion BL by a clocked inverter 9 and inverted from a ground potential to a power potential. In the reverse case, when a control signal phi1 becomes the power potential, an output contact inversion DO is connected through the inverter 8 and an NMOS transistor 1 to a bit line BL. The line BL becomes the power potential by the inverter 8 and the inversion BL subsequently becomes the ground potential by the activation of a sense amplifying part (d). Thus, the erroneous transfer due to the through current between the power and the ground and the difference potential destruction of the bit line is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory having a data transfer function between a memory cell represented by a dynamic memory and a data register.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 3, a semiconductor memory device of this type has a pair of bit lines BL and BL (inversion value) connected to a sense amplifier section d and a P-channel type MOS transistor (hereinafter 3, 4 and N-channel type MOS transistor (hereinafter referred to as NMOST)
It is composed of a data register section a composed of 5, 5 and 6.

In addition, the bit line BL has a capacitance 10 as an NMO.
It is connected to the output contacts DO and DO (inverted value) of the data register section a via the memory cell section c, the sense amplifier section d, and the data transfer section b which are connected via ST7. The data transfer unit b has N-channel MOS transistors 1 and 2.

A signal φ1 is applied to the gates of the transistors 1 and 2.
Is applied, and the signal WL is applied to the gate of the transistor 7 in the memory cell section c.

The operation of the circuit of FIG. 3 will be described with reference to the timing chart of FIG.

FIG. 4A shows the waveforms at each part in FIG. 3 in the case of the transfer from the memory cell to the data register. At time T1, the activation of the sense amplifier part d is started, and in the period T2, Interference occurs between the data register and the sense amplifier. Further, the potential difference between the signals BL and BL (inversion value) is ΔV.

In FIG. 4B, the waveforms of the respective parts of FIG. 3 in the case of the transfer from the data register to the memory cell are shown, and the activation of the sense amplifier part d starts at the time point T1 and the data starts at the period T2. Interference occurs between the register and the sense amplifier.

Data transfer between the memory cell section c and the data register section a is performed by the control signal φ1 of the transfer transistor.
Becomes the power supply potential, the NMOS T1 and NMOST2 shown in FIG. When the control signal φ1 becomes the ground potential, the transistors 1 and 2 become non-conductive and data transfer becomes impossible.

First, the case of transferring data from the memory cell c to the data register section a will be described with reference to FIGS. 3 and 4A. The control signal WL is activated in advance and the capacitance 10
Is transmitted to the bit line through the NMOST7 and amplified by the sense amplifier d.

Here, before starting data transfer, the bit line BL
And the output contact DO (inverted value) of the data register section a is
The power supply potential is used, and the bit line BL (inverted value) and the output contact DO of the data register are ground potential.

When the control signal φ1 becomes the power supply potential, the sense amplifier d supplies electric charge to the output contact DO of the data register section a, so that the sense amplifier d, the transfer transistors NMOST1 and 2, and the data register section a are connected. The potentials of the output contacts DO, DO (inverted value) of the data register are determined by the capacity ratio of the constituent transistors. Therefore, in order to transfer the data correctly, the drive capabilities of the sense amplifier d and the transfer transistors NMOST1 and NMOST2 are set to be large enough to invert the data register section a.

When the control signal φ1 becomes the ground potential,
The output contact DO of the data register section a is set to the power supply potential, and DO
The (inverted value) is brought to the ground potential, and the data holding operation is performed.

Next, the case of transferring data from the data register section a to the memory cell section c will be described with reference to FIGS. 3 and 4B. Input / output contact DO of data register a
(Inverted value) is power supply potential, DO is ground potential, control signal WL
When is activated, the bit line BL is
If the control signal φ1 becomes the power supply potential, the output contact DO of the data register and the bit line BL are NMOS.
DO (inverted value) and BL (inverted value) are NMO through T1
Each is connected via ST2.

In the case of the 1/2 VCC precharge system, the bit line is kept at the 1/2 VCC level until it is connected to the input / output contact of the data register. Therefore, when the control signal φ1 is activated, the potential of the contact of the data register changes to a level determined by the capacitance division with the bit line. Since the capacity of the data register output contact is usually smaller than the bit line capacity, the data register output contact DO.
The DO (inverted value) level fluctuates near the 1/2 VCC level.

On the other hand, the bit line BL starts transition to the ground potential by the NMOS T5, and the BL (inverted value) starts transition to the power supply potential by the PMOS T4. Then, the control signal φ1
When the sense amplifier d is activated after a certain delay time after activation of, the charge is supplied by the sense amplifier d and BL
The (inverted value) is set to the power supply potential, and the BL is set to the ground potential.

[0016]

The conventional semiconductor memory device described above has a gap between the output contact of the data register and the bit line during the transfer from the data register to the bit line and the transfer from the bit line to the data register. Since interference occurs, there is a drawback that an ON-ON current easily flows between the power supply and the ground via the transistor forming the data register during transfer, and the difference potential of the bit line amplified by the sense amplifier d is easily destroyed. It was

The object of the present invention is to solve the above-mentioned drawbacks and to provide ON-
An object of the present invention is to provide a semiconductor memory device in which an ON current does not flow.

[0018]

According to the structure of the present invention, in a semiconductor memory device in which a plurality of bit line pairs are provided and data registers are arranged according to the bit line pairs, the output contact of the data register is input. No. 1 inverter, a transistor which is controlled by a first control signal and connects the output of the first inverter to one of the bit line pairs, and the other of the bit line pairs is input to generate a second control signal. And a second inverter controlled by a signal having a reverse phase of this signal and outputting to the input contact of the data register.

[0019]

1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention.

In FIG. 1, the semiconductor memory device of this embodiment is configured to include a sense amplifier section d, a data transfer section b, a data register section a, and a memory cell section c, as in the conventional example. There is.

The part of this embodiment different from the conventional example is a data transfer part b. This data transfer unit b has a control signal φ1.
Is controlled by the output contact D of the data register section a.
A first inverter 8 that receives O (inverted value) as an input, and a first N that controls connection between this output section and one bit line BL
Has a MOS transistor 1, a second control signal φ2,
The bit line B is controlled by the opposite phase signal φ2 of φ2.
A second clocked inverter 9 that receives L (inverted value) as an input and outputs it to the input contact DO of the data register section a is arranged.

In the above configuration, the operation at the time of data transfer will be described with reference to the waveforms of (A) and (B) of FIG.

In FIG. 2A, the waveform of each part in FIG. 1 when transferring from the memory cell to the data register is shown. In FIG. 2B, when transferring from the data register to the memory cell. The waveforms of the respective parts of FIG. 1 are shown, and the sense amplifier activation starts at time T1.

First, when transferring from the memory cell c shown in FIG. 2A to the data register section a, the control signals φ1 and φ
2 is the ground potential and φ2 (inverted value) is the power source potential, and the data in the memory cell section c is previously amplified by the sense amplifier section d and transmitted to the bit lines BL, BL (inverted value).

Here, it is assumed that the bit line BL (inverted value) before the start of transfer and the data register output contact DO are at the ground potential, and the bit line BL and the data register output contact DO (inverted value) are at the power supply potential.

Control signal φ2 is power supply potential, φ2 (inverted value)
To the ground potential, the output contact D of the data register section a
O and bit line BL (inverted value) are clocked inverter 9
The output contact DO of the data register part a is inverted from the ground potential to the power supply potential by the charge supply of the clocked inverter 9.

Next, transfer from the data register section a shown in FIG. 2B to the memory cell section c will be described. The control signals φ1 and φ2 are ground potentials, φ2 (inverted value) is the power source potential, the output contact DO (inverted value) of the data register section a is the ground potential, and the bit line BL (inverted value) when the signal WL is active.
Is higher than BL by a potential difference ΔV. When the control signal φ1 becomes the power supply potential, the output contact DO of the data register section a
The (inverted value) is connected to the bit line BL via the inverter 8 and the NMOST1. At this time, the sense amplifier section d
Is in the inactive state, the bit line BL transitions from the 1/2 VCC potential to the power supply potential by the charge supply by the inverter 8 as shown in the timing chart of FIG.
L (inversion value) maintains 1/2 VCC. After that, the bit line BL is set to the power supply potential by the activation of the sense amplifier section d.
BL (inverted value) is fixed to the ground potential.

As described above, in the semiconductor memory device of this embodiment, in the semiconductor memory device in which the same number of data registers as the bit line pairs are arranged, the first inverter for inputting the output contact of the data register and the first inverter. A first transfer gate that connects the output of the inverter and one of the bit lines under the control of a control signal, and the other of the bit lines is input to input a second control signal and the opposite phase of this signal. And a first clocked inverter which outputs the signal to an input contact of the data register under the control of the signal.

[0029]

As described above, according to the present invention, at the time of data transfer from the data register to the memory cell and data transfer from the memory cell to the data register, the output contact of the data register is particularly connected to the clocked inverter. By connecting via the bit line via the bit line, the interference between the input / output contact of the data register and the bit line is cut off, and the ON-ON current flowing through the data register during data transfer and the destruction of the bit line level are eliminated. ..

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory device according to an embodiment of the present invention.

2A and 2B are timing charts showing the respective operations of FIG.

FIG. 3 is a circuit diagram of a conventional semiconductor memory device.

4A and 4B are timing charts showing the respective operations of FIG.

[Explanation of symbols]

 1, 5, 6, 7 N-channel type MOS transistor 3,4 P-channel type MOS transistor φ1, φ2, φ2 (inverted value), WL control signal 8 inverter 9 clocked inverter 10 capacity a data register section b data transfer section c Memory cell part d Sense amplifier part T1 time point T2 period

Claims (2)

[Claims] 1. A semiconductor memory device having a plurality of bit line pairs, and a data register arranged according to the bit line pair, wherein a first inverter for inputting an output contact of the data register and a first control signal are provided. Controlled by the transistor for connecting the output of the first inverter and one of the bit line pairs, and the other of the bit line pairs for inputting a second control signal and a signal of opposite phase to this signal. Second controlled output to the input contact of the data register
A semiconductor memory device comprising: an inverter. 2. The transistor is an N-channel type, and the second inverter is a clocked inverter.
A semiconductor memory device as described.