JPH05128328A - Ic card - Google Patents

Abstract

PURPOSE:To provide an inexpensive IC card having a small number of elements where data is read out at a high speed regardless of a large capacity by mounting a large-capacity nonvolatile memory and a memory which has a small capacity but a high read speed. CONSTITUTION:An address bus 4a through which address data is supplied, a chip enable signal line 10 where the output of a data transfer circuit 8 whose input end a card enable signal line 6 and a write enable signal line 7 of a GRAM 2 are connected to is the signal source, and an output enable signal line 25 where the card enable signal is the signal source are connected to a mask ROM 1. A part of data related to present read out of data stored in the large-capacity nonvolatile mask ROM 1 is transferred to the small-capacity GRAM 2 having a high read speed, and the SRAN 2 is activated to read out data from a buffer 3 to the outside of the card at a high speed at the time of reading out data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card having a large-capacity non-volatile memory and a rewritable memory having a smaller capacity and a higher data reading speed than the non-volatile memory.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing a circuit configuration of a conventional SRAM card. 2 in the figure is an IC16 having a capacity of 1 Mb
Each SRAM 2 IC is a chip select signal line 21, address data (A ₀ ~
An address bus 4 for supplying A ₁₆ ), an output enable signal line 5 and a write enable signal line 7 are connected.

The chip select signal line 21 is connected to the address decoder 20, and the address decoder 20 is connected to the upper 4-bit address line 19 and the card enable signal line 6.

The SRAM 2 is connected via an internal data bus 12 to a buffer 3 which is a data input / output area to the outside of the card, and an external data bus 13 for transmitting data to the outside of the card is connected to the buffer 3.

Further, an external power supply line 14 is connected to the external power supply, and the external power supply line 14 is connected to a power supply switching circuit 15 to which a backup battery 18 for storing data of the SRAM 2 is connected via a diode 16 and a resistor 17. Connected and power switching circuit
Reference numeral 15 switches the internal power supply between the external power supply and the backup battery 18 according to the voltage supplied from the outside.

A data read operation of the conventional SRAM card having the above configuration will be described. The address decoder 20 supplied with the voltage of 5V through the external power supply line 14 and supplied with the card enable signal outputs the upper 4 bits of the address data.
Any of the SRAM2 by decoding the bit
IC is activated.

An address is set by the address data supplied via the address bus 4, and the data stored in the set address of the IC which is in the output state by the supply of the output enable signal is transferred from the internal bus 12 and the buffer 3. It is read out via the external bus 13.

Since the SRAM 2 is a volatile memory, the internal power supply is switched from the external power supply to the battery 18 by the power supply switching circuit 15 so that the data is not erased when the power supply from the external power supply is stopped.

[0009]

By the way, the read speed of data is higher in RAM than in ROM and faster in SRAM than in DRAM. Therefore, if the SRAM is used, the data reading speed will be high, but since the SRAM requires many constituent elements such as attached circuits and parts, it can be obtained even if the circuit integration degree is increased in a limited card area. Limited memory capacity.

The present invention has been made in order to solve such a problem, and a large-capacity non-volatile memory and a memory having a smaller reading capacity but a higher reading speed can be mounted. The purpose of the present invention is to provide an inexpensive IC card that has a high reading speed and a high capacity.

[0011]

An IC card according to the present invention has a large-capacity non-volatile memory and a second memory having a smaller capacity and a higher reading speed than the non-volatile memory mounted therein, All the data is stored in the non-volatile memory, while the data to be read is stored in the non-volatile memory
After the data is transferred to the memory, the data is output from the second memory to the outside of the card.

[0012]

The IC card according to the present invention realizes a large capacity by storing all the data in the non-volatile memory which can be constituted by a relatively small number of elements and has a higher reading speed than the non-volatile memory for the data expected to be read. When the data is read out, the data is output from the second memory to the outside of the card and the data is read out faster than the nonvolatile memory.

[0013]

The present invention will be described below with reference to the drawings showing the embodiments thereof. FIG. 2 is a block diagram showing the circuit configuration of the IC card according to the present invention. In the figure, 1 is a 16 Mb mask ROM, and the mask ROM 1 has address data (A ₀ ~
A ₂₀ ) for supplying the address bus 4a, the card enable signal line 6 and the write enable signal line 7 of the SRAM 2 described later.
Is connected to its input terminal, the chip enable signal line 10 having an output of the data transfer circuit 8 as a signal source and the output enable signal line having a card enable signal as a signal source
25 are connected.

The data terminal (DATA) of the mask ROM 1 is connected to the data terminal (DAT) of the SRAM 2 of 1 Mb via the internal data bus 12.
Address bus 4b connected to A) and supplying address data (A _{0 to} A ₁₆ ) excluding the upper 4 bits to SRAM 2, chip enable signal line 26 that uses the output enable signal of mask ROM 1 as a signal source, output The enable signal line 5 and the write enable signal line 7 are connected.

The data terminal (DATA) of the SRAM 2 is connected via an internal data bus 12 to a buffer 3 which is a data input / output area to the outside of the card. Further, the buffer 3 outputs the output of the enable circuit 9 as a signal source. An external data bus 13 for transmitting data to the outside of the card is connected to the buffer 3.

In the enable circuit 9, the output enable signal line 25 of the mask ROM 1, the output enable signal line 5 and the write enable signal line 7 of the SRAM 2 are connected to the input end, and the output end is the output enable signal line 11
Is connected to the buffer 3 described above.

FIG. 3 is a conceptual diagram of data transfer from the mask ROM 1 to the SRAM 2 which is performed prior to data reading in the IC card having the above structure. The operation of data transfer will be described below.

In the following description, the number in parentheses after the signal indicates the number given to the signal line transmitting the signal.

For example, the mask ROM 1 address "120000"
If "H ~ 13FFFFH" is the memory area to be read out for the time being, specify the address "120000H" of the mask ROM 1 via the address bus 4a, and specify the card enable signal (6).
Is set to "L" and the write enable signal (7) is set to "L" to set the mask ROM 1 to the data output state and the SRAM 2 to the data write state to set the mask ROM 1 address "1200".
The data of 00H "is transferred to the address" 0H "of the SRAM 2 via the internal data bus 12.

The address of the mask ROM 1 is sequentially incremented and the same data transfer is repeated. The data of the address "120000H to 13FFFFH" of the mask ROM 1 is stored in the address "0H to 1FFFFH" of the SRAM 2 and the address of the mask ROM 1 is stored. And the address of SRAM 2 are stored in association with each other.

During data transfer, the three inputs of the enable circuit 9 are the output enable signal (5) "H", the card enable signal (6) "L" and the write enable signal (7) "L". It becomes "H", the buffer 3 is inactive and cannot be read.

Next, the data read operation of the IC card according to the present invention will be described. When the card enable signal (6) is set to "L" and the write enable signal (7) is set to "H", the output of the data transfer circuit 8 becomes "H", so that the chip select signal (10) of the mask ROM 1 becomes "H". "And the mask ROM 1 becomes inactive.

On the other hand, the output enable signal (5)
When "L" is set to "L", the SRAM 2 becomes a read state, and the three inputs of the enable circuit 9 are the output enable signal (5) "L" and the card enable signal (6).
Since it is "L" and the write enable signal (7) is "H", the output becomes "L", the buffer 3 is activated and the SRAM is activated.
High-speed reading from 2 is possible.

Next, when the addresses "120000H to 13FFFFH" of the mask ROM 1 are set as data read addresses, the data stored in the addresses "0H to 1FFFFH" of the SRAM 2 are read out from the IC card at high speed.

Further, when the data in the mask ROM 1 other than the data stored in the SRAM 2 is read, the data in the address area is read after being transferred from the mask ROM 1 to the SRAM 2 in the same manner as described above.

If the upper 4 bits of the data transferred to the SRAM 2 are fixed, the capacity of the SRAM 2 will not be exceeded. Therefore, in the address comparison at the time of data transfer, only the upper 4 bits of the address of the mask ROM 1 are compared. If the upper 4 bits match, the data is transferred, and if they do not match, the upper 4 bits match. The read operation is performed after the data is transferred.

Therefore, for the convenience of reading data, when storing data and application programs in the mask ROM 1, it is desirable to store data or a series of application programs that are closely related to each other in the area where the upper 4 bits are the same.

FIG. 4 is a block diagram showing the circuit configuration of another embodiment of the IC card according to the present invention. The same parts as those in the above-described embodiment are designated by the same reference numerals and the description thereof will be omitted. The difference from the above-described embodiment is that the address bus 4c for transmitting the upper 4-bit address data is connected to the latch circuit 22 and the comparator 23, and the output of the latch circuit 22 is used as one input of the enable circuit 9 and the output line of the comparator 24. 24 is connected to a CPU (not shown).

That is, in the above-mentioned embodiment, the upper side address is compared on the system side. However, in this embodiment, when the upper 4 bits of the address do not match, "H" is sent to the system side via the output line 24. "" Is output to notify the discrepancy.

In this embodiment, the mask ROM 1 to SRAM are
When transferring data to 2, the upper 4 bits of the address data are fixed, but may be transferred from any address. In that case, it goes without saying that it is necessary to compare all the addresses.

[0031]

As described above, the IC card according to the present invention is equipped with both a large-capacity non-volatile memory and a small-capacity memory that operates at a higher speed than this non-volatile memory, and stores data in the non-volatile memory. Since data is transferred to a memory that can be read at high speed and only this memory that operates at high speed is accessed to read data, the read operation is fast even though the data capacity is large, and auxiliary circuits such as a backup power supply for data storage are The excellent effect that an inexpensive IC card that does not require a large number of elements and is inexpensive can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a conventional SRAM card.

FIG. 2 is a block diagram showing a circuit configuration of an IC card according to the present invention.

FIG. 3 is a conceptual diagram of data transfer in the IC card according to the present invention.

FIG. 4 is a block diagram showing a circuit configuration of another embodiment of the IC card according to the present invention.

[Explanation of symbols]

 1 Mask ROM 2 SRAM 3 Buffers 4a, 4b, 4c Address Bus 8 Transfer Circuit 9 Buffer Enable Circuit 12 Internal Data Bus

[Procedure amendment]

[Submission date] April 17, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

Claims (1)

[Claims] 1. An IC card for outputting data stored in a memory to the outside of the card, comprising: a nonvolatile memory;
A rewritable second memory that has a smaller capacity than the non-volatile memory and a higher data read speed than the non-volatile memory, a means for transferring data from the non-volatile memory to the second memory, and a second memory external to the card. To output data to the IC card.