JPH05127900A - Parallel processor - Google Patents

Abstract

PURPOSE:To ensure the smooth flow of data through a network and to improve the inter-processor communication efficiency by preferentially selecting an output port that has the large communication quantity. CONSTITUTION:The 16 processors PE00-PE33 forming a processor network 12 are divided into four groups in the row direction. The data received from the groups 0-3 are outputted to the outside through the output ports 14a-14d which are provided independently to the groups 0-3 respectively. A communication quantity detecting circuit 16 counts the busy signals sent from each processor for each group. An output arbiter circuit 20 compares the count values of busy signals with each other and outputs preferentially the data received from the output port having the largest count value to the outside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing device, and more particularly to a parallel processing device that communicates with a network of a plurality of processors and the outside through a plurality of output ports.

[0002]

2. Description of the Related Art A conventional parallel processor 1 is connected to a host computer or the like and outputs data to the outside of the host computer or the like. In this case, the parallel processing device 1 includes a high-performance processor network 2 in which a plurality of processors are combined, and a plurality of output ports 3 are provided in correspondence with the plurality of processors of the processor network 2 to improve efficiency. In such a case, the host computer or the like often cannot receive a plurality of data at the same time, and therefore the output arbitration circuit 4 arbitrates when the outputs from the plurality of output ports 3 compete with each other. Output arbitration is performed by multiple output ports 3
The priority order is set for each of the above, and when the outputs conflict with each other, the output is performed from the output port having the highest priority.

[0003]

In such an output arbitration method, consideration is given only to the existence and priority of the output data at the output port, and even if the output port has the most output data, the priority order is the highest. If it is low, it cannot be output until all the output data of other output ports are output. Therefore, there is a problem that output of a large amount of data may be delayed, and the efficiency of communication between the processors in the parallel processing device becomes poor.

Therefore, a main object of the present invention is to provide a parallel processing device capable of improving communication efficiency.

[0005]

According to a first aspect of the present invention, a plurality of processors each including a processing unit and a communication unit and mutually coupled, a plurality of output ports for outputting data from the plurality of processors, Communication amount detecting means for detecting the communication amount in the communication units of the plurality of processors, and one of the plurality of output ports according to the communication amount
It is a parallel processing device provided with an output arbitration means for preferentially outputting data from one terminal.

According to a second aspect of the present invention, a plurality of processors each including a processing unit and a communication unit and coupled to each other and divided into a plurality of groups; A plurality of output ports that individually output data from the group, a communication amount detection unit that detects the communication amount in the communication units of the multiple processors for each group, and a communication amount by comparing the communication amounts for each group Is a parallel processing device including output arbitration means for preferentially outputting data from one of the plurality of output ports having the maximum value.

[0007]

In the first invention, a plurality of processors are connected to each other to form a processor network. And the processor network is connected to multiple output ports,
When data is transferred from a certain processor to the outside, it is output via any output port. The communication amount detecting means detects the communication amount by, for example, a busy signal from each processor. Then, when the output requests from the plurality of output ports compete with each other, the output arbitration unit arbitrates based on the detected communication amount so as to preferentially output the data from the output port having the large communication amount to the outside. To do.

In the second invention, a plurality of processors form a processor network, wherein the plurality of processors are divided into a plurality of groups, and the data from each processor is individually provided for each group. Output through the output port. Then, the communication amount detecting means detects the communication amount for each group by the busy signal from each processor. The output arbitration unit compares the communication amount of each group connected to these output ports when the output requests from the plurality of output ports compete with each other, and outputs the data from the output port corresponding to the group having the maximum communication amount. Is output preferentially.

[0009]

According to the present invention, each output port is arbitrated according to the amount of communication, so that the data flow becomes smooth and the communication efficiency between the processors is improved. The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0010]

1 and 2, a parallel processing apparatus 10 of this embodiment has a processor network 12 in which 16 processors PE00 to PE33 having four communication ports are arranged in a two-dimensional matrix. including. In the processor network 12, PE00 to PE03 are group 0
And PE10 to PE13 form a group 1. PE20 to PE23 form a group 2, and PE30 to PE33 form a group 3. Groups 0-3 are connected to their own output ports 14a-14d, respectively. The groups 0 to 3 of the processor network 12 are connected to the communication amount detection circuit 16. The communication amount detection circuit 16 is composed of four busy counters 18a to 18d, and each of the busy counters 18a to 18d is a processor network 1 respectively.
2 groups 0 to 3 are respectively connected. Each busy counter and each group are connected so that busy signals from the four processors forming each group are applied to the busy counter. Then, the four busy counters 18a to 1 that configure the communication amount detection circuit 16
8d and four output ports 14a to 14d are connected to the output arbitration circuit 20.

Each processor constituting the processor network 12 is constructed as shown in FIG. 3, and data transfer is performed through the network control unit 22. The data to be transferred is in the form of the data packet shown in FIG.
The upper 2 bits of this data packet are flags indicating the presence and the start / end of the data packet. The network control unit 22 of each processor compares the destination processor number stored in the data packet with the number assigned to the processor, and if they match, the data is taken in internally, and if they do not match, they are transferred in the destination direction. Therefore, data can be transferred efficiently because the data is not taken into the areas other than the network controller except the destination processor. Then, when outputting data from a certain processor to the outside, the data is transferred to the leftmost processor in the same group,
This is done via the output port connected to this processor. Further, the network control unit 22 outputs a busy signal which becomes “1” when a data packet exists in the network control unit 22 and “0” when it does not exist. This is input to the communication amount detection circuit 16.

Next, with reference to FIG. 5, a method of arbitration when output requests from a plurality of output ports compete with each other will be described. As described above, the busy signal from each processor is input to the communication amount detection circuit 16. The busy counter 18a includes four processor PEs that form group 0.
Busy signals from 00 to PE03 are input, and busy signals from the four processors PE10 to PE13 forming the group 1 are input to the busy counter 18b. In addition, the busy counter 18c is included in the group 2 4
Busy signals from the four processors PE20 to PE23 are input, and busy signals from the four processors PE30 to PE33 forming the group 3 are input to the busy counter 18d. In each busy counter 18a-18d,
The number of "1" s of the busy signals of each group corresponding to each is counted and input to the comparator 24 in the output arbitration circuit 20. In the comparator 24, each busy counter 18a-18
The count value of d is compared and a control signal is sent to the multiplexer 26 also included in the output arbitration circuit 20. On the other hand, the data output from the output ports 14a to 14d is input to the multiplexer 26, and the multiplexer 26
Based on the control signal from the comparator 24, the data of the output port of the group having the maximum number of busy signals "1" is selected and output. The output port selected once outputs the data packet until the end of the data packet is output. At this time, whether or not the output is selected is notified to each output port, and the output of the data is waited for except the selected output port. Further, when the end of the data packet is output from the selected output port, the number of busy signals “1” of each group is again compared by the comparator 24 to select the output port.

In this way, the data packets are output to the outside in order from the group having the largest communication amount. Also, when the communication volume becomes lower than other groups due to the output of data packets to the outside, etc., the group with the maximum communication volume is output from the group connected to the output port that is waiting for output. Like next,
Referring to FIG. 6, a parallel processing device 30 of another embodiment has a processor network 32 in which 16 processors having four communication ports are arranged and connected in a two-dimensional matrix as in the previous embodiment. Including. The data transfer between the processors is performed in the same manner as in the previous embodiment. When outputting data from a certain processor to the outside, any one of the four processors forming the left end of the processor network, that is, the first column. Data is output to the four processors, and the data is output via the output ports 34a to 34d respectively connected to the four processors. The output of each output port is the output arbitration circuit 3
6 is input.

These four output ports 34a-34d
When there is a conflict between the output requests from the external device to the external device, the output arbitration circuit 36 selects which output port is to be preferentially output. Each of the 16 processors forming the processor network 32 outputs a busy signal which becomes "1" when the data packet exists in the network control unit 22 and becomes "0" when the data packet does not exist in the network control unit 22, as in the previous embodiment. Then, 16 busy signals are input to the communication amount detection circuit 38. The communication amount detection circuit 38 includes a decoder (ROM) not shown, and outputs the output ports 34a to 34a based on "1" or "0" of the busy signal from each processor.
The output arbitration circuit 36
Send to. In the output arbitration circuit 36, the communication amount detection circuit 38
Based on the input from, the output port with the largest communication amount is selected and the data is preferentially output to the outside.

In each of the above-mentioned embodiments, 16 processors and 4 output ports are used, but any number may be used.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

2 is a block diagram showing details of the processor network shown in FIG. 1. FIG.

FIG. 3 is a block diagram showing details of the processor shown in FIG.

FIG. 4 is an illustrative view showing one example of a data packet.

5 is a block diagram showing details of a communication amount detection circuit and an output arbitration circuit shown in FIG.

FIG. 6 is a block diagram showing another embodiment of the present invention.

FIG. 7 is a block diagram showing a conventional technique.

[Explanation of symbols]

 10, 30 ... Parallel processing device 12, 32 ... Processor network 14a-14d, 34a-34d ... Output port 16, 38 ... Communication amount detection circuit 18a-18d ... Busy counter 20, 36 ... Output arbitration circuit

Claims (2)

[Claims] 1. A plurality of processors, each processor including a processing unit and a communication unit, and coupled to each other; a plurality of output ports for outputting data from the plurality of processors; and a plurality of processors in the communication unit of the plurality of processors. A parallel processing apparatus comprising: a communication amount detecting unit for detecting a communication amount; and an output arbitration unit for preferentially outputting data from one of the plurality of output ports according to the communication amount. 2. A plurality of processors, each of which includes a processing unit and a communication unit, and which are coupled to each other and divided into a plurality of groups, each of which is uniquely assigned to each of the plurality of groups. A plurality of output ports for individually outputting the data, a communication amount detecting means for detecting a communication amount in the communication units of the plurality of processors for each of the plurality of groups, and comparing the communication amount for each of the plurality of groups. A parallel processing device, comprising: an output arbitration unit that preferentially outputs data from one of the plurality of output ports having the largest communication amount.