JPH0512460A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit area of a semiconductor substrate or the like and to widen operating frequency band width by sharing a clock width control part to a dynamic holding operation circuit group. CONSTITUTION:A clock generation part 2, static operation circuit group 3 to be operated based on a clock C1 from this clock generation part 2, clock width control part 4 to control the width of the clock C2 from the clock generation part 2, and dynamic holding operation circuit group 5 are provided on the semiconductor substrate. For this dynamic holding operation circuit group 5, output timing is controlled according to an output signal from the static operation circuit group 3 and a clock from the clock width control part 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit including a dynamic holding circuit.

[0002]

2. Description of the Related Art Conventionally, this kind of semiconductor integrated circuit is formed by a mixture of a dynamic holding circuit and a static operation circuit.

FIG. 7 is a block diagram of a conventional semiconductor integrated circuit. As shown in FIG. 7, the conventional semiconductor integrated circuit 1A has various dynamic holding circuits in addition to the clock generation circuit 2 and the static circuits 16 and 17. As such a dynamic holding circuit, there are an ALU 13, a ROM section 14, and another dynamic holding section 15, and each of these dynamic holding circuits has respective clock width adjusting sections 4A to 4C. The clock width adjusting units 4A to 4C are provided to prevent data retention failure in each unit. Here, the respective circuits are connected by clock lines C7 to C11 and signal lines S4 to S8. The necessity of this clock adjustment unit will be described below.

FIG. 8 is a specific circuit diagram of the dynamic holding operation circuit shown in FIG. As shown in FIG. 8, in this case, a dynamic holding operation circuit without a clock width adjusting section is shown. This circuit includes a static operation circuit group 16 via a clock from the clock generation circuit 2 and input terminals 20a to 20c. P-channel transistor 18 and N-channel transistor 1 for inputting signals from 17
The dynamic holding unit 10 has an inverter INVA that inverts signals from the dynamic holding unit 10 and outputs the inverted signals to the data holding circuit 7. Reference numeral 8 represents a power supply terminal.

FIG. 9 is a timing chart of various signals for explaining the circuit operation in FIG. As shown in FIG. 9, during normal operation of this dynamic holding operation circuit,
The dynamic holding unit 10 is precharged when the clock signal from the clock generation circuit 2 is at a low level. That is, in FIG. 8, the P channel type enhancement
The transistor 18 is turned on and the three N-channel enhancement transistors 19 are turned on. Next, when the clock signal is at the high level, the dynamic holding unit 10 inputs / outputs data. That is, P
When the channel type transistor 18 is turned off and any one of the three N channel type transistors 19 is turned on, the dynamic holding unit 10 becomes low level and all the N channel type transistors 19 are turned off. The dynamic holding unit 10 holds the high level. The data in the dynamic holding unit 10 is output to the data holding circuit 7 in synchronization with the clock signal.

FIG. 10 is a timing chart of various signals when the dynamic holding operation circuit in FIG. 9 is defective. Figure 10
As shown in, the dynamic retention failure is caused by the leakage of the charges in the dynamic holding unit 10 from the diffusion layer to the semiconductor substrate, and the charge leakage occurs as the high level of the clock signal becomes longer. When the dynamic holding unit 10 becomes a low level due to this charge leak, the data holding circuit 7 causes the dynamic holding unit 1 to synchronize with the clock signal.
Since the inverted data of 0 is input, a malfunction occurs. In order to prevent such a dynamic holding failure in the dynamic holding unit 10, each dynamic holding circuit is provided with a clock width adjusting unit.

FIG. 11 is a concrete circuit diagram of a clock width adjusting unit and a dynamic holding operation circuit in a semiconductor integrated circuit for explaining another conventional example, and FIG. 12 is a view for explaining the circuit operation in FIG. It is a timing diagram of various signals. As shown in FIG. 11, this circuit is the circuit of FIG. 8 provided with a clock width adjusting unit 4. Also, FIG.
As shown in FIG. 2, the high width of the clock signal can be selected by the clock width adjusting unit 4 to be an appropriate width that does not cause the dynamic retention failure.

Based on the above reason, each dynamic holding circuit is provided with a clock width adjusting section.

[0009]

Since the conventional semiconductor integrated circuit described above includes both static circuits and dynamic holding circuits, a plurality of clock width adjusting circuits are provided in order to prevent dynamic holding failure. Therefore,
The conventional semiconductor integrated circuit has a drawback that not only the circuit area increases but also the operating frequency band width of the circuit is narrowed.

It is an object of the present invention to provide a semiconductor integrated circuit capable of reducing the circuit area and widening the operating frequency band width of the circuit.

[0011]

According to another aspect of the present invention, there is provided a semiconductor integrated circuit in which a clock generator, a static operation circuit group which operates based on a clock from the clock generator, and the clock generator are provided on a semiconductor substrate. And a dynamic holding operation circuit group whose output timing is controlled by the output signal from the static operation circuit group and the clock from the clock width adjustment section. To be done.

[0012]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor integrated circuit showing a first embodiment of the present invention. As shown in Figure 1,
The semiconductor integrated circuit 1 according to the present embodiment includes a clock generation circuit 2
A static operation circuit group 3 and a clock width adjusting unit 4 which are respectively connected to the clock generating circuit 2 by clock lines C1 and C2, and a clock width adjusting unit which is connected to the static operation circuit group 3 by signal lines S1 to S3. Dynamic holding operation circuit group 5 connected to C4 through C3 to C5
Have and. The clock width adjusting unit 4 of the semiconductor integrated circuit 1 adjusts the clock width when the clock from the clock generating circuit 2 is supplied to the dynamic holding operation circuit group 5. Although not shown, the dynamic holding circuits in the dynamic holding operation circuit group 5 and the static operation circuits in the static operation circuit group 3 are connected by clock lines and signal lines, respectively.

FIG. 2 is a concrete circuit diagram centering on the dynamic holding operation circuit shown in FIG. As shown in FIG. 2, here, the clock width adjustment unit 4 and the first and second dynamic holding circuits 5A and 5B controlled by the output of the clock width adjustment unit 4 are shown at the circuit level. In addition, the first and second dynamic holding circuits 5A and 5B
Are the first data holding circuits 6a to 6n and the second data holding circuits, respectively.
Connected to the data holding circuit 7. Of these, the first dynamic holding circuit 5A includes the dynamic holding units 9a to 9a.
n, a P-channel type transistor connected to the power supply terminal 8, an N-channel type transistor connected to the input signal terminals IN1 to INn, and dynamic holding units 9a to 9n.
It has inverters INV1 to INVn and the like connected to. On the other hand, the second dynamic holding circuit 5B receives the input signal from the static operation circuit group 3 via the input terminals 11a to 11d and takes a NAND logic with the output of the clock width adjusting unit 4, and the dynamic holding unit. 10 and an inverter INVA connected to the dynamic holding unit 10. In particular, the inverter I
NV1 to INVn and INVA are clock width adjustment units 4
Dynamic holding unit 9a only when the signal from is high level
9n and 10 signals to the data holding circuits 6a to 6n and 7 are clocked inverters. still,
The first data holding circuits 6a to 6n and the second data holding circuit 7 are also connected to other static operation circuits or dynamic holding circuits.

FIG. 3 is a timing chart of various signals for explaining the circuit operation in FIG. As shown in FIG. 3, the clock signal from the clock generation circuit 2 is adjusted by the clock width adjusting unit 4, but the high-level width of the clock is adjusted to such a width that the dynamic holding unit does not cause a holding failure. To be done. Each dynamic holding unit is precharged when the adjusted clock signal CLK (aj) is at low level, and inputs data when it is at high level. Further, when the clock signal CLK (aj) is at the high level, the data in each dynamic holding unit is the inverter INV.
1 through INVn, INVA through the data holding circuit 6a
6n and 7 are held.

The first embodiment has been described above.
In the present embodiment, the operation of the two dynamic holding circuits 5A and 5B is controlled by one clock width adjusting unit 4. Therefore, regarding the area of the integrated circuit, the area corresponding to one clock width adjusting unit is reduced. can do. However,
In reality, since one clock width adjusting unit controls many dynamic holding circuits, the integrated circuit area can be greatly reduced. Moreover, the clock width adjusting unit 4 can select the high width of the clock signal to an appropriate value even in a region where the clock frequency is relatively small, so that the semiconductor integrated circuit can operate in a wide clock frequency band. It is possible to operate.

FIG. 4 is a specific circuit diagram centering on the dynamic holding operation circuit for explaining the second embodiment of the present invention, and FIG. 5 is various kinds for explaining the circuit operation in FIG. It is a timing diagram of a signal. As shown in FIGS. 4 and 5, the block configuration of this embodiment as a semiconductor integrated circuit is similar to the block configuration of FIG. 1, and differs from the first embodiment described above in that Of the dynamic holding circuit 5A. The dynamic holding unit 9 and the inverter INVB connected to the dynamic holding unit 9 are integrated into one, respectively, so that the data holding circuit 6 is also integrated into one. Further, on the output to the inverter INVB, the switching signal from the output switching terminal 12 determines which side of the N-channel transistor data is supplied. Moreover, the inverters INVA and INVB are clocked inverters that transmit the data in the dynamic holding units 9 and 10 to the data holding circuits 6 and 7 only when the output CLK (aj) from the clock width adjusting unit 4 is at a high level. These dynamic holding units 9 and 10 have CLK
When (aj) is at low level, it is precharged, and when it is at high level, data is input. That is, CLK
When (aj) is high level, the dynamic holding units 9 and 1
The data of 0 is held in the data holding circuits 7 and 6 through the inverters INVA and INVB. As described above, in the dynamic holding circuit, the clock width adjusting unit 4 can be shared. Therefore, the area of the integrated circuit can be reduced by controlling a large number of dynamic holding circuits with one clock width adjusting unit.

FIG. 6 is a block diagram of a semiconductor integrated circuit showing a third embodiment of the present invention. As shown in FIG.
The semiconductor integrated circuit 1 of this embodiment includes a clock generation circuit 2 and
A static operation circuit group 3 and a clock width adjusting unit 4 which are respectively connected to the clock generating circuit 2 by the clock lines C1 and C2, and a signal line S1 to S3 connected to the static operation circuit group 3 and a clock width adjusting unit 4. C
3 and C4 and a dynamic holding operation circuit group 5 connected to the clock generation circuit 2 by a clock line C6. In this embodiment, the clock signal from the clock generation circuit 2 is directly input to the dynamic holding operation circuit group 5 via the clock line C6 and used as a precharge control clock for the dynamic holding unit. That is, the output CLK (aj) from the clock width adjusting unit 4 is input to the dynamic holding operation circuit group 5 through the clock lines C3 and C4, and is used as a clock for controlling the data output timing from the dynamic holding unit.

[0019]

As described above, the semiconductor integrated circuit of the present invention is provided with the clock generating section, the static operation circuit group, the dynamic holding operation circuit group and the clock width adjusting section, and each of the clock width adjusting sections is provided. By sharing the dynamic holding operation circuit, the circuit area can be reduced. Further, the present invention has an effect that the operating frequency band width of the circuit can be easily widened by commonly using the clock width adjusting section.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a semiconductor integrated circuit showing a first embodiment of the present invention.

FIG. 2 is a specific circuit diagram centering on the dynamic holding operation circuit shown in FIG.

FIG. 3 is a timing chart of various signals for explaining the circuit operation in FIG.

FIG. 4 is a specific circuit diagram centering on a dynamic holding operation circuit for explaining a second embodiment of the present invention.

5 is a timing chart of various signals for explaining the circuit operation in FIG.

FIG. 6 is a block configuration diagram of a semiconductor integrated circuit showing a third embodiment of the present invention.

FIG. 7 is a block configuration diagram of a semiconductor integrated circuit showing a conventional example.

8 is a specific circuit diagram of the dynamic holding operation circuit shown in FIG.

9 is a timing diagram of various signals for explaining the circuit operation in FIG.

10 is a timing chart of various signals when the dynamic holding operation circuit in FIG. 9 is defective.

FIG. 11 is a specific circuit diagram of a clock width adjusting unit and a dynamic holding operation circuit in a semiconductor integrated circuit for explaining another conventional example.

FIG. 12 is a timing chart of various signals for explaining the circuit operation in FIG.

[Explanation of symbols]

1 semiconductor integrated circuit 2 clock generation circuit 3 static operation circuit group 4 clock width adjustment unit 5, 5A, 5B dynamic holding operation circuit group 6, 6a to 6n, 7 data holding circuit 8 power supply terminals 9a to 9n, 9, 10 dynamic holding Part 11 Input signal from static operation circuit group 12 Output switching terminals C1 to C6 Clock lines S1 to S3 Signal lines IN1 to INn Input signal terminals INV1 to INVn, INVA, INVB Inverters

Claims (1)

Claim: What is claimed is: 1. On a semiconductor substrate, a clock generator, a static operation circuit group that operates based on a clock from the clock generator, and a width of the clock from the clock generator. A semiconductor integrated circuit comprising: a clock width adjusting unit for adjusting; and a dynamic holding operation circuit group whose output timing is controlled by an output signal from the static operation circuit group and a clock from the clock width adjusting unit.