JPH0512459A - Single-chip microcomputer - Google Patents

Abstract

PURPOSE:To permit a test mode and to protect data stored in an incorporated PROM by inputting a password from the outside. CONSTITUTION:A test circuit 17 to permit the test mode is composed of a random number generation circuit 21, comparator circuit 22, counter 24 and shift register 20 and according to a serial circuit 18, the password is inputted from the outside to the shift register 20. At such a time, the counter 24 counts the number of times for shifting and when it reaches the fixed number of times, the shift is stopped. Simultaneously, the counter 24 outputs a clock 60, and the random number generation circuit 21 is operated synchronously with the clock 60 and generates a random number. The comparator circuit 22 compares the input password to the shift register 20 with the output value of the random number generation circuit 21 and only when they are coincident, a signal 9 is outputted to permit the test mode. Therefore, access is hardly performed to data having high privacy stored in the built-in PROM, and the danger of mallicious use is reduced as well.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single-chip microcomputer in which a memory function and a computer function are integrated on a single semiconductor substrate, and only when data corresponding to a value generated by a built-in random number generation circuit is input from the outside. , A single-chip microcomputer capable of directly testing an internal PROM from the outside.

[0002]

2. Description of the Related Art In recent years, due to advances in LSI manufacturing technology,
In the field of single-chip microcomputers (hereinafter referred to as single-chip microcomputers), high integration has been advanced, and the cost per unit function has been significantly reduced.

Conventionally, magnetic cards have been mainly used in financial institutions such as banks. However, magnetic cards have a small storage capacity and have a problem in terms of security. Recently, many crimes such as illegal use and forgery have occurred. Frequently occurs, which has become a major social problem. Therefore, an IC card equipped with a single-chip microcomputer has appeared as an alternative to this magnetic card, and large-scale experiments are in progress domestically and overseas. This IC card has a storage capacity several times larger than that of a magnetic card, and since the card has a built-in computer function, it has remarkably high reliability in terms of security.

Generally, in an IC card equipped with a single-chip microcomputer, most of the data memory is UVE.
PROM (Ultra-Violet Erasabl
eProgrammable ROM) or EEPR
OM (Electrical Erasable Pr)
A programmable ROM) is used (hereinafter, UVEPROM and EEPROM are collectively referred to as PROM), and its data memory is divided into several areas to manage the access.

When an IC card is used as a cash card or credit card issued by a financial institution such as a bank, a part of this divided data memory is called a secret zone, and the bank account number and ID number are used. , It is used to store highly confidential data such as secret numbers.

The secret zone is an important part for preventing illegal use and forgery of the IC card. When using the secret zone, the access to the area is managed by software so that the area can be accessed only in special cases. It has become. However, in the test mode of this IC card, the entire area of the extension PROM can be easily accessed directly from the outside, and the value in the secret zone can be read and abused or can be intentionally changed.

FIG. 7 is a block diagram of a conventional single-chip microcomputer. This single chip microcomputer 1b
Is a read-only or read-write memory used by the memory unit 3 for storing a user program and data, an internal bus 4 is a bus for transferring addresses and data in a time division manner, and an internal bus 8 is It is a time division bus used when transferring addresses and data to the internal bus 4 via the external terminal 10 in the test mode.

The central processing unit (hereinafter referred to as CPU) 2 is
Data processing is performed according to the program stored in the memory unit 3, and the peripheral unit 6 is composed of a board or the like for communication with the outside of the chip, and outputs the data input via the internal bus 4 to the external terminal 61. It has a function of inputting data from the external terminal 61 and outputting it to the internal bus 4.

The PROM 5 is a UVEP as a data memory.
It is composed of a ROM or an EEPROM, has a secret zone 5a in the memory, stores an ID number, a secret number, an account number, etc. of a card, and performs reading and writing by a command of a CPU. The user manages access to the secret zone 5a by software.

The external input terminal 15 is set to 1 in the test mode.
Since the output of the inverter 7 becomes 0 at this time, only the PROM 5 is connected to the internal bus 4, and the PROM 5 can be accessed directly from the outside of the chip. The input / output terminal 10 inputs / outputs addresses and data to / from the outside via the internal bus 8 and is connected to the internal bus 4. The clock terminal 12 is a CP output by the CPU 2.
The U clock 11 is output, and the reset terminal 13 is a CPU
It is a terminal to reset 2 and reset signal 14 when 1
Becomes 1 and the CPU 2 is reset.

Next, the operation during the test will be described. Terminal 13
Is set to 1 and the terminal 15 is set to 1 and the terminal 13 is set to 0 in synchronization with the fall of the CPU clock 11.

At this time, the test signal 9 becomes 1 and the output of the inverter 7 becomes 0, so that the CPU 2, the memory section 3 and the peripheral section 6 are electrically disconnected from the internal bus 4 and are therefore connected to the internal bus 4. Is only PROM5. In this state, an address and data are input to the PROM 5 via the external terminal 10 and the internal bus 8 to read and write data. At this time, if the address of the secret zone 5a is input, the data in the zone can be easily accessed, so that the data read and write can be easily performed.

In such a conventional single-chip microcomputer, access control to the secret zone 5a for storing secret data is all performed by user software. When this single-chip microcomputer is mounted on a card, it is possible to perform unauthorized data access to the secret zone by using the test mode. Furthermore, when an electrically erasable read-only memory (EEPROM) is used as the data memory, PRO is executed when a write command is executed.
Since the voltage for writing is automatically generated inside M, it is possible to easily perform improper writing in the secret zone.

[0014]

As described above, in a single-chip microcomputer that manages access to the secret zone, which is the access protection area in the conventional data memory, all access management to the built-in PROM is performed by software. Since it is performed by software, it is easily accessible in the test mode, and there is a risk that unauthorized access will be made and the data in the secret zone may be misused or the data may be intentionally rewritten. Were present.

An object of the present invention is to solve such a problem, and by adding a simple test circuit, it is possible to eliminate an unjust access in a test mode and easily obtain a more reliable security. To provide a single-chip microcomputer.

[0016]

According to the structure of the present invention, a central processing unit, a storage unit, a peripheral unit, and a programmable ROM (hereinafter referred to as PROM) are integrated on a single semiconductor substrate, and a test function for this PROM is provided. In a single-chip microcomputer including a test circuit, the test circuit includes a random number generation circuit, a shift register that holds serial data input from the outside, an output of the shift register, and a random number value generated by the random number generation circuit. And a control circuit which enables access to the PROM from the outside only when the comparison outputs of the comparison circuit are equal.

[0017]

1 (a) and 1 (b) are block diagrams of a first embodiment of a single-chip microcomputer of the present invention and a test circuit therefor. In this embodiment, the components other than the newly added test circuit 17 are the same as the conventional example shown in FIG. Therefore, the test circuit 17 will be mainly described.

In the figure, the test circuit 17 serially inputs data from the external terminal 19 in synchronization with the clock signal 11 output from the CPU, compares the value generated by the random number generation circuit with the value input from the outside, and It has the function of permitting the test mode only when they match.

As shown in FIG. 1B, the test circuit 17 comprises a shift register 20, a random number generation circuit 21, a comparison circuit 22, and a counter 24. Shift register 2
When 0 is the reset signal 14 and 1 is the shift enable signal 28, the signal line 18 is synchronized with the fall of the CPU clock 11.
Input the above 10-bit serial data. The random number generation circuit 21 generates a random number in synchronization with the clock generated by the counter 24. The comparison circuit 22 compares the output of the random number generation circuit 21 with the value stored in the shift register 20, and outputs the test signal 9 only when they match.

The counter 24 is a circuit for controlling the shift operation of the shift register 20. The counter 24 counts the CPU clock 11 only when the test mode signal 16 is 1 and the reset signal 14 is 0 in synchronization with the rise of the basic clock 11. And the shift enable signal 2 to the shift register 20.
8 is output.

FIG. 2 is a timing chart for explaining the operation timing of the test circuit 17. First, the reset signal 14
, And the test mode signal 16 is set to 0. Next, the test signal mode 16 is set to 1 and the reset signal 14 is set.
Is set to 0 in synchronization with the fall of the CPU clock 11. Then, in synchronization with the rise of the CPU clock 11, the external terminal 1
16-bit data is serially input from 9.

At this time, the counter 24 indicates the CPU clock 1
The shift enable signal 28 is set to 1 and output to the shift register 20 while counting 16 times in synchronization with 1. The counter 24 sets the shift enable signal 28 to 0 after 16 times of counting operation and stops. When the shift permission signal 28 is 1, the shift register 20 performs the shift operation 16 times in synchronization with the fall of the CPU clock 11, and then the shift permission signal 28 becomes 0, so that the shift operation is stopped.
When the reset signal 14 is 1, the stored value is cleared to 0. The comparison circuit 22 outputs the test signal 9 when the value generated by the random number generation circuit 21 and the value stored in the shift register 20 are the same.

FIG. 3 is a block diagram showing the structure of the counter 24, which is composed of a 4-bit up counter 30, an AND gate 31, and an RS latch 27.

When the reset signal 14 is 1, the up counter 30 is cleared and the operation is stopped. Further, the RS latch 27 is set and the shift permission signal 28 becomes 1.
When the reset signal 14 becomes 0, the test mode signal 16
Is 1 and the output of the RS latch 27 is 1, the counter 30
Counts up in synchronization with the rise of the output of the AND gate 31.

When counting 16 times, the fourth bit becomes 1, so that the RS latch 27 is reset and the output becomes 0. Therefore, the output of the AND gate 31 also becomes 1, and the counter 30 stops the counting operation.

FIG. 4 is a block diagram showing the configuration of the random number generation circuit 21 of the test circuit. This random number generation circuit 21
Operates according to the clock 60 generated by the counter 24
Generates a 6-bit random number, and executes an exclusive OR gate (hereinafter EX
OR gates) 50, 51, a 4-bit length shift register 55, a 7-bit length shift register 56, and a 5-bit length shift register 57. At the time of reset, these shift registers are initialized to a fixed value fixed by hardware.

The EXOR gate 50 is a shift register 5
7 and the shift outputs of the shift register 55 are input to output the exclusive OR, and the EXOR gate 51 inputs the shift outputs of the shift register 56 and the shift register 55 to output the exclusive OR.

The 4-bit shift register 55 has an EXOR
The output of the gate 51 is input and the shift operation is performed in synchronization with the clock 60.
The output of the gate 50 is input and the shift operation is performed in synchronization with the clock 60. The 5-bit length shift register 57 inputs the output of the shift register 55 and performs the shift operation in synchronization with the clock 60.

(1) First, when the reset signal 14 is 1,
The shift registers 55 to 57 are each initialized to a fixed value.

(2) When the clock 60 is input, the shift registers 55 to 57 shift right by 1 bit in synchronization with the clock 60, and at this time, the fourth register of the shift register 57 is shifted.
The shift output of the shift register 55 is input to the bit. The EXOR value with each shift output of the shift register 57 and the shift register 55 is input to the sixth bit of the shift register 56, and the shift register 57 and the shift register 56 are input to the third bit of the shift register 55.
The EXOR value of each shift output of is input.

(3) Similarly, since 16 clocks 60 are output, this operation is repeated 16 times.

The input value to the shift register 20 is 1
Since it is 6 bits long, there are 2 ¹⁶ patterns. Moreover, since the random number generation circuit 21 scrambles, it becomes more difficult to detect a 16-bit pattern that can realize the test mode. Therefore, it becomes more difficult for the third party to execute the test mode.

In this embodiment, by adding the test circuit 17 composed of simple hardware,
It becomes difficult for a third party to implement the test mode, and it is possible to prevent unauthorized access to the data in the secret zone 5a and loss of the data, and to realize a high degree of fail safe.

FIGS. 5A and 5B are block diagrams of a second embodiment of the single chip microcomputer of the present invention and a test circuit thereof. The present embodiment differs from the block diagram of FIG. 1 only in that a path from the PROM 5 to the test circuit 17a is provided.

The test circuit 17a of this embodiment is different from the test circuit 17 of the first embodiment in that the random number generation circuit 2
1a is different in that the initial value can be designated by the value built in the PROM 5.

The test circuit 17a loads an initial value from the PROM 5 into the random number generating circuit 21a, and then generates a 16-bit random number in the random number generating circuit 21a. The test circuit 17 outputs the signal 9 only when the random number and the input data to the shift register 20 match to realize the test mode.

Next, the configuration of the random number generation circuit 21a will be described with reference to FIG.

Like the random number generation circuit 21, the random number generation circuit 21a operates in accordance with the clock 60 generated by the counter 24 to generate a 16-bit random number, the EXOR gates 50 to 52, the 4-bit length shift register 55, It is composed of a 7-bit length shift register 56 and a 5-bit length shift register 57. At the time of resetting, these shift registers set the value stored in the PROM as an initial value.

The EXOR gate inputs the shift outputs of the shift register 57 and the shift register 55 and outputs the exclusive OR, and the EXOR gate 51 inputs the shift outputs of the shift register 56 and the shift register 55 and the exclusive logic. Output the sum.

The 4-bit length shift register 55 is an EXO.
The output of the R gate 51 is used as an input, and the shift operation is performed in synchronization with the clock 60.
The output of the XOR gate 50 is used as an input, the shift operation is performed in synchronization with the clock 60, and the 5-bit length shift register 57
Takes the output of the shift register 55 as an input and clocks 6
It operates in synchronization with 0. When the reset signal 14 is 1, each shift register loads the initial value stored in the PROM 5a.

Since the value input to the shifter register 20 is 16 bits long, there are 2 ¹⁶ patterns and the random number generator 21a scrambles the initial value output from the PROM, so that the test mode can be realized. It becomes more difficult to detect such a 16-bit pattern. Further, in the test circuit 17a, the initial value of the random number generating circuit can be changed, and it becomes more difficult to realize the test mode by periodically changing the initial value. Therefore, the third
It is more difficult for the person to implement the test mode than in the first embodiment.

[0042]

As described above, in the present invention,
By adding a test circuit that allows the test mode only when the data generated by the random number generation circuit and the data input from the outside match, data can be freely accessed to the secret zone in the conventional test mode. There is an effect that high-level security can be realized by prohibiting unjust data access that occurs in the event of an emergency.

[Brief description of drawings]

1A and 1B are block diagrams of a single-chip microcomputer and a test circuit 17 thereof in a first embodiment of the present invention.

FIG. 2 is a timing diagram illustrating an operation of the test circuit of FIG.

3 is a block diagram of a counter 24 in the test circuit of FIG.

4 is a block diagram of a random number generation circuit 51 in the test circuit of FIG.

5A and 5B are block diagrams of a second embodiment of the present invention and a test circuit thereof.

6 is a block diagram of a random number generation circuit in the test circuit of FIG.

FIG. 7 is a block diagram of an example of a conventional single-chip microcomputer.

[Explanation of symbols]

1, 1a, 1b Single-chip microcomputer 2 CPU 3 Memory section 4, 8 Internal bus 5 PROM 5a Secret zone 6 Peripheral section 7 Inverter 9 Test signal 10, 12, 13, 15, 19, 61 External terminal 11 CPU clock 14 Reset Signal 16 Test mode Signal 17, 17a Test circuit 18 18 Signal line 20 Shift register 21, 21a Encryption circuit 22 Comparison circuit 23 Password 24, 30 Counter 27 RS latch 28 Shift enable signal 31 AND gate 51, 52 EXOR gate 55 4-bit shift Register 56 7-bit shift register 57 5-bit shift register 60 clock

Claims (2)

[Claims] 1. A central processing unit, a storage unit, a peripheral unit, and a programmable ROM (hereinafter referred to as PROM) on a single semiconductor substrate.
In a single-chip microcomputer including a test circuit having a test function for the PROM, the test circuit includes a random number generation circuit,
A shift register that holds serial data that is input from the outside, a comparison circuit that compares the output of this shift register with the value of the random number generated by the random number generation circuit, and the comparison output of this comparison circuit from the outside only when the comparison outputs are equal. PR
A single-chip microcomputer comprising a control circuit that enables access to the OM. 2. The random number generating circuit has an initial value of PROM.
The single-chip microcomputer according to claim 1, wherein the single-chip microcomputer is set by.