JPH05122922A - Circuit for sensing failure of device - Google Patents
Circuit for sensing failure of deviceInfo
- Publication number
- JPH05122922A JPH05122922A JP27915491A JP27915491A JPH05122922A JP H05122922 A JPH05122922 A JP H05122922A JP 27915491 A JP27915491 A JP 27915491A JP 27915491 A JP27915491 A JP 27915491A JP H05122922 A JPH05122922 A JP H05122922A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- gto
- width
- failure
- sensing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Power Conversion In General (AREA)
- Rectifiers (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、自己消弧可能な素子か
ら構成される自励式電流形変換器の素子故障検出回路に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device failure detection circuit for a self-excited current source converter which is composed of self-turn-off devices.
【0002】[0002]
【従来の技術】近年、超電導コイルに直流電流を還流さ
せてエネルギを貯蔵し、核融合などのパルス負荷や、電
力のピ―ク負荷対策に用いる超電導エネルギ貯蔵システ
ム(以下、SMESと記す)の研究が進められている。
SMESは長時間ににわたる電力調整の他に、電力系統
と連系する変換装置を自己消弧可能な素子(例えば、ゲ
―トタ―ンオフサイリスタ、以下GTOと記す)で構成
すれば、系統安定化及び系統無効電力補償等の機能を有
することができる。図3は、電流形変換器に半導体素子
を使用したSMESの回路例を示す。2. Description of the Related Art In recent years, a superconducting energy storage system (hereinafter referred to as SMES) has been used for storing energy by circulating a direct current in a superconducting coil to prevent pulse load such as nuclear fusion and electric power peak load. Research is in progress.
In addition to long-term power adjustment, SMES is a system that is stable if the converter connected to the power system is composed of self-extinguishing elements (for example, gate turn-off thyristor, hereinafter referred to as GTO). It is possible to have functions such as conversion and system reactive power compensation. FIG. 3 shows a circuit example of the SMES using a semiconductor element for the current source converter.
【0003】図3において、1は変圧器、2は交流コン
デンサ、3a〜3fは半導体素子であり、自励式変換器
を構成している。4は超電導コイル、5は交流変流器、
6はしゃ断器、7は異常検出回路、8は制御指令に応じ
て半導体素子のオンオフを決めるゲ―トタイミング制御
回路、9はしゃ断器入力切回路、10は系統である。通
常このような回路では、半導体素子3aが短絡故障した
場合、S相―半導体素子3b―半導体素子3a―R相、
或いはT相―半導体素子3c―半導体素子3a―R相の
経路で短絡電流が流れ、交流変流器5及び異常検出回路
7で過電流を検出して、ゲ―トタイミング制御回路8に
より半導体素子3a〜3fにオフ信号を与えると共にし
ゃ断器入切回路9によりしゃ断器6を遮断していた。In FIG. 3, 1 is a transformer, 2 is an AC capacitor, and 3a to 3f are semiconductor elements, which constitute a self-excited converter. 4 is a superconducting coil, 5 is an AC current transformer,
Reference numeral 6 is a circuit breaker, 7 is an abnormality detection circuit, 8 is a gate timing control circuit for deciding on / off of a semiconductor element in response to a control command, 9 is a circuit breaker input disconnection circuit, and 10 is a system. Usually, in such a circuit, when the semiconductor element 3a has a short circuit failure, S phase-semiconductor element 3b-semiconductor element 3a-R phase,
Alternatively, a short-circuit current flows in the T-phase-semiconductor element 3c-semiconductor element 3a-R phase path, an overcurrent is detected by the AC current transformer 5 and the abnormality detection circuit 7, and the gate timing control circuit 8 detects the semiconductor element. The breaker 6 was shut off by the breaker on / off circuit 9 while the OFF signal was given to 3a to 3f.
【0004】ところで、半導体素子としてGTOを使用
する場合には、GTOの逆電圧阻止能力は非常に低いた
め、電圧形変換器のようにGTOに逆並列にダイオード
が接続される場合には、問題はないが図3のように電流
形変換器を構成する場合には問題がある。By the way, when a GTO is used as a semiconductor element, the reverse voltage blocking capability of the GTO is very low. Therefore, when a diode is connected in anti-parallel to the GTO like a voltage source converter, there is a problem. However, there is a problem in configuring the current source converter as shown in FIG.
【0005】従って、逆電圧阻止能力の非常に低いGT
Oで電流形変換器を構成する場合には、図4の構成例に
示すように、ダイオードDa〜DfをGTO3a〜3f
に直列接続して構成している。Therefore, a GT having a very low reverse voltage blocking capability
When configuring the current source converter with O, the diodes Da to Df are connected to the GTOs 3a to 3f as shown in the configuration example of FIG.
It is configured by connecting in series.
【0006】[0006]
【発明が解決しようとする課題】しかしながら、図4に
おいてはGTO3aが短絡故障してもダイオードDaが
あるために、S相ーGTO3bーダイオードDbーダイ
オードDaーGTO3a或いは、T相ーGTO3cーダ
イオードDcーダイオードDaーGTO3aの経路で短
絡電流が流れないため、GTO3aの短絡故障が検出さ
れないという問題がある。However, in FIG. 4, even if the GTO 3a is short-circuited, there is a diode Da. Since a short circuit current does not flow in the path of the GTO 3a, there is a problem that a short circuit failure of the GTO 3a is not detected.
【0007】故障が検出されないまま装置の運転を継続
すると制御が正常に行われないばかりではなく、系統に
対して異常電力を供給することになり、悪影響を与える
結果となる。このため、従来は、特公昭63ー3620
7号開示しているように、図3のGTO3a〜3fの各
々に素子故障検出器を設けて素子の故障を検出してい
た。このような従来のものでは、GTOの数だけ故障検
出器が必要となるため、高価になると共に構造が複雑に
なる問題があった。従って、本発明の目的は、前記問題
を除去するためになされたものであって、安価でシンプ
ルな素子故障検出回路を提供することにある。[0007] If the operation of the device is continued without detecting a failure, not only the control will not be performed normally, but also abnormal power will be supplied to the system, resulting in an adverse effect. For this reason, conventionally, the Japanese Examined Patent Publication No. 63-3620
As disclosed in No. 7, an element failure detector is provided in each of the GTOs 3a to 3f in FIG. 3 to detect an element failure. In such a conventional device, as many failure detectors as GTOs are required, so there is a problem that the cost becomes high and the structure becomes complicated. Therefore, it is an object of the present invention to provide an inexpensive and simple device failure detection circuit, which has been made to eliminate the above problems.
【0008】[0008]
【課題を解決するための手段】本発明は、上記目的を達
成するために、半導体素子としてGTOを用い、該GT
Oとダイオードの直列回路でアームが構成される自励式
電流形変換器において、この自励式電流形変換器の交流
電流の正側の通電幅と該通電幅を決定する前記GTOの
ゲートパルス幅の不一致を検出する手段と、前記自励式
電流形変換器の交流電流の負側の通電幅と該通電幅を決
定する前記GTOのゲートパルス幅の不一致を検出する
手段をそれぞれ具備したことを特徴とするものである。In order to achieve the above object, the present invention uses a GTO as a semiconductor element,
In a self-excited current source converter having an arm formed by a series circuit of O and a diode, the positive side energization width of the alternating current of the self-excited current source converter and the gate pulse width of the GTO for determining the energization width A means for detecting a mismatch, and a means for detecting a mismatch between the current-carrying width on the negative side of the alternating current of the self-exciting current source converter and the gate pulse width of the GTO for determining the current-carrying width. To do.
【0009】[0009]
【作用】前記のように構成することにより、自励式電流
形変換器を構成するいずれかのGTOに短絡故障が生じ
ると、該GTOを介して流れる交流電流の通電幅と該G
TOのゲートパルス幅とが不一致となるため、素子短絡
故障を検出することができる。With the above configuration, when a short-circuit fault occurs in any of the GTOs constituting the self-excited current source converter, the conduction width of the AC current flowing through the GTO and the G
Since the gate pulse width of TO does not match, the element short-circuit failure can be detected.
【0010】[0010]
【実施例】図3及び図4と同一部に同一符号を付して示
す図1は本発明の一実施例を示す構成図である。図1に
おいて、11はGTOのゲート信号Ga〜Gfと交流変
流器5の出力電流IR,IS,ITを比較し、不一致の
場合に故障信号を出力する素子故障検出回路である。図
2は図1の動作を説明するためのタイムチャート。以下
図1及び図2を参照して本発明を説明する。1 is a block diagram showing an embodiment of the present invention, in which the same parts as those in FIGS. 3 and 4 are denoted by the same reference numerals. In FIG. 1, reference numeral 11 is an element failure detection circuit that compares the gate signals Ga to Gf of the GTO with the output currents IR, IS and IT of the AC current transformer 5 and outputs a failure signal if they do not match. FIG. 2 is a time chart for explaining the operation of FIG. The present invention will be described below with reference to FIGS.
【0011】通常ゲートタイミング制御回路8よりのゲ
ート信号で運転を行っている。図2に各ゲート信号及び
交流電流波形を示し、正常時はゲート信号幅と交流電流
の通電幅は一致しているため素子故障検出回路11から
故障検出信号Fは出力されない。 もし、何等かの原因
で時刻t0 の時点でGTO3aが短絡故障になると、時
刻t0 以降の交流変流器5の出力電流IR,IS,IT
は、図2の点線で示す波形となる。一方、故障検出回路
11は、ゲート信号Gaの幅と交流電流IRの正側の通
電幅及びゲート信号Gbの幅と交流電流IRの負側の通
電幅の不一致を検出する排他的論理回路を有している。
更に、図示していなが、交流電流IS,ITについても
同様に構成されている。Normally, the operation is performed by the gate signal from the gate timing control circuit 8. FIG. 2 shows respective gate signals and AC current waveforms. In a normal state, the failure detection signal F is not output from the element failure detection circuit 11 because the gate signal width and the AC current conduction width match. If the GTO 3a is short-circuited at the time t0 for some reason, the output currents IR, IS, IT of the AC current transformer 5 after the time t0.
Has a waveform shown by a dotted line in FIG. On the other hand, the failure detection circuit 11 has an exclusive logic circuit that detects a mismatch between the width of the gate signal Ga and the energization width of the positive side of the alternating current IR, and the width of the gate signal Gb and the energization width of the negative side of the alternating current IR. is doing.
Further, although not shown, the alternating currents IS and IT are similarly constructed.
【0012】従って、時刻t0 以後GTO3aが短絡故
障になるとゲート信号Gaの幅と交流電流IRの正側の
通電幅に不一致が生じて素子故障検出回路11から故障
信号Fが発生する。この故障信号Fによって、速かにし
ゃ断器6が解放される。もし、しゃ断器6を解放しなけ
れば交流変流器5の出力電流IR,IS,ITは点線の
ような波形となる。Therefore, when the GTO 3a has a short circuit failure after the time t0, the width of the gate signal Ga and the energization width of the positive side of the alternating current IR do not coincide with each other, and the failure signal F is generated from the element failure detection circuit 11. The breaker 6 is quickly released by the fault signal F. If the circuit breaker 6 is not released, the output currents IR, IS and IT of the AC current transformer 5 have waveforms like dotted lines.
【0013】[0013]
【発明の効果】以上説明のように、本発明によれば、G
TOのゲート信号と変換器の交流電流を検出する交流変
流器5の出力電流とを比較し、その不一致検出によって
素子の短絡故障を検出するようにしているため、簡単且
安価な素子故障検出回路を提供できる。As described above, according to the present invention, G
Since the gate signal of TO is compared with the output current of the AC current transformer 5 for detecting the AC current of the converter, and the short circuit failure of the element is detected by the mismatch detection, the element failure detection is simple and inexpensive. A circuit can be provided.
【図1】 本発明の一実施例を示す構成図。FIG. 1 is a configuration diagram showing an embodiment of the present invention.
【図2】 図1の動作を説明するためのタイムチャ―
ト。FIG. 2 is a time chart for explaining the operation of FIG.
To.
【図3】 電流形変換器を用いた超電導エネルギ貯蔵シ
ステムの構成図。FIG. 3 is a configuration diagram of a superconducting energy storage system using a current source converter.
【図4】 GTOを用いた自励式電流形変換器の基本構
成図。FIG. 4 is a basic configuration diagram of a self-excited current source converter using a GTO.
1 …変圧器 2…交
流コンデンサ 3a〜3f…GTO 4…超
電導コイル 5 …交流変流器 6…し
ゃ断器 8 …ゲートタイミング制御回路 9…し
ゃ断器入切回路 11 …素子故障検出回路 F…故
障検出信号 IR〜IT…交流電流 Ga〜Gf…ゲート信号 Da〜Df…ダイオートDESCRIPTION OF SYMBOLS 1 ... Transformer 2 ... AC capacitors 3a-3f ... GTO 4 ... Superconducting coil 5 ... AC current transformer 6 ... Breaker 8 ... Gate timing control circuit 9 ... Breaker on / off circuit 11 ... Element failure detection circuit F ... Failure detection Signal IR-IT ... AC current Ga-Gf ... Gate signal Da-Df ... Die auto
Claims (1)
Oとダイオードの直列回路でアームが構成される自励式
電流形変換器において、この自励式電流形変換器の交流
電流の正側の通電幅と該通電幅を決定する前記GTOの
ゲートパルス幅の不一致を検出する手段と、前記自励式
電流形変換器の交流電流の負側の通電幅と該通電幅を決
定する前記GTOのゲートパルス幅の不一致を検出する
手段をそれぞれ具備して成る素子故障検出回路。1. A GTO is used as a semiconductor element, and the GT is used.
In a self-excited current source converter having an arm formed by a series circuit of O and a diode, the positive side energization width of the alternating current of the self-excited current source converter and the gate pulse width of the GTO for determining the energization width Device failure comprising means for detecting a mismatch and means for detecting a mismatch between the negative side energization width of the alternating current of the self-excited current source converter and the GTO gate pulse width for determining the energization width. Detection circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27915491A JPH05122922A (en) | 1991-10-25 | 1991-10-25 | Circuit for sensing failure of device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27915491A JPH05122922A (en) | 1991-10-25 | 1991-10-25 | Circuit for sensing failure of device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05122922A true JPH05122922A (en) | 1993-05-18 |
Family
ID=17607207
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27915491A Pending JPH05122922A (en) | 1991-10-25 | 1991-10-25 | Circuit for sensing failure of device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05122922A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017119109A1 (en) * | 2016-01-07 | 2017-07-13 | 東芝三菱電機産業システム株式会社 | Ac-dc converting device and control method for same |
-
1991
- 1991-10-25 JP JP27915491A patent/JPH05122922A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017119109A1 (en) * | 2016-01-07 | 2017-07-13 | 東芝三菱電機産業システム株式会社 | Ac-dc converting device and control method for same |
JPWO2017119109A1 (en) * | 2016-01-07 | 2018-09-13 | 東芝三菱電機産業システム株式会社 | AC / DC converter and control method thereof |
US20180351449A1 (en) * | 2016-01-07 | 2018-12-06 | Toshiba Mitsubishi-Electric Industrial Systems Corporation | Ac-dc conversion device and method for controlling same |
US10404157B2 (en) | 2016-01-07 | 2019-09-03 | Toshiba Mitsubishi-Electric Industrial Systems Corporation | AC-DC conversion device and method for controlling same by controlling the timing of multiple switch portions |
US20190273430A1 (en) * | 2016-01-07 | 2019-09-05 | Toshiba Mitsubishi-Electric Industrial Systems Corporation | Ac-dc conversion device and method for controlling same by controlling the timing of multiple switch portions |
US10938297B2 (en) | 2016-01-07 | 2021-03-02 | Toshiba Mitsubishi-Electric Industrial Systems Corporation | AC-DC conversion device and method for controlling same by controlling the timing of multiple switch portions |
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