JPH05122834A - Motor driver - Google Patents

Abstract

PURPOSE:To provide a motor driver in which a transistor for driving a motor can be protected positively even if the motor is stopped forcibly due to an external cause. CONSTITUTION:Even if a motor 1 is stopped forcibly due to an external cause, a rotational state deciding circuit 8 can make a decision that no rotational position detection signal exist within a predetermined period of second clock signal and thereby drive input to the internal element of a drive circuit 5 is interrupted by means of a drive control signal outputted from the rotational state decision circuit 8 thus stopping driving signal supply to the motor 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor drive device capable of preventing a circuit element for driving a motor from being destroyed when the motor is forcibly stopped from rotating due to some external factor.

[0002]

2. Description of the Related Art Generally, when speed control is performed in order to rotate a motor at a desired number of rotations, an FG signal generated according to the rotation of the motor is compared with a predetermined clock signal, and the FG signal is compared with the clock signal. The rotation speed of the motor is controlled according to whether the signal frequency is high or low. That is, FG
When the frequency of the signal and the frequency of the clock signal match, the rotation speed of the motor is considered to be the desired rotation speed, and the motor rotates at a constant speed while maintaining this rotation speed.
If the frequency of the signal is higher than the frequency of the clock signal, the motor is rotating faster than the desired number of revolutions, so the deceleration signal for decelerating the current number of revolutions of the motor to the desired number of revolutions causes the motor to rotate. If the frequency of the FG signal is lower than the frequency of the clock signal, the motor is rotating slower than the desired number of revolutions, so the current number of revolutions of the motor is changed. The rotation of the motor is accelerated by an acceleration signal for accelerating to a desired rotation speed, and the motor is rotated at a constant speed. Here, the clock signal that is a source for rotating the motor at a constant speed is generated from an oscillation circuit to which a crystal oscillator or the like is connected.

[0003]

When the motor which is rotating at a constant speed is forcibly stopped by an external factor on a trial basis, the FG signal is not applied to the drive circuit for driving the motor. That is, it is determined that the zero FG signal having no change is applied. Then, the number of rotations of the motor is erroneously determined to be lower than the desired number of rotations, that is, an acceleration signal is always generated, and a large current flows through the output transistor inside the drive circuit for driving the motor, There is a problem that the output transistor is destroyed.

Therefore, an object of the present invention is to provide a motor drive device capable of reliably protecting a transistor for driving a motor even if the motor is forcibly stopped by an external factor.

[0005]

The present invention has been made to solve the above-mentioned problems, and is characterized in that an FG signal generated according to the rotation speed of a motor and a first FG signal are generated. A speed control circuit that outputs a speed control signal for controlling the rotation speed of the motor based on a comparison result with a clock signal, and to drive the motor at a desired rotation speed based on the speed control signal. A drive circuit that outputs a drive signal of the second drive signal, and a second drive signal and a rotational position detection signal generated according to the rotational position of the motor are applied to the second drive circuit. A rotation state determination circuit that determines whether or not the rotational position detection signal is present during a predetermined cycle of a clock, and outputs a drive control signal for controlling the drive circuit based on the determination result. The rotation state determining circuit, the second
When it is determined that the rotational position detection signal does not exist during the predetermined period of the clock signal, the drive control signal for stopping the supply of the drive signal to the motor is output.

[0006]

According to the present invention, even if the motor is forcibly stopped due to an external factor, the rotation position determination circuit causes the rotation position detection signal to exist during the predetermined period of the second clock signal. Since the absence state can be determined, the drive control signal output from the rotation state determination circuit stops the supply of the drive signal to the motor.

[0007]

The details of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a circuit of the present invention, FIG. 2 is a circuit diagram showing a rotation state judging circuit which constitutes FIG. 1, and FIG. 3 is a timing chart showing waveforms of respective parts of FIG. In FIG. 1, (1) is a motor having, for example, three-phase drive coils, and the motor (1) generates an FG signal according to its rotation. Since the FG signal has a low level, it is amplified by the amplifier (2). (3) is an oscillating circuit that is connected to, for example, a crystal oscillator and performs an oscillating operation, and outputs a first clock signal CLK1 required to control the speed of the motor (1). (4) is a speed control circuit, which compares the frequency of the FG signal and the clock signal CLK1. And FG
When the frequency of the signal is lower than the frequency of the clock signal CLK1, the rotation speed of the motor (1) is slower than the desired rotation speed.
The speed control circuit (4) outputs an acceleration signal for accelerating the rotation speed of the motor (1) to a desired rotation speed. On the contrary, F
When the frequency of the G signal is higher than the frequency of the clock signal CLK1, the speed of the motor is faster than the desired speed, so the speed control circuit (4) reduces the speed of the motor (1) to the desired speed. To output a deceleration signal. Reference numeral (5) is a drive circuit, which receives an acceleration signal or a deceleration signal output from the speed control circuit (4), and outputs a drive signal for rotating the motor (1) at a desired rotation speed according to these signals. Output.
That is, the speed of the motor (1) is controlled by the feedback loop including the motor (1), the amplifier (2), the speed control circuit (4), and the drive circuit (5).

(6) is an oscillating circuit,
The second clock signal CLK2 having a lower frequency than the clock CLK1 obtained from (3) is generated.
(7) is a Schmitt amplifier having hysteresis.
Here, a hall element (not shown) for detecting the rotational position of the motor (1) is fixed to the stator of the motor (1), and the Schmitt amplifier (7) outputs the sine wave output of the hall element. It is provided to amplify and output as a square wave. The reason why the Schmitt amplifier (7) is used to amplify the Hall element output is as follows. In other words, if noise is superimposed on the output of the Hall element by using a Schmitt amplifier (7) having two different threshold levels,
It is possible to reliably remove the output superimposed noise of the Hall element existing between the threshold levels of various types, but if an ordinary amplifier (not shown) having a single threshold level is used separately, the threshold levels will not be wide. Therefore, the output superimposed noise of the Hall element is amplified as it is without being removed. That is, the Schmitt amplifier
This is because the use of (7) has the effect of removing the output superimposed noise of the Hall element. (8) is a rotation state determination circuit for determining whether or not the motor (1) is rotating, and the clock signal CLK2 and the hall signal HL (rotation position detection signal) obtained from the Schmitt amplifier (7) are It is applied to determine whether or not the hall signal HL is present during a predetermined period of the clock signal CLK2 (whether or not there is a change in rising and falling of the hall signal HL).
That is, the rotation state determination circuit (8) detects whether there is an abnormality in the generation of the hall signal HL and determines the presence of the hall signal HL. For example, when the rotation of the motor (1) is forcibly stopped due to an external factor even though the motor (1) is about to rotate at a constant speed, the rotation state determination circuit (8) outputs a drive signal. A drive control signal DRV for cutting off the drive input to the internal elements of the circuit (5) and stopping the supply of the drive signal to the motor (1) is output. The drive circuit (5) receives the drive control signal DRV and receives the motor (1).
Stop supplying drive signal to the. From this, the motor (1)
Since the drive source of 1 is cut off, the motor (1) rotates only by inertia and stops after a predetermined time. by this,
It is possible to prevent a large current from flowing through an output transistor (not shown) for driving the motor (1) provided inside the drive circuit (5) and prevent the drive circuit (5) from being destroyed.

Next, FIG. 2 showing a concrete example of the rotation state judging circuit (8) will be explained. Figure 2 shows IIL (Integrated In)
(Jection Logic), (9)
Is in synchronization with the fall of the hall signal HL
-A reset pulse generation circuit that generates a reset pulse for resetting the FF. The inside of the reset pulse generation circuit (9) has inverters (10), (11), (1) connected in series.
2) and flip-flop connected inverters (13) (14)
And inverters (15) (16) (17) (18) connected in series. The hall signal HL is sent to the inverter (10).
Is applied, and the output of the inverter (10) is applied to the inverter (13) forming a flip-flop. Further, the output of the inverter (11) is fed back to the inverter (14) forming a flip-flop via the four-stage inverters (15), (16), (17) and (18). Further, the logical product of both outputs of the inverters (10) and (13) is applied to the inverter (11). here,
The input timing of the inverters (13) and (14) that form the flip-flop will be described. The input timing of the inverter (14) is higher than that of the inverter (13). ) (16) (17)
It will be delayed by the signal transmission time between the input and output of (18). That is, when the hall signal HL falls from the high level (hereinafter referred to as “H”) to the low level (hereinafter referred to as “L”), the inverter (12) starts from the fall of the hall signal HL to the inverter (11). ) (15) (16) (17) (18) outputs the reset pulse a which becomes “H” for the transmission delay time.

Reference numeral (19) is a D-FF for dividing the clock signal CLK2 by 1/2, the D (data) terminal and the * Q (inverted output) terminal are connected, and the C (clock) terminal is connected. The clock signal CLK2 is reversely applied, and the reset pulse a is applied to the R (reset) terminal. That is, the motor
(1) rotates steadily and the reset pulse a is the hall signal HL.
If it occurs in synchronization with the falling edge of D-FF (1
The output of the Q terminal of 9) rises to "H" in synchronization with the fall of the clock signal CLK2, and then falls to "L" in synchronization with the reset pulse a immediately after that, so that No divide-by-2 output can be obtained. However, when the rotation of the motor (1) is forcibly stopped by an external factor and the reset pulse a is no longer generated,
From the Q terminal of the D-FF (19), the output b divided by 1/2 is obtained in synchronization with the fall of the clock signal CLK2. Further, (20) is a D-FF for dividing the Q terminal output b of the D-FF (19) by 1/2,
The Q terminal is connected to the Q terminal, the Q terminal output b of the D-FF (19) is inversely applied to the C terminal, and the reset pulse a is applied to the R terminal. That is, when the 1/2 frequency-divided output b of the clock signal CLK2 is obtained from the Q terminal of the D-FF (19), D-
From the Q terminal of the FF (20), the output c further divided by 1/2 in synchronization with the fall of the 1/2 divided output b, that is, the 1/4 divided output of the clock signal CLK2 is obtained. become. Here, the Q terminal outputs b and c of the D-FFs (19) and (20) are ANDed to form a signal d. When this signal d is "H", the supply of the drive signal to the motor (1) is stopped. It becomes a stop instruction signal to instruct. The D-FFs (19) and (20) and the logical product means of the outputs b and c (intersection of the outputs b and c) constitute a stop instruction signal generating circuit. Further, (21) is a D-FF that outputs a drive control signal DRV of "H" or "L" according to the stop instruction signal d, the D terminal is in an open state, and the C terminal has a stop instruction signal. d is reversely applied, and the reset pulse a is applied to the R terminal. That is, when the stop instruction signal d falls, the drive control signal DRV of "H" is output from the Q terminal of the D-FF (21), and then the hall signal HL is restored and the fall reset pulse a is generated. , The drive control signal DRV falls to "L" in synchronization with the rising of the reset pulse a. In addition, D-FF
(21) constitutes a drive control signal generation circuit, and the drive control signal D
Only when the RV is "H", the drive input to the elements inside the drive circuit (5) is cut off and the supply of the drive signal to the motor (1) is stopped. Further, the output of the inverter (22) is logically connected to the output of the inverter (11), and when the motor (1) forcibly stopped is started to rotate again, a pulse START that becomes “H” is generated by the inverter ( It is applied to the input of 22).

The operation of the present invention will be described with reference to FIG. First, before time t ₀ , the FG signal and the clock signal CLK1 are normally applied to the speed control circuit (4), and control for driving the motor (1) at a desired rotation speed is performed. .. On the other hand, the hall signal HL and the clock signal CLK2 when the motor (1) is steadily rotating are applied to the rotation state detection circuit (8), and a reset pulse is generated at each falling edge of each cycle of the hall signal HL. Therefore, the drive control signal DRV remains "L" at all times, and the drive signal output from the drive circuit (5) is applied to the motor (1) without being stopped. ) Will be speed controlled to a desired number of revolutions. After that, time t ₀
When the rotation of the motor (1) is forcibly stopped due to an external factor in spite of the motor (1) trying to rotate at a constant speed, the FG signal is always "L".
Therefore, the speed control circuit (4) erroneously determines that the motor (1) is rotating at a speed lower than the desired speed,
The motor (1) sends a drive signal instructing acceleration from the drive circuit (5).
It tries to operate so that it may be applied to. However, at time t
_{In 1 the} drive control signal DRV rises to "H" when the clock signal CLK2 is divided by 1/4, so that the supply of the drive signal to the motor (1) is stopped.
It is possible to prevent a large current from flowing through the output transistor inside the drive circuit (5) circuit in an attempt to accelerate (1). That is, if the stop state of the hall signal HL does not change even after a predetermined time t _{0 to} t ₁ has elapsed since the hall signal HL stopped, it is determined that the transmission of the hall signal HL is cut off. Then, the drive input to the elements inside the drive circuit (5) is cut off and the supply of the drive signal to the motor (1) is stopped.

[0012] Then, at time t _2, when the START pulse rises to "H", since the reset pulse a rises to the "H" Along with this, the drive control signal DRV falls to "L", the drive than this When the signal is supplied to the motor (1), the hall signal HL starts to be generated at time t ₃ ,
The speed of the motor (1) will be controlled. D which constitutes the stop instruction signal generation circuit inside the rotation state determination circuit (8)
Number of -FF is not limited to two stages, as more may be longer determination period t ₀ ~t ₁ of the presence or absence of the Hall signal HL, the characteristics of the motor (1) in this respect The number of D-FF stages may be set in consideration.

From the above, even when the motor (1) is trying to rotate at a constant speed, the rotation state is detected even if the rotation of the motor (1) is forcibly stopped by an external factor. Depending on the circuit, the clock signal CLK2
Since it can be determined that the hall signal HL is no longer transmitted by detecting the absence of the hall signal HL during the predetermined period of, the supply of the drive signal to the motor (1) is stopped and the drive circuit ( 5) can be protected.

[0014]

According to the present invention, even if the motor is forcibly stopped due to an external factor, the rotation state determination circuit causes the rotation position detection signal to exist during the predetermined period of the second clock signal. Since it is possible to determine the state in which the motor is not operating, the supply of the drive signal to the motor is stopped by the drive control signal output from the rotation state determination circuit. As a result, it is possible to prevent a large current that attempts to rotate the motor from flowing through the drive circuit element for driving the motor, and there is an advantage that the drive circuit element can be protected.

[Brief description of drawings]

FIG. 1 is a diagram showing a device of the present invention.

FIG. 2 is a circuit diagram showing a rotation state determination circuit of FIG.

FIG. 3 is a timing chart showing waveforms at various points in FIG.

[Explanation of symbols]

 (1) Motor (4) Speed control circuit (5) Drive circuit (8) Rotation state judgment circuit

Claims (5)

[Claims] 1. An FG generated according to a rotation speed of a motor.
A speed control circuit that outputs a speed control signal for controlling the rotation speed of the motor based on a comparison result between the signal and the first clock signal; and based on the speed control signal,
A drive circuit that outputs a drive signal for driving the motor at a desired rotation speed, wherein a rotation position detection signal and a second clock signal that are generated according to a rotation position of the motor are provided. Is applied,
A rotation state determination circuit that determines whether the rotational position detection signal is present during a predetermined cycle of the second clock and outputs a drive control signal for controlling the drive circuit based on the determination result. The rotation state determination circuit includes a drive control signal for stopping the supply of the drive signal to the motor when it is determined that the rotation position detection signal does not exist during a predetermined cycle of the second clock signal. The motor drive device is characterized in that 2. The rotation state determination circuit is a reset pulse generation circuit that generates a reset pulse for each cycle of the rotation position detection signal, and is reset by the reset pulse when the rotation position detection signal exists. And a stop instruction signal generation circuit for generating a stop instruction signal for instructing to stop the supply of the drive signal to the motor based on a predetermined frequency division result of the second clock signal when the rotational position detection signal does not exist, 2. A motor drive device according to claim 1, further comprising a drive control signal generation circuit that generates a drive control signal for stopping the supply of the drive signal to the motor based on the stop instruction signal. .. 3. The rotation state determination circuit outputs a drive control signal for stopping the supply of a drive signal to the motor, and then outputs a drive pulse to the motor in response to a start pulse for restarting the rotation of the motor. The motor drive device according to claim 2, wherein a drive control signal for restarting the supply of the drive signal is output. 4. The motor drive device according to claim 1, wherein the frequency of the second clock signal is lower than the frequency of the first clock signal. 5. The frequency of the second clock signal is set to a frequency at which the stop instruction signal generating circuit can be reset by the reset pulse before the stop instruction signal is generated during steady rotation of the motor. The motor drive device according to claim 3, wherein