JPH05122531A - Image encoder - Google Patents

Abstract

PURPOSE:To provide the device for a high-speed processing, the exact adjustment of a data amount and error countermeasure in case of transmission with a small hardware amount when quantizing data, for which image information is changed into a frequency area, and turning those data into a variable length code. CONSTITUTION:Transformed data outputted from one-frame period delay circuits 34a-34d are quantized by quantizing circuits 32a-32e, data amount information nb1-nb4 in the case of encoding those data by variable length code circuits 40a-40e decides the quantizing steps of respective stages, and the output of the variable length code circuit 40e is defined as the encoded output of an AC component. In comparison with this variable length code 40e, a DC component is extracted from the stage preceding for one frame by a DC extraction circuit 51 and turned to an equal length code through a quantizing circuit 52 and encoding circuit 54. These encoded outputs of DC and AC components are transmitted after adjusting the order of transmission so as to first transmit the DC component by buffer memories 46 and 56 and a multiplexer 48.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding apparatus,
In particular, the present invention relates to an image coding apparatus that quantizes conversion data obtained by converting image information into a frequency domain and performs variable length coding on the quantized conversion data.

[0002]

2. Description of the Related Art In recent years, an adaptive DCT (Discrete Cosine Transform) coding system has been attracting attention as a coding system for color image signals, and a group established as an international standardization organization for this type of coding system. A certain JPEG (Joint
Photographic Expert Group
The DCT coding method is also used in the coding method in p).

An outline of the basic system of this type of encoding system will be briefly described below.

FIG. 4 is a block diagram for explaining a schematic configuration example of a conventional coding method using the DCT transform, and FIGS. 5 to 8 are diagrams for explaining processing of the coding method shown in FIG. is there. Reference numeral 2 is an input terminal for a digital image signal to be encoded, to which a digital image signal by raster scanning is input. The image signal input to the terminal 2 is 8 × 8
It is input to the blocking circuit 4 and is two-dimensionally (8 ×
8) Divided into pixel blocks made up of pixels, and these pixel blocks are sent to the subsequent stage.

Reference numeral 6 denotes a DCT conversion circuit which performs DCT conversion on the image signal from the blocking circuit 4 and outputs a (8 × 8) data matrix in the frequency domain. That is, the pixel block composed of the image data D _{11 to} D ₈₈ as shown in FIG. 5 is converted by the circuit 6 into X _{11 to} X _{88 as} shown in FIG.
Is converted into a data matrix consisting of

Here, X ₁₁ represents a direct current (DC) component in the horizontal and vertical directions of the pixel block, that is, an average value of this pixel block. When X _{11 to} X ₈₈ are generally designated as X _ij , a component having a higher frequency in the vertical direction as i increases, and a component having a higher frequency in the horizontal direction as j greater.

The data matrix output from the DCT conversion circuit 6 is input to the linear quantization circuit 8. On the other hand, the quantization matrix generation circuit 18 uses the DCT coefficients X _{11 to} X _88.
To generate a quantization matrix W _{11 to} W ₈₈ (shown in FIG. 5) indicating weighting of the quantization step size, and the coefficient generation circuit 16 generates a coefficient C. The quantization matrices W _{11 to} W ₈₈ and the coefficient C are input to the multiplier 20. The multiplier 20 calculates (W _ij × C), and the quantization step of the linear quantization circuit 8 is determined according to the outputs Q _{11 to} Q ₈₈ of the multiplier 20. Here, C is a positive value, and the value of C controls the image quality and the amount of generated data.

In practice, the linear quantizing circuit 8 uses X _ij / Q
_ij is calculated and output. The outputs of the linear quantization circuit 8 are G _{11 to} G ₈₈ . This quantized converted data G
_{11 to} G ₈₈ are sequentially transmitted from the DC component in the zigzag scanning circuit 10. That is, from the zigzag scanning circuit 10, G ₁₁
~ G ₈₈ is G ₁₁ , G ₁₂ , G ₂₁ , G ₃₁ , G ₂₂ , G ₁₃ , G ₁₄ ,
G ₂₃ , G ₃₂ , G ₄₁ ... G ₈₅ , G _86, G ₇₇ , G ₆₈ , G ₇₈ , G
₈₇ and G ₈₈ are sequentially supplied to the variable length coding circuit (VLC) 12.

In the VLC 12, for example, a DC component G
_{For 11} , the prediction value is calculated between pixel blocks located in the vicinity, and the prediction error with this prediction value is Huffman coded. Alternatively, only this DC component is isometrically encoded. On the other hand, for the AC components G _{12 to} G ₈₈ other than the DC component G ₁₁ , the quantized output is encoded while zigzag scanning from the low frequency component to the high frequency component as described above, and the quantized output is a non-zero significant coefficient. Is classified into groups by that value, and the Huffman coding is performed by grouping the group identification number and the run length of the number of invalid coefficients having a quantized output of 0 sandwiched between the immediately preceding significant coefficients, Then, an isometric code is added to indicate which value in the group.

Generally, since a high frequency component in an oblique direction of an image has a low probability of occurrence, it is estimated that the latter half of G _ij after zigzag scanning is often all zero. Therefore, the variable length code obtained in this way can be expected to have a very high compression rate, and if a compression rate of a fraction of the average is assumed,
An image with almost no image quality deterioration can be restored.

On the other hand, in general, the transmission path has a predetermined transmission capacity per unit time, and in the case where one screen must be transmitted every predetermined period as in the case of transmitting a moving image, an output code Is desired to be a fixed number of bits in a screen unit or a pixel block unit.

Here, if the above-mentioned coefficient C is made large, G _ij
The probability that 0 becomes 0 increases, and the total number of encoded bits NB decreases. It is known that the relationship between the coefficient C and the total number of bits NB varies depending on the image, but in any case, it is a simple decreasing function, and an average image has a logarithmic curve as shown in FIG.

Therefore, a method for predicting the coefficient C0 for obtaining the desired total number of bits NBO has been presented by the above-mentioned JPEG or the like. That is, a certain coefficient C1 is first encoded, and the total number of bits nb1 of the code thus obtained is
Ask for. Predicted value C of C0 based on this nb1 and C1
2, the logarithmic curve shown in FIG.
1, nb1) and can be predicted.

By repeating this operation several times, an error code amount of about several% can be obtained with respect to the desired total bit number NB0.

[0015]

However, the process of repeatedly performing the coding to determine the value of the coefficient C0 as described above is a very time-consuming process, and one screen is displayed in a predetermined period like a moving image. It is not suitable for encoding devices that must be transmitted. In particular, such processing is not possible when handling an image signal having an extremely high bit rate such as a high definition television signal.

Further, in this type of apparatus, when the code is transmitted in a unit of a predetermined period such as one frame, only the DC component is transmitted first, and then the variable length encoded AC component is transmitted. Is desirable. This is because even if a code error occurs on the transmission path, the DC component is more likely to be protected. However, in order to perform such processing, a large amount of memory is required to change the transmission order, and this causes an increase in hardware scale.

Under the above background, the present invention quantizes the data obtained by converting the image information into the frequency domain, and quantizes the quantized converted data in a coding device that can perform high-speed processing. It is therefore an object of the present invention to provide an image coding apparatus capable of setting the data amount for each predetermined period to a desired data amount and capable of performing coding in consideration of the occurrence of code errors with a small hardware amount.

[0018]

According to the present invention, the converted data obtained by converting the image information into the frequency domain is quantized, and the quantized converted data is variable length coded. In the encoding device for converting, the parallelizing means for outputting the converted data having a time difference of a predetermined period in parallel to output the converted data of a plurality of channels, and the converted data of the plurality of channels output by the parallelizing means, respectively. The quantizing means for quantizing, and the data amount when at least the AC component in the converted data quantized by the first quantizer in the quantizing means is coded by the variable length coding, Calculating means for calculating in units of period; first coding means for variable-length coding at least an AC component in one of the conversion data of a plurality of channels quantized by the quantizing means; Control of the quantization step of the second quantizer to which the conversion data before the predetermined period is input with respect to the conversion data to be input to the first quantizer in accordance with the output of Generating means for generating a control coefficient, and second encoding means for encoding at least a DC component in the conversion data after the predetermined period with respect to the conversion data encoded by the first encoding means. And a time axis multiplexing means for multiplexing the output of the first encoding means and the output of the second encoding means in the same period prior to the output of the second encoding means. Prepared to be equipped.

[0019]

With the above configuration, the control coefficient of the second quantizing means is higher than that of the first quantizing means.
The value becomes close to the desired value, and by performing such processing in parallel and in multiple stages, it is possible to obtain a substantially desired control coefficient. Also, since it is not necessary to repeatedly perform encoding and calculation of control coefficients,
The processing can be performed at an extremely high speed, and processing of moving images and the like can be sufficiently applied. Further, since the parallelizing means is effectively used to adjust the transmission order of the DC component and the AC component, the transmission of the code in consideration of the occurrence of an error can be realized without increasing the amount of hardware.

[0020]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 is a block diagram showing a configuration of an encoding device to which the present invention is applied to a transmission device for transmitting a television signal as an embodiment of the present invention.

In the figure, reference numeral 20 denotes an analog television signal input terminal, and the television signal input from the terminal 20 is digitized into 8 bits by an A / D converter 22, and the block circuit of FIG. Perform the same operation as 4 (8 ×
8) The block formation circuit 26 divides the pixel block into (8 × 8) pixel blocks, and supplies each block to the DCT conversion circuit 28.

The pixel data D _{11 to} D ₈₈ of each block are DC
As in the case of FIG. 4, the T conversion circuit 28 converts the data matrix into the data matrix X _{11 to} X ₈₈ in the frequency domain and supplies the data matrix X _{11 to} X ₈₈ to the zigzag scanning circuit 30. The zigzag scanning circuit 30
Performs the same operation as 10 in FIG. 4 to convert the DCT-converted data matrices X _{11 to} X ₈₈ into X ₁₁ , X ₁₂ , X ₂₁ ,
X ₃₁ , X ₂₂ , X ₁₃ , X ₁₄ , X ₂₃ , X ₃₂ , X ₄₁ ... X ₈₅ , X
₈₆ , X ₇₇ , X ₆₈ , X ₇₈ , X ₈₇ , X ₈₈ are output in this order.

The quantization matrix generation circuit 36 generates the above-mentioned quantization matrices W _{11 to} W ₈₈ . However, the quantization matrix W ₁₁ to _W-88 Because the data that have already been zigzag scanned in the quantization circuit 32a~32e in this embodiment is also input is generated in an order corresponding to zigzag scanning,
It is supplied to the multiplication circuits 38a to 38e.

In the multiplier 38a, from the initial coefficient generating circuit,
The initial coefficient C1 is supplied as the above-mentioned coefficient (control coefficient) C. Here, in this embodiment, the initial coefficient C1 is "1".
And When the initial coefficient C1 is set to "1", W _ij = Q _ij, and thus the multiplication circuit 38a is unnecessary, and the quantization matrices W _{11 to} W ₈₈ can be directly input to the quantization circuit 32a. good.

In this way, the quantization circuit 32a obtains the quantization codes G1 _{11 to} G1 ₈₈ based on the control coefficient C1. The quantized conversion codes G1 _{11 to} G1 ₈₈ are input to the VLC 40a.

In this embodiment, VLCs 40a-40d are used.
Does not output the actual encoded data, but outputs only the total bit number information nb1 to nb4 for each screen when the same processing as the VLC 12 of FIG. 4 is performed on the AC component. Here, the total bit number information nb1 output from the VLC 40a is input to the coefficient calculation circuit 44a. Coefficient calculation circuits 44a to 44
d is total bit number information nb1 from VLCs 40a to 40d
~ Nb4 and the initial coefficient and the outputs C1 to C4 of the coefficient calculation circuits 44a to 44c are used to predict the control coefficient C0 corresponding to the desired total number of bits NB0, and C2 to C2 as the control coefficients, respectively.
Output C5. Here, the coefficient calculation circuits 44a to 44d
Represents the control coefficients C2 to C5 obtained by the conversion data for one screen input to the quantization circuits 32a to 32d as
The converted data for the screen is output at the timing of being input to the quantization circuits 32a to 32d. As will be described later, in the present embodiment, the DC component is equal-length coded, so that each VL is
In C40a-40d, the total amount of data after encoding only the AC component is calculated.

On the other hand, 34a to 34d are circuits (1 for delaying the output of the zigzag scanning circuit 30 for one screen (frame) period.
Therefore, the control coefficient C2 output from the coefficient calculation circuit 44a is input to the multiplier 38b at the timing when the conversion data for one screen used to obtain the control coefficient C2 is input to the quantization circuit 32b. To be done. Multiplication circuit 38
In (b), (W _ij × C) is calculated and input to the quantization circuit 32b. That is, the quantization circuit 32b performs the second quantization on the same screen, and the control coefficient C2
To obtain quantized codes G2 _{11 to} G2 ₈₈ . The quantized conversion codes G2 _{11 to} G2 ₈₈ are input to the VLC 40b.

Coefficient calculation circuits 44b to 44d and multiplication circuit 3
8c-38e, 1FDL34b-34, VLC40b-
The operations of 40d and the quantization circuits 32c to 32e are performed by the coefficient calculation circuit 44a, the multiplication circuit 38b, the 1FDL 34a,
The operation is similar to that of the VLC 40a and the quantizing circuit 32b, and the predicted value of the desired control coefficient for one screen is sequentially updated by these circuits.

As a result, the predicted value C5 of the control coefficient obtained from the coefficient calculation circuit 44d is the desired total number of bits NB.
It should have converged to a value very close to the control coefficient C0 corresponding to 0, and in this embodiment, this control coefficient C5 is supplied to the multiplication circuit 38e as the final control coefficient C. The output of the multiplier 38e is supplied to the quantization circuit 32e, and the quantization circuit 32e outputs the output of the 1FDL 34d, that is, 4
At least an AC component in the converted data frame period delayed quantized, VLC40e as G5 ₁₂ ~G5 ₈₈
Supply to.

The VLC 40e has the AC components G5 _{12 to} G5.
_{The 88 is} actually encoded as described in FIG. 4, and the encoded data (DATA) is output.

On the other hand, for the DC component, 1FDL34c
Is extracted and extracted by the DC extraction circuit 51 and input to the quantizer 52. In the quantizer 52, the above-mentioned coefficient C
Regardless of, the DC component X ₁₁ is quantized in a predetermined quantization step and input to the encoding circuit 54.

The coding circuit 54 performs equal-length coding on the DC component as described above by predictive difference coding or the like. Here, the data of the DC component that has been encoded in the encoding circuit 54 in the same length and the data of the AC component that has been subjected to the variable length encoding in the VLC 40e as described above are input to the buffer memories 56 and 46, respectively.

The reading of the encoded data from the memories 46 and 56 is controlled by the memory control circuit 58. For the encoded data of the same frame, all the DC component encoded data of one frame are read out first, and next. It is controlled to read the AC component encoded data of the same frame.

Here, a time relationship between writing and reading of stored data in the memories 46 and 56 will be described.

FIG. 2 shows writing of data into the memory 46, that is, writing of AC component encoded data (AC), writing of data into the memory 56, that is, writing of DC component encoded data (DC), and both memories. It is a figure showing the time relation of the reading of the data from.

DC component encoded data (DATA-2)
Quantization can be performed prior to the determination of the final coefficient C in the factor calculation circuit 44 by performing the quantization in a constant quantization step regardless of the coefficient C described above.

Therefore, in FIG. 1, the final stage 1FD
Before the L34d, the DC component data is separated and extracted by the DC extraction circuit 50, and the quantization is performed by the quantization circuit 52.

As a result, during the period when the AC component coded data (AC) of the frame of interest is written in the memory 46, the DC component coded data (DC) of the same frame already stored in the memory 56, It is possible to read the AC component encoded data (AC) in advance.

On the other hand, FIG. 3 does not use the DC extraction circuit 51,
AC component coded data (A when the AC component data and the DC component data are quantized and encoded in the same frame period)
FIG. 6C is a diagram showing a time relationship between writing and reading of data corresponding to DC component encoded data (DC).

In this case, since the data transmission order is changed and the reading is performed with a delay of one frame period with respect to the writing, a memory capacity of 2 frames for AC is required.

According to the above description, the memory capacity required for changing the transmission order of data on a frame-by-frame basis requires two frames according to the normal configuration. However, in this embodiment, the AC component is used. Regarding the encoded data (AC), it is possible to change the data transmission order only by providing a memory having a capacity of one frame.

Needless to say, the memories 46 and 56 also have a buffer function for reading data at a predetermined bit rate.

Further, at this time, the memory control circuit 58 slightly delays the start of reading the data in units of one frame from the start of the writing so that the read address of the data from the memory 46 is not overtaken by the write address. Control.

The AC component coded data (AC) and the DC component coded data (DC) read from the memory 46 and the memory 56 as described above are multiplexed with the final coefficient C by the multiplexer 48, It is output to the transmission line through the terminal 60 at a predetermined bit rate.

From the above description, the coefficient C is not fed back at all according to the above-mentioned configuration.
Even though the control coefficient C is calculated 5 times for the same screen, the period required for the processing for one screen is the same as the processing for keeping the control coefficient C constant, and extremely high speed processing becomes possible. There is.

Further, due to the small memory capacity, the data transmission order is changed, that is, DC component encoded data (DC).
It is possible to postpone.

In the above embodiment, the coefficient calculation circuit 44 is used.
b to 44d are coefficients C2 to C4 output from the coefficient calculation circuits 44a to 44c and quantization according to the coefficients C2 to C4,
Total bit number information nb2 to nb4 when variable length coding is performed
Although the desired control circuit C0 is predicted by using, it is possible to make a more accurate prediction by using the coefficient and total bit number information of the preceding stage. For example, the coefficient calculation circuit 44b
When the coefficients C1 and C2 and the total bit number information nb1 and nb2 are used to calculate the coefficient C3 in, the coefficient C0 can be predicted more accurately.

Further, in the present embodiment, the control coefficient F is determined for each screen in order to realize extremely high-speed processing, but if there is some margin in processing time, this control is performed. It is also possible to make the unit (period) that determines the value of the coefficient F small (short).

[0050]

As described above, according to the image coding apparatus of the present invention, the data obtained by converting the image information into the frequency domain is quantized, and the quantized converted data is variable length coded. In the encoding device described above, the amount of data for each predetermined period can be set to a desired amount of data, and processing can be performed at extremely high speed.

Further, it is possible to reduce the memory capacity for changing the transmission order of the data, which is useful for the error countermeasure at the time of transmission, and to realize the image coding apparatus for which the increase of the hardware scale is suppressed to the minimum.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image coding apparatus as an embodiment of the present invention.

FIG. 2 is a diagram for explaining a control operation of a data transmission order in the device of FIG.

FIG. 3 is a diagram for explaining a control operation of a data transmission sequence for a DC component and an AC component obtained at the same time.

FIG. 4 is a block diagram for explaining a schematic configuration of a conventional coding method using DCT transform.

FIG. 5 is a diagram showing a pixel block made up of (8 × 8) image data.

FIG. 6 is a diagram showing a DCT-converted data matrix.

FIG. 7 is a diagram showing a quantization matrix showing weighting of a quantization step size.

FIG. 8 is a diagram showing a relationship between a coefficient C and a total number of bits.

[Explanation of symbols]

 26 Blocking circuit 30 DCT conversion circuit 32a to 32e Quantization circuit 34a to 34d 1 frame period delay circuit 36 Quantization matrix generation circuit 38a to 38e Multiplication circuit 40a to 40e Variable length coding circuit 42 Initial coefficient generation circuit 44a to 44d Coefficient Operation circuit 46, 56 Buffer memory 48 Multiplexer 51 GC (DC component) extraction circuit 52 Quantization circuit 54 Encoding circuit 58 Buffer control circuit

Claims (1)

[Claims] 1. An encoding device for quantizing transform data obtained by transforming image information into a frequency domain and performing variable length coding on the quantized transform data, wherein the transform data have a time difference of a predetermined period from each other. In parallel to output converted data of a plurality of channels, a quantizing means for quantizing the converted data of a plurality of channels output from the parallelizing means, and a first quantum in the quantizing means. A data amount when at least the AC component in the conversion data quantized by the quantizer is coded by the variable-length coding; First encoding means for variable-length encoding at least an AC component in one of the conversion data of a plurality of channels; and a conversion input to the first quantizer in accordance with an output of the arithmetic means. Coefficient generating means for generating a control coefficient for controlling the quantization step of the second quantizer to which the conversion data before the predetermined period is input, in units of the predetermined period; and the first encoding. Second encoding means for encoding at least a direct current component in the conversion data after the predetermined period with respect to the conversion data encoded by the means, and an output of the first encoding means in the same period. An image coding apparatus comprising: a time-axis multiplexing unit that multiplexes the output of the second encoding unit with the output of the second encoding unit preceding.