JPH05122201A - Communication circuit device - Google Patents

Abstract

PURPOSE:To simplify the configuration of the communication circuit device which executes simultaneous communication through a single communication line with respect to the communication circuit device ensuring two-way communication through the single communication line. CONSTITUTION:The communication circuit device D1 (D2) provided between computers 1, 2 via a communication line 3 is provided with transistors(TRs) T1, T2 (T11, T12) outputting a transmission signal from the computer 1 (2) to the communication line 3, TRs T3, T4 (T13, T14) discriminating the state of the transmission signal from its own computer 1 (2) and selecting a reference voltage Vref based on the discrimination, with resistors R12-R14 (R32-R34), and with a comparator 8 (13) connecting to the communication line 3 and comparing a transmission reception signal on the communication line 3 with the reference voltage Vref selected by the TRs T3, T4, T13, T14 and the resistors R12-R14 and R32-R34 so as to discriminate the presence of a reception signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication circuit device, and more particularly to a communication circuit device for ensuring bidirectional communication on a single-line communication path.

[0002]

2. Description of the Related Art Conventionally, a number of computers have been used in car electronics, and the computers communicate with each other. In car electronics, the number of signal lines is large, and it is necessary to reduce the number. Here, for example, as shown in FIG. 9, in a conventional communication system 30, a transmission circuit 31 and a reception circuit 32 are built in computers 33a and 33b, and a pair of signal lines 34a and 34b and a ground line 35 are provided between the computers 33a. , 33b are connected. That is,
One signal line 34a connects the transmitting circuit 31 of one computer 33a and the other receiving circuit 32, and the other signal line 34b connects the receiving circuit 3 of one computer 33a.
2 and the other transmission circuit 31 are connected. Then, the computers 33a and 33b are connected by the grounding line 35 so that the grounding levels are the same. Therefore, communication between the computers 33a and 33b can be performed simultaneously. However, in this case, the computer 33
communication lines 34a, 34 for communication between a and 33b
Three b are required including the ground wire 35.

A communication system 36 as shown in FIG. 10 has been proposed for the purpose of reducing the communication lines 34a and 34b. The communication system 36 is configured by connecting a transmission circuit 31 and a reception circuit 32 built in the computers 38a and 38b together by a single communication line 37. However, in this case, the communication line 37 and the ground line 35 can be formed by two lines,
The mutual communication between the computers 38a and 38b cannot be performed simultaneously.

Therefore, as a communication system capable of simultaneously communicating with one communication line, Japanese Patent Laid-Open No. 58-3604.
The one shown in Japanese Patent Publication No. 5 has been proposed. In this communication system, the level of one communication line is compared and detected by a pair of comparators provided at points A and B, and the result is output to a determination circuit. With this determination circuit, points A and B detect only the reception signal of the other party from which the transmission signal of its own is subtracted, and perform simultaneous communication.

[0005]

However, when performing simultaneous communication, two comparators are used to subtract the transmission signal of itself between the points A and B to extract the reception signal of the other side. However, there is a problem that the circuit configuration becomes complicated accordingly.

The present invention has been made in order to solve the above problems, and an object thereof is to provide a communication circuit device capable of simplifying the configuration of a communication circuit device for performing simultaneous communication by a single-wire communication path. Especially.

[0007]

In order to solve the above problems, the present invention provides a communication circuit device provided via a single-wire communication path between signal processing devices, wherein a transmission signal is transmitted from the signal processing device. A signal output means for outputting to a single wire communication path, a judgment reference value switching means for judging the state of a transmission signal from its own signal processing device and switching a judgment reference value based on the judgment, and connected to the single wire communication path. Comparing and determining processing means for comparing the determination reference value switched by the determination reference value switching means with a transmission / reception signal of a single-wire communication path and determining the presence or absence of a received signal based on the comparison result. Use as a summary.

[0008]

The signal output means outputs the transmission signal to the signal processing device on the other side through the single line communication path and the communication circuit based on the signal processing device. The judgment reference value switching means judges the state of the transmission signal from its own signal processing apparatus, and switches the judgment reference value when it judges that the signal processing apparatus of its own is a high level transmission signal. The comparison / discrimination processing means compares and discriminates the transmission / reception signal input from the single-line communication path and the switched judgment reference value. At this time, if the transmission / reception signal does not exceed the switched determination reference value, the comparison / determination processing means determines that the received signal is in a low level state, and if the transmission / reception signal exceeds the switched determination reference value, the comparison / determination processing. The means determines that the received signal is in the high level state.

Further, the judgment reference value switching means does not switch the judgment reference value when it judges that the signal processing device of its own is a transmission signal in a high level state. Then, the comparison / determination processing means compares and determines the transmission / reception signal input from the single-wire communication path and the determination reference value that has not been switched. At this time, if the transmission / reception signal does not exceed the non-switched determination reference value, the comparison / determination processing means determines that the reception signal is in a low level state, and if the transmission / reception signal exceeds the non-switchable determination reference value, the comparison / determination processing is performed. The processing means determines that the received signal is in a high level state.

Therefore, by switching the comparison reference value, only one comparison / discrimination processing means is provided, and simultaneous communication is performed by the single-wire communication path.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is embodied in computer communication will be described below with reference to FIGS.

As shown in FIG. 1, a pair of computers 1 and 2 as a signal processing device are connected to each other by a single communication line 3 as a single line communication path. The pair of computers 1 and 2 are connected to each other by a ground line 4 and have the same ground level. That is, the communication line 3 is connected to the input / output terminals 1a and 2a provided on the pair of computers 1 and 2, and the ground wire 4 is connected to the ground terminals 1b and 2b provided on the pair of computers 1 and 2. ing.

Next, the configuration of the pair of computers 1 and 2 will be described in detail. Since the configuration of the pair of computers 1 and 2 is the same, only the configuration of the computer 1 will be described in detail.

An arithmetic processing unit 5 for performing arithmetic processing and a communication circuit device D1 are provided inside the computer 1, and a transmission circuit 6 for outputting a transmission signal and a counterpart computer are provided in the arithmetic processing unit 5. A receiving circuit 7 is provided for receiving the received signal from 2.

The transmission circuit 6 in the arithmetic processing unit 5 is connected to the base of a transistor T1 as a signal output means via a resistor R1 of the communication circuit device D1. A resistor R grounded between the transistor T1 and the resistor R1.
2 is connected. The collector of the transistor T1 is connected to the base of a transistor T2 as a pnp type signal output means via a resistor R3, and the emitter of the transistor T1 is grounded. Further, the emitter of the transistor T2 is a power source (in the present embodiment, 5
[V]) is connected to Vcc, and the collector is connected to the input / output terminal 1a via a resistor R5. Further, a bias resistor R4 is provided between the base and emitter of the transistor T2.
Are connected. Further, the resistor R5 and the input / output terminal 1
A grounded resistor R6 is connected between a and a.

A base of a transistor T3 as a judgment reference value switching means is connected between the transmission circuit 6 and the resistor R1 via a resistor R7. A grounded resistor R8 is connected between the resistor R7 and the base of the transistor T3. The collector of the transistor T3 is connected via a resistor R9 to the base of a transistor T4 as a judgment reference value switching means. Also, the transistor T3
A resistor R10 connected to the power source Vcc is connected between the collector of the resistor R9 and the resistor R9, and the emitter of the transistor T3 is grounded. A grounded resistor R11 is connected between the resistor R9 and the base of the transistor T4. The collector of the transistor T4 is connected to the resistor R12 as the judgment reference value switching means, and the emitter is grounded. The resistor R12 is connected between resistors R13 and R14 which are connected in series and serve as a judgment reference value switching unit. The resistor R13 is connected to the power source Vcc, and the resistor R14 is grounded.

Further, a positive electrode on the input side of a comparator 8 as a comparison / discrimination processing means is connected between the resistors R5 and R6,
The negative electrode on the input side is connected between the resistors R13 and R14. The output side of the comparator 8 is connected to the receiving circuit 7 in the arithmetic processing section 5. A resistor R connected to the power supply VCC is provided between the output side of the comparator 8 and the receiving circuit 7.
15 is connected. Further, in this embodiment, the resistance values of the resistors R5, R6, R25 and R26 are all set to be the same.

The comparator 8 is adapted to detect the voltage level VS of the communication line 3. Then, the comparator 8 compares this voltage level VS with a reference voltage Verf as a judgment reference value generated between the resistors R13 and R14, and when the voltage level VS exceeds the reference voltage Vref, the other side When it is determined that the transmission signal from the computer 2 is in the H level, the output side is set to the H level, and when the voltage level VS does not exceed the reference voltage Vref, the transmission signal from the other computer 2 is at the L level. It is determined that the output side is grounded and is set to the L level.

Further, when the transmission signal from the transmission circuit 11 of the computer 2 is at L level, the transmission signal from the transmission circuit 6 of the computer 1 is transmitted to the other computer 2
In the H level (high potential) state for output to the transistor T1, the transistor T1 is turned on by the potential predetermined by the resistance ratio of the resistors R1 and R2. Therefore, the base of the transistor T2 is grounded, the transistor R2 is turned on by the bias resistor R4, and the power source Vcc is output to the resistor R5. As a result, the circuit shown in FIG. 5 is formed. At this time, since the resistors R5, R6, and R26 all have the same resistance value, the voltage level VS of the communication line 3 is Vs.
S = 5/3 [V].

Further, when the transmission signal from the transmission circuit 6 of the computer 1 is at the H level and the transmission signal is output from the transmission circuit 11 of the computer 2 to the counterpart computer 1, if the H level (high potential) state is reached. On the contrary, the transistors T11 and T12 are turned on. Therefore, the resistance R
Since 6, R25 and R26 all have the same resistance value, the voltage level VS of the communication line 3 is VS = 5 as in the above case.
It becomes / 3 [V].

When the transmission signals from the transmission circuits 6 and 11 of the computers 1 and 2 are at the H level, the transistor T in the computers 1 and 2 is
2 and T12 are turned on, the circuit shown in FIG. 6 is formed. At this time, the voltage level VS of the communication line 3 is VS = 5 /
It becomes 2 [V].

Therefore, FIG. 3 shows changes in the voltage level VS of the communication line 3 due to changes in the transmission signals of the transmission circuits 6 and 11 in the computers 1 and 2. As can be seen from FIG. 3, when the transmission signals from the transmission circuits 6 and 11 of the computers 1 and 2 are in the L level, the voltage level VS becomes 0 [V], and one of the transmission circuits 6 and When the transmission signal from 11 is at the H level, the voltage level V
S becomes 5/3 [V]. Furthermore, the mutual transmission circuits 6, 1
When the transmission signal from 1 is at the H level, the voltage level VS becomes 5/2 [V]. This voltage level VS
Are respectively detected by the comparators 8 and 13.

Further, the reference voltage Vref of the comparators 8 and 13 is
Changes depending on the presence or absence of a transmission signal.
That is, in the computer 1, the transistor T3 is turned on when the transmission signal from the transmission circuit 6 is at the H level. Therefore, the power supply Vcc has a resistance R
The state shown in FIG. 7 is formed because the transistor T4 is turned off and the transistor T4 is turned off.

At this time, the reference voltage Vref is the resistance R13,
The reference voltage Vref is determined by the resistance ratio of R14, and the reference voltage Vref is Vref1 = [R14 / (R13
+ R14)] × 5 [V]. That is, FIG.
As shown in, the first reference voltage Vref1 when the transmission signal is output from the transmission circuit 6 is 5/3 [V] <Vre
Resistance R1 so that it is set in the range of f1 <5/2 [V]
The resistance values of R3 and R14 are selected and set in advance. Therefore, the first reference voltage Vref1 set within the above range and the voltage level VS are compared by the comparator 8.

Further, when the transmission signal from the transmission circuit 6 is at L level, the transistor T3 is turned off, so that the power supply Vcc is applied to the resistors R9 to R11 and the transistor T4 is turned on. Therefore, the resistor R12 is grounded, and the circuit shown in FIG. 8 is formed.

At this time, the reference voltage Vref is the resistance R12-
Determined by the resistance ratio of R14, the reference voltage Vref is the second reference voltage Vref2,

[0027]

[Equation 1]

It is calculated by That is, as shown in FIG. 4, the second reference voltage Vref2 when the transmission signal from the transmission circuit 6 is in the L level is 0 [V] <Vref2 <5.
The resistors R12 to R1 are set in the range of / 3 [V].
A resistance value of 4 is selected and set in advance. The second reference voltage Vref2 set within the above range and the voltage level VS are compared by the comparator 8.

The reference voltage Vre in the computer 2
f is also connected to the first and second reference voltages Vre by the resistors R32 to R34.
f1 and Vref2 are switched to the first and second reference voltages Vre
The resistance values of f1 and Vref2 are selected and set in advance so as to be set within the same range as above.

Next, the operation of the communication circuit devices D1 and D2 configured as described above will be described. Since the transmission / reception operations of the communication circuit devices D1 and D2 provided in the computers 1 and 2 are the same, only the transmission / reception operation of the communication circuit device D1 in the computer 1 will be described.

First, the transmission circuits 6 of the computers 1 and 2
When the transmission signals from 11 are in the L level, the transistors T1 and T11 are turned off, so that the power supply Vcc is not output from the transistors T2 and T12 to the communication line 3. Therefore, as shown in FIG. 3, the comparator 8 of the computer 1 detects the potential level VS of 0 [V] from the communication line 3.

Further, since the transmission signal from the transmission circuit 6 of the computer 1 is in the L level state, the transistor T3
Does not turn on, and the transistor T4 turns on. Therefore, since the resistor R12 is grounded, the circuit shown in FIG. 8 is formed, and the reference voltage Vref is set to the second reference voltage Vref2 shown in FIG. 4 as described above. Therefore, the comparator 8 compares the second reference voltage Vref2 with the potential level VS. In this case, the potential level VS is 0 as shown in FIG.
Since it becomes [V], it does not exceed the second reference voltage Vref2. As a result, the comparator 8 sets the output side to the L level, so that the reception signal of the L level is input to the reception circuit 7.

Then, when the transmission signal from the transmission circuit 11 of the computer 2 becomes the H level state, the transistor T12 is turned on as described above, and the power source Vcc changes the resistance R25.
Is output to. Therefore, the potential level VS of the communication line 3 is changed by the circuit formed by the resistors R6, R25 and R26.
Becomes 5/3 [V], and this potential level VS is set to the comparator 8
To detect. At this time, the comparator 8 outputs the second reference voltage Verf2.
2 and the potential level VS, the potential level VS exceeds the second reference voltage Verf2 as shown in FIG. As a result, the comparator 8 outputs the H level power supply Vcc to the receiving circuit 7 with the output side at the H level. That is, it means that the transmission signal from the computer 2 is received.

Next, the transmission circuits 6 of the computers 1 and 2
When the transmission signals from 11 reach the H level with each other, the transistors T2 and T12 are turned on and the power supply Vcc is output to the resistors R5 and R25. As a result, the circuit shown in FIG. 6 is formed, so that the potential level VS of the communication line 3 becomes 5/2 [V], and the comparator 8 detects this potential level VS.

Further, since the transmission signal from the transmission circuit 6 of the computer 1 is in the H level state, the transistor T3 is turned on, the power source Vcc is grounded through the resistor R9, and the transistor T4 is turned off. The circuit shown in is constructed. Therefore, the reference voltage Vref input to the comparator 8
Is set to the first reference voltage Vref1. And the comparator 8
Is the potential level VS of 5/2 [V] and the first reference voltage V
Compare with ref1. At this time, the potential level VS exceeds the first reference voltage Vref1 as shown in FIGS. As a result, the comparator 8 sets the output side to the H level, so that the power source V
CC is output to the receiving circuit 7. That is, the H-level transmission signal from the computer 2 is input.

Further, when the transmission signal from the transmission circuit 6 of the computer 1 is in the H level and the transmission signal from the transmission circuit 11 of the computer 2 is in the L level,
The transistor T12 is turned off to form the circuit shown in FIG. Therefore, the potential level VS of the communication line 3 is 5/3
[V], and the comparator 8 detects this potential level VS.

Therefore, the reference voltage V input to the comparator 8
Since ref is set to the first reference voltage Vref1 as shown in FIG. 4, the comparator 8 compares the potential level VS of 5/3 [V] with the first reference voltage Vref1. At this time, since the potential level VS does not exceed the first reference voltage Vref1 as shown in FIGS. 2 and 4, the comparator 8 sets the output side to the L level. Therefore, the L level reception signal is input to the reception circuit 7.

The reception circuit 12 of the computer 2 can also receive the transmission signal of the transmission circuit 6 of the computer 1, like the reception circuit 7 of the computer 1.

Further, in the simultaneous communication, when the transmission signals from the transmission circuits 6 and 11 of the computers 1 and 2 are at the L level and the transmission signals are at the H level, the reference values are used as boundaries. Reception circuit 7, 12
Can easily judge these. However, when only one of the transmission signals is in the H level state,
It cannot be judged by one reference value. In the present invention, the reference voltage Vref, which is a predetermined reference value, is switched based on the presence / absence of the output of its own transmission signal, so that the receiving circuits 7 and 12 do not detect their own transmission signal as a reception signal and reliably receive it. Only the signal can be detected.

As a result, simultaneous communication can be performed by one communication line 3. Also, the reference voltage Vref of the comparator 8
Based on the judgment as to whether or not the own computers 1 and 2 output the transmission signals, the first and second reference voltages Vref1 and Vre
Since it is switched to f1, the communication circuit devices D1 and D2 can be configured by one comparator 8 unlike the conventional case. Therefore, the circuit configurations of the communication circuit devices D1 and D3 can be simplified.

When this communication system is applied to computer communication of car electronics, the body can be grounded, so that it is not necessary to connect the computers with a grounding wire, and one communication line 3 is completely used. Can be

Further, according to the present invention, the reference of the reference voltage Vref is switched based on the states of the transmission signals from the transmission circuits 6 and 11 of the computers 1 and 2, and the computers 1 and 2 on the other side are switched.
However, the circuit configuration is not limited to the above because it is only necessary to be able to receive the transmission signal of.

[0043]

As described above in detail, according to the present invention, there is an excellent effect that the structure of a communication circuit device for performing simultaneous communication through a single-line communication path can be simplified.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram showing a communication system between computers containing a communication circuit device according to the present invention.

FIG. 2 is a characteristic diagram showing that a reception circuit of a communication circuit device in a computer receives a reception signal.

FIG. 3 is a correspondence diagram showing that the potential level of a communication line changes depending on the level of a transmission signal from each computer.

FIG. 4 is an explanatory diagram showing that the reference voltage is switched and set to the first and second reference voltages based on the level of the transmission signal output from each computer.

FIG. 5 is a circuit configuration diagram configured when a transmission signal from one computer becomes H level.

FIG. 6 is a circuit configuration diagram that is formed when transmission signals from the computers are at an H level.

FIG. 7 is a circuit diagram illustrating a circuit that sets a reference voltage when a transmission signal from the transmission circuit becomes H level.

FIG. 8 is a circuit diagram illustrating a circuit that sets a reference voltage when a transmission signal from a transmission circuit becomes H level.

FIG. 9 is a system configuration diagram showing a conventional communication circuit device.

FIG. 10 is a system configuration diagram showing a conventional communication circuit device.

[Description of Reference Signs] 1, ... Computer as signal processing device, 3 ... Communication line as single-line communication path, 8 ... Comparator as comparison / determination processing means, D1, D2 ... Communication circuit device, T1, T2, T1
1, T12 ... Transistor as signal output means, Vre
f ... Reference voltage as judgment reference value, T3, T4, T1
3, T14 ... Transistors as judgment reference value switching means, R12 to R14, R32 to R34 ... Resistors as judgment reference value switching means

Claims (1)

[Claims] 1. A communication circuit device provided between respective signal processing devices via a single-wire communication path, and a signal output means for outputting from the signal processing device to the single-wire communication path, and a signal in its own signal processing device. Judgment reference value switching means for judging the state of the transmission signal from the output means and switching the judgment reference value based on the judgment, and a judgment reference value connected by the single line communication path and switched by the judgment reference value switching means. And a transmission / reception signal of a single-line communication path, and a comparison / discrimination processing means for discriminating the presence / absence of a reception signal based on the comparison result.