JPH05122025A - Synchronizing signal generation circuit - Google Patents

Abstract

PURPOSE:To make it possible to continuously generate and output a pulse signal to be inputted for only a short time by a prescribed interval and a pulse synchronized with a high accuracy by providing a clock generation means, first and second count means and a phase adjusting means. CONSTITUTION:An input pulse signal is one to be inputted repeatingly, for instance, one which is to be inputted for only a short time and is to be again inputted for a short time after a prescribed time inverval passes. A first counter 10 counts the time interval of this pulse plural times, using a clock pulse 14 and a CPU 18 calculates the average of the plural counts. A second counters 15-1 to 3 count this average value by using the clock pulse 14 and continuously perform a pulse output at the time interval corresponding to the average value. Further, the phase is adjusted by phase adjusting means 17-1 to 3 making the phase of a pulse output from the second counters 15-1 to 3 to coincide with the phase of an input pulse and outputting the phase, and the pulse output becomes a signal synchronized with the input pulse with high accuracy.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal generating circuit, and more particularly to a synchronizing signal generating circuit capable of continuously generating a pulse signal synchronized with a target input pulse signal with high accuracy.

[0002]

2. Description of the Related Art Conventionally, another SSR (Secondary Surveillance Radar) which does not have a transmitter itself but has a transmitter is used.
rveillance Radar) A passive SSR device that detects the position of an aircraft or the like by intercepting an SSR response radio wave transmitted from an SSR transponder mounted on an aircraft in response to an SSR interrogation radio wave emitted from a site is known. ing. Further, by receiving the radio waves emitted from the radio wave transmission site such as the SSR site, the azimuth and distance of the moving object viewed from the radio wave transmission site or their changes are detected, and the movement based on the detection information is detected. There is known a position recognition device capable of detecting the position of an object, that is, the device itself. These passive SSR devices and position recognizing devices are disclosed in, for example, JP-A-60-222782, JP-A-63-266381, and JP-A-63-263.
298084, JP-A-64-35287,
JP-A-64-35289 and JP-A-64-3
It is disclosed in Japanese Patent No. 5290.

In such a passive SSR device and position recognizing device, a pulse signal emitted from an SSR site or a radio wave transmission site is input, and a pulse signal which is synchronized with the pulse signal with high precision is continuously generated. A generator circuit is used. The input pulse signal is SSR
It is placed on the radio wave transmitted from the rotating antenna at the site or radio wave transmission site. Therefore, the receiving side detects this pulse signal at intervals of about 4 seconds (rotation period of the rotating antenna), for example. The synchronization signal generation circuit continuously outputs a signal synchronized with a pulse signal input for a short time at such a predetermined interval, that is, a pulse signal substantially the same as a pulse signal emitted from an SSR site or a radio wave transmission site. That is, the output signal is generated and output even when the input pulse signal is not received. This synchronization signal is used for position detection processing in a passive SSR device or position recognition device.

As such a synchronizing signal generating circuit, conventionally, for example, a circuit in which a time difference (deviation) from a reference signal is recognized as an analog voltage and a voltage controlled crystal oscillator (VCO) repeatedly generates a synchronizing signal is used. It was

[0005]

However, in such a sync signal generating circuit using a VCO, since the analog signal processing is performed, there is a deterioration in the synchronization accuracy and a decrease in the S / N ratio due to drift or the like. On the other hand, in the above-mentioned passive SSR device and position recognition device, in order to detect the position with high accuracy, a circuit capable of generating a synchronization signal with higher accuracy is required.

In view of the above circumstances, an object of the present invention is to provide a synchronizing signal generating circuit capable of continuously generating and outputting a pulse signal which is synchronized with a pulse signal input at a predetermined interval for a short time with high accuracy. To do.

[0007]

In order to achieve the above object, the present invention inputs a pulse signal which is periodically repeated for a short time and continuously generates a synchronizing pulse signal which is synchronized with the pulse signal. A synchronizing signal generating circuit for generating a clock pulse of a predetermined cycle;
First inputting an input pulse signal and counting a plurality of pulse intervals of the input pulse signal using the clock pulse
Counting means, a calculating means for calculating an average value of the counting results of the first counting means a plurality of times, the average value is counted using the clock pulse, and the counting is continued at a time interval corresponding to the average value. The present invention is characterized in that it is provided with a second counting means for selectively outputting a pulse, and a phase adjusting means for outputting the pulse output from the second counting means by matching the phase of the pulse output with the phase of the input pulse.

Further, it is preferable to provide a gate circuit that opens and closes according to the pulse interval of the input pulse signal so that only the significant pulse portion of the input pulse signal is input to the first counting means.

[0009]

The input pulse signal is a signal which is repeatedly input, for example, for a short time and then for a short time again after a predetermined time interval. The one input for a short time is a pulse signal having several pulses (for example, 10 to 30 pulses) repeated at a predetermined time interval. The first counting means counts the time interval of this pulse using the clock pulse from the clock generating means. This counting is performed multiple times. The average of the results of the plurality of counts is calculated by the calculating means. The calculated average value is a value corresponding to the pulse interval of the input pulse signal, and is accurate because it is an average of a plurality of counts. The second counting means counts the average value using the clock pulse and continuously outputs the pulse at time intervals corresponding to the average value. Since the average value is a value that expresses the pulse interval of the input pulse signal with high accuracy, the pulse interval of this continuous pulse output is almost equal to the pulse interval of the input pulse signal. Furthermore, the second
The phase is adjusted by the phase adjusting means for outputting the phase of the pulse output from the counting means in agreement with the phase of the input pulse, and the final synchronous output is a signal whose frequency and phase are synchronized with the input pulse with high accuracy. Becomes

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 6 shows the structure of a passive SSR device to which the synchronizing signal generating circuit of the present invention is applied. Figure 7
FIG. 4 is an explanatory diagram for explaining the operating principle of this passive SSR device.

In FIG. 7, PH, PN, and PY are SSR sites for transmitting interrogation radio waves, such as airports, and PR is a passive S type.
The installation position of the SR device is shown. S indicates an aircraft or the like. In the passive SSR site PR, another SSR site P
Interrogation radio waves from H, PN, PY and response radio waves transmitted from the aircraft S are received. Then, for this response radio wave, the propagation time from the transmission of the inquiry radio wave to the reception of the response radio wave is measured. This propagation time is, for example, the distance LH1 from the SSR site, for example, the airport PH from the airport PH to the aircraft S, and the distance PH2 from the aircraft S to the receiving point PR.
Corresponds to the sum LH of. That is, the aircraft S has the SSR site PH and the reception point PR as two focal points and has the distance LH.
It exists at one point on an ellipse EH having a major axis of (= LH1 + LH2). At the same time, the aircraft S is
Ellipse E determined by the same relationship for sites PN and PY
It exists on N and EY. Therefore, these ellipses E
If the intersection of H, EN and EY is calculated, this is the position of the aircraft S.

The passive SSR device shown in FIG. 6 executes the operation based on the above-described principle to calculate the position of the aircraft S. This device includes an omnidirectional antenna 111 and a receiver 1.
12, local oscillator 113, parabolic antenna 121, 1
22, 123, receivers 131, 132, 133, synchronization signal generation circuits 141, 142, 143, data detection circuit 1
51, 152, 153, correlation circuits 161, 162, 16
3, central processing unit (CPU) 170, keyboard 17
1, and a display 172. The antenna 111, the receiver 112, and the local oscillator 113 are
It is for receiving the response signal transmitted from the transponder mounted on the aircraft S. Antenna 121,
122, 123, receivers 131, 132, 133, synchronization signal generation circuits 141, 142, 143, data detection circuits 151, 152, 153, and correlation circuits 161, 16
2, 163 are provided one by one corresponding to each of the three SSR sites PH, PN, PY.

At the SSR site PH (PN, PY), the inquiry signal is repeatedly transmitted at a predetermined cycle (for example, 200 to 450 Hz). The interrogation signal is placed on a beam-shaped radio wave transmitted from a rotating antenna that rotates at a predetermined cycle (for example, 4 seconds or 10 seconds). The antenna 121 (122, 123) is the SSR site PH.
It is installed toward (PN, PY). And the S
In the vicinity of the rotating antenna of the transmitter of the interrogator of the SR site PH (PN, PY) facing the device PR at predetermined intervals, the SSR is centered around this facing time.
An interrogation signal (a plurality of repetitive pulse signals) is received while being determined by the beam width of the antenna. Receiver 131 (132, 13
3) amplifies the pulse signal from the antenna 121 (122, 123) to generate a synchronization signal generation circuit 141 (14
2, 143).

Sync signal generation circuit 141 (142, 14)
3) generates a pulse TRGH (TRGN, TRGY) synchronized with the interrogation signal transmission timing with high accuracy.
Details of the circuit 141 (142, 143) will be described later.
Further, the circuit 141 (142, 143) discriminates the mode MODE of the inquiry signal and sends it to the CPU 170.

Data detection circuit 151 (152, 153)
Is the synchronization pulse TRG from the output signal of the receiver 112.
The reception timing of the response signal based on H (TRGN, TRGY), that is, the inquiry signal is the SSR site P.
SS assuming transmission from H (PN, PY)
The distance LH (LN, LY) from the R site PH (PN, PY) to the device PR through the aircraft S is detected, and the output signal is detected to extract the code CODE carried in the response signal. For example, the transmission interval of the inquiry radio wave is 5
If it is about ms, the movement amount of the aircraft S during this period is 1 hour / hour.
Even at 000 km, it is about 1.4 m. Therefore, the propagation time of the response radio wave, that is, the distance LH to several consecutive inquiry radio waves transmitted from the same SSR site is substantially constant.

The correlation circuit 161 (162, 163) outputs a response signal which is almost constant for several synchronization pulses TRGH (TRGN, TRGY) in which the distance LH (LN, LY) is continuous, to the SSR site PH (PN, PY). ), It discriminates as a response signal to the interrogation signal sent from the device, and the reception timing (distance) of this response signal and the code data C
The ODE is sent to the CPU 170.

The CPU 170 is composed of a microprocessor and the like, and has a synchronizing signal generating circuit 141 (142, 1).
43), the correlation circuit 161 (162, 163) and the arithmetic processing according to various data supplied from the keyboard 171. For example, the position of the aircraft S is calculated based on the mode data MODE and the code data CODE, and the display output signal is created based on these data,
It is sent to the display 172. Further, the position information of the aircraft S within a fixed time, that is, the track is stored. The display 172 includes a CRT, a video RAM, a map signal ROM, etc., and based on the display output signal from the CPU 170 and the map signal from the map signal ROM, the map within the detection range of this device, the position of the aircraft, the flight number, etc. Display aircraft information for.

Next, a synchronizing signal generating circuit according to an embodiment of the present invention (corresponding to the above circuits 141, 142, 143).
Will be explained.

FIG. 1 shows the configuration of a synchronizing signal generating circuit according to an embodiment of the present invention. FIG. 2 is a time chart showing the timing of inquiry radio waves and the like.

First, the inquiry signal which is a pulse signal will be described with reference to FIG. The interrogation signal 201 is received for each rotation cycle of the rotating antenna that transmits the interrogation radio wave on which the interrogation signal is placed. Here, the inquiry signal from the SSR site in which the rotation period of the rotating antenna is 4 seconds is shown as an example. Four
For example, 14 to 16 question triggers 203 are included in one question signal 202 received every second. That is, the question trigger 203 is repeated about 14 to 16 times in a short time of about 30 to 35 ms, for example. The time interval between each question trigger is, for example, 2.2727 ms. This value is a value when a query trigger is sent at 440 Hz.

FIG. 3 shows the pulse time relationship of one interrogation trigger 204. The interrogation trigger in one interrogation signal 202 has a pulse-time relationship depending on the mode. There are four modes A, mode B, mode C, and mode D. Mode A is a mode for instructing acquisition of aircraft identification information, and mode C is a mode for instructing acquisition of aircraft altitude information. Therefore, for example, the aircraft S that has received the inquiry signal of mode A recognizes that it is in mode A, and sends its own aircraft identification information in the response signal. Also,
The aircraft S that has received the mode C inquiry signal recognizes that it is in mode C, and sends the aircraft altitude information at that point in a response signal and sends it out.

The synchronizing signal generating circuit of this embodiment receives interrogation signals from three SSR sites and generates synchronizing signals for the respective interrogating signals. The sync signal generated at number 206 in FIG. 2 is shown.

The interrogation signal from each SSR site is input at every rotation cycle of the rotating antenna, and this rotation cycle is SSR.
It is generally different for each site. Therefore, in order to eliminate the overlap of the question signals from each SSR site, a gate that opens and closes in accordance with the period of the question signal from each SSR site that is known in advance is provided.
As shown in 05, the timing at which the gate is opened (conducted) and one interrogation signal 202 is input (about 30 to 3 in FIG. 2)
The signal input is accepted only at intervals of 5 ms. The process using such a gate will be described later with reference to FIG.

Next, the basic structure and operation of the synchronizing signal generating circuit of this embodiment will be described with reference to FIG. The synchronization signal generation circuit 1 of FIG. 1 has a CPU board 2 and a universal board 3. 3 on the universal board 3
A mode discriminating and counting section 4-1, 4-2, 4-3 and an output pulse generating section 5 for respectively processing interrogation signals from one SSR site are provided. Since the three mode discriminating and counting units 4-1, 4-2 and 4-3 have the same configuration, the mode discriminating and counting unit 4-1 is used.
Only the figures are shown, and the illustration and description of the other two are omitted.

The mode discriminating and counting unit 4-1 uses the C
A gate 7 for passing only a significant section of an interrogation signal (input pulse signal) input via an ORR circuit (correlation circuit for reducing noise) 6 and a mode of an interrogation signal passed through the gate 7 are determined. Mode discriminators 8A, 8B, 8
Equipped with C and 8D. Mode discriminators 8A, 8B, 8
C and 8D determine whether the mode of the input interrogation signal is mode A, mode B, mode C, or mode D, and output 1 pulse in the mode.

Reference numeral 9 is a mode discriminating section 8A, 8B, 8C, 8D.
Input the four discrimination result signals from the
R circuits and 10 are 16-bit counters that are reset by the output of the OR circuit 9 and start counting. The clock pulse (20.72 MHz) of the clock pulse oscillator 14 is input to the counter 10 and serves as a reference clock for counting. Reference numeral 11 is a latch circuit for latching the count result of the counter 10, and 12 is a one-shot multivibrator for receiving the output of the OR circuit 9 and outputting it as a status signal STATUS1. Discrimination result signals from the mode discriminators 8A, 8B, 8C and 8D are input to the latch circuit 11 as timing signals for data latch.

The latch data of the latch circuit 11 is the CPU 1
Enter in 8. A ten key 19 and a display 20 are connected to the CPU 18. The CPU 18, the numeric keypad 19 and the display 20 are the CPU 1 of FIG.
70, ten keys 171 and display 172 are also used.

Reference numeral 13 denotes an I / O interface for data output from the CPU 18, 15-1, 15-2, 15-
Reference numeral 3 denotes three ring counters for counting down the data given from the CPU 18 via the I / O interface 13, and reference numerals 16-1, 16-2, 16-3 denote ring counters 15-1, 15-2, 15-3. Is a three-shot multivibrator which inputs the respective outputs of the above and outputs a pulse signal. Ring counter 15-1, 15
-2 and 15-3 are clock pulses (20.72) of the clock pulse oscillator 14 as reference clocks for counting.
(MHz) is input. Each output of the one-shot multivibrator 16-1, 16-2, 16-3 is a PLL.
(Phase-locked loop) circuits 17-1, 17-2,
Input to 17-3. PLL circuits 17-1, 17-2,
17-3, each mode discrimination and counting section 4
Output signals (output of the OR circuit 9) from -1, 4-2 and 4-3 are input.

Next, the operation of the synchronizing signal generating circuit 1 having the above configuration will be described.

First, immediately after the reception of the inquiry signal is started, the gate 7 is opened in all the mode discriminating and counting units 4-1, 4-2 and 4-3 so that all the received signals are inputted. .. When the first interrogation trigger of the first interrogation signal indicated by reference numeral 201 in FIG. 2 is input, this interrogation trigger is transmitted to the mode discriminators 8A, 8B, 8C and 8D via the CORR circuit 6 and the gate 7 in the open state. input. The mode discrimination units 8A, 8B, 8C and 8D discriminate whether or not the input question triggers are mode A, mode B, mode C and mode D, respectively. In the case of any mode, the mode discrimination unit outputs one pulse. These output signals are output as a signal MODE1 indicating the mode of the interrogation signal sent from the SSR site corresponding to this mode discrimination and counting section 4-1. Further, the discrimination result signals from the mode discriminators 8A, 8B, 8C and 8D are input to the OR circuit 9 so that the OR circuit 9 outputs one pulse when a question trigger of any mode is detected. It has become. The output of the OR circuit 9 is output as a status signal STATUS1 indicating the state via the one-shot multivibrator 12.

The output pulse of the OR circuit 9 indicating that the inquiry trigger of any mode is detected is the counter 10
To enter. As a result, the counter 10 is reset to "0" and starts counting. That is, the counter 10
Starts counting from the timing when a query trigger in any mode is detected.

After the first question trigger, the number 20 in FIG.
The next interrogation trigger should be input at an interval of 2.2727 ms as shown in 3,204. In this blank space, the mode discriminators 8A, 8B, 8C, 8D
Is 0, the OR circuit 9 does not output a pulse, and the counter 10 continues counting. 2.
When the next question trigger is input at an interval of 2727 ms, the same process as described above is performed, and one of the mode determination units 8
A, 8B, 8C, and 8D output "1" as the determination result.
The discrimination result signals from the mode discrimination units 8A, 8B, 8C and 8D are input to the latch circuit 11, and the latch circuit 11 latches the value of the counter 10 at this timing. After latching, the counter 10 is reset by one pulse from the OR circuit 9. After that, the above operation is repeated.

As a result, the counter 10 counts the pulse interval (2.2727 ms) of the inquiry trigger 204 of FIG. 2 with the clock pulse having the frequency of 20.72 MHz. The cycle of this clock pulse is 4.826 × 10.
Since it is E−2 μs, in principle, the counter 10 should count up from “0” to “47092” in the interval between the query triggers. This state is shown as number 207 in FIG.

On the other hand, due to various error factors, the counter 10
The final value of is not "47092" but may fluctuate slightly. Therefore, the value of the counter 10 that can be sequentially obtained by the above operation is stored in the CPU 18, and when a predetermined number of data is input, the CPU 18 calculates the average of those values. This average value is a value that accurately represents the interval between the input question triggers 204.

The average value is set in the ring counter 15-1 from the CPU 18 through the I / O interface 13. The ring counter 15-1 counts down the average value and outputs one pulse when it reaches "0". Further, even after the output of one pulse, the operation of setting the average value again and counting down is repeated. Counter 15
The one-pulse output of -1 is input to the PLL circuit 17-1 via the one-shot multivibrator 16-1.

The PLL circuit 17-1 also inputs the output of the OR circuit 9 of the mode discriminating and counting section 4-1. Then, the phase of the output pulse of the PLL circuit 17-1 is adjusted to be in phase with the output of the OR circuit 9. OR
Since the circuit 9 is output at the timing when any mode is detected as described above, as a result, the PLL circuit 17
The output pulse STRIG1 from -1 is a signal highly accurately synchronized with the frequency and phase of the input interrogation trigger.

The output from the PLL circuit 17-1 as described above is continuously performed even when the interrogation signal is not input, and as a result, the pulse signal substantially the same as the interrogation signal (number 2 in FIG. 2).
06) is obtained.

As shown by the number 205 in FIG. 2, the gate 7 becomes "1", that is, in the open state (conduction state) while about 14 to 16 question triggers 204 are input (in other words, a window function is generated). To be controlled. Further, in this embodiment, the first 12 question triggers input when the gate 7 is open are used for averaging the time intervals between the question triggers, and the remaining 4 or so are used for opening and closing the gate 7. It is used for timing.

FIG. 4 shows each mode discriminating and counting section 4.
It is an example of the timing of opening the gates of -1, 4-2 and 4-3. The timing of opening and closing the gate will be described with reference to FIG.

In this embodiment, the mode discrimination and counting section 4-1 counts and finally outputs the synchronization signal from the PLL 17-1 to the interrogation station in Haneda. The second when the synchronization signal is finally output from the PLL 17-2 after being counted by the section 4-2
Is assigned to the interrogation station in Narita, and the third sequence in which the synchronization signal is finally output from the PLL 17-3 after being counted by the mode discriminating and counting section 4-3 is previously assigned to the interrogation station in Hakone. The interrogation signal transmitted from the interrogation station in Haneda has an antenna rotation period of 4 seconds and an interrogation frequency of 440 pps.
(That is, the interval between question triggers is 2.2727 ms). The interrogation signal transmitted from the interrogation station in Narita has an antenna rotation period of 4 seconds and the interrogation count of 376 pps (that is, the interrogation interval is 2.6595 ms). The interrogation signal transmitted from the interrogation station in Hakone has an antenna rotation period of 10 seconds and an interrogation frequency of 345.2 pps (that is, an interval between interrogation triggers is 2.896ms).

Immediately after starting the reception of the inquiry signal, the CPU 18 opens the gate 7 in all the mode discriminating and counting units 4-1, 4-2 and 4-3 so that all the received signals are inputted. .. When an interrogation signal from any interrogation station is input, the mode discriminating and counting unit 4-1 assumes that the interrogation signal is from Haneda, and after 4 seconds, opens the gate 7 again. If the interrogation signal is not input at that time, it means that the interrogation signal input at the beginning was not from Haneda, and thus the gate 7 is normally opened again to wait for the next interrogation signal. Each mode discriminating and counting unit 4-1 and 4-
By performing such an operation in Nos. 2 and 4-3, it is possible to catch the interrogation signal from the corresponding interrogation station. The interrogation stations of Haneda and Narita have the same antenna rotation cycle of 4 seconds, so it cannot be distinguished only by the above method. Therefore, the question trigger interval (count value) is determined and distinguished.

FIG. 4 shows how the corresponding interrogation signal is captured in this way. As the interrogation signal 201 received, interrogation signals from the three interrogation stations are input independently in a timely manner. Each inquiry station is identified and captured by the above-described method, and thereafter, the inquiry signal is input by opening the gate at predetermined intervals as illustrated.

As described above, the antenna rotation period and the number of interrogations of each interrogation station are made slightly different, and the gate 9 is used to input only a necessary portion of the input interrogation signal. Therefore, for example, in an interrogation station with an antenna rotation period of 4 seconds and an interrogation station with 10 seconds, the number of times of interrogation signals is 3 / 100,000 times, which is approximately once every 92 hours.
In the above embodiment, the gate 9 has an antenna rotation cycle 30.
The gate is controlled so as to be in an open state for about 35 ms, but during this 30 to 35 ms, a signal representing each mode as shown in FIG. 3 has a predetermined cycle (for example, 2. It is repeatedly transmitted at 2727 ms intervals).
Therefore, the gate may be opened every 25 .mu.s (the longest interrogation trigger in Mode D) plus a slight margin for each predetermined period. In this way, the possibility of signal overlap can be greatly reduced.

FIG. 5A is a flow chart of the main routine showing the general operation of the CPU 18 of this embodiment.
Further, FIG. 5B is a flowchart of the interrupt process.

When the operation is first started in the synchronizing signal generating circuit 1 of this embodiment, the CPU 18 repeats the monitoring of the inquiry signal (step S1). If the first interrogation trigger of the interrogation signal is detected, it is determined from which station the interrogation signal is coming from, and then the interruption process of FIG. 5B is performed. Three interrupt processes are prepared according to the series corresponding to the three question stations. Here, only the interrupt processing corresponding to the first series will be described. The latter two interrupt processes also perform the same process. In addition,
When it is not known which station the received inquiry signal is immediately after the start of operation, a plurality of interrupt processes corresponding to the possible sequences are all sequentially activated.

In the interrupt process of FIG. 5B, first, the input question trigger data is read (step S1).
1). Then, the mode determination unit 8A, 8B, 8C, 8D determines the mode (step S12). next,
It is determined whether the read data is the 12th data (step S13). If it is not the 12th data,
It returns from the interrupt processing and waits for the next data to be read. When the interrupt process is started again, the data is read, and the read data becomes the 12th data, the average of the 12 data is calculated and the counter 15-1
(Step S14). Then, the data is collated with the interrogation station data stored in advance, and it is confirmed that the interrogation signal is from the interrogation station assigned (step S15). Further, the gate generation synchronization data that defines the gate opening / closing timing is generated and output (step S16), and the process returns.

According to the above embodiment, it is possible to easily generate and output a pulse signal which is synchronized with the interrogation signal from the SSR site with high accuracy. In particular, the clock signal that serves as a reference for counting is self-excited oscillation using a crystal, and its frequency and the like fluctuate depending on temperature and humidity. However, the synchronizing signal generating circuit of the above embodiment is only used for measuring and reproducing the interval between the query triggers repeated in a short time (for example, about 30 to 35 ms in FIG. 2). It is stable against environmental changes (temperature, humidity, voltage fluctuations, etc.) in a short time, that is, short-term stability is guaranteed, so that high accuracy is always obtained. It also does not require expensive equipment.

In the above embodiment, the questioning station SS
Although the case where the R site has three stations has been described, the present invention is not limited to this and can be applied to any number of stations. In addition, SSRs all over the country
The data of the site may be stored in advance, and when the position of the own station is input, the data of the nearby SSR site may be automatically extracted and set.

Further, the above-mentioned embodiment is a passive SS.
Although the example applied to the R device has been described, the present invention is not limited to this, and the present invention can be widely applied when it is necessary to continuously generate a pulse signal synchronized with a target input pulse signal with high accuracy. You can

Further, in the above embodiment, the pulse interval of the inquiry trigger is counted and the average value thereof is calculated, and the average value is down-counted by the clock pulse to output the pulse. However, instead of obtaining the average, the inquiry is performed. The shift amount of the count value obtained by counting the trigger pulse interval may be directly reflected in the down count value for the next pulse output.

[0052]

As described above, according to the present invention, it is possible to continuously generate and output a pulse signal which is synchronized with a pulse signal input at a predetermined interval for a short time with high precision.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a synchronization signal generation circuit according to an embodiment of the present invention.

[Figure 2] Time chart showing the timing of interrogation radio waves

FIG. 3 is a waveform diagram showing the pulse time relationship of one question trigger.

FIG. 4 is a diagram showing timings for discriminating each mode and opening a gate of a counting unit.

FIG. 5 is a flowchart showing a schematic operation of the CPU of this embodiment.

FIG. 6 is a configuration diagram of a passive SSR device to which one of the synchronization signal generation circuits of the present invention is applied.

FIG. 7 is an explanatory diagram for explaining the operating principle of this passive SSR device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Synchronous signal generating circuit, 2 ... CPU board, 3 ... Universal board, 4-1, 4-2, 4-3 ... Mode discrimination and counting section, 5 ... Output pulse generating section, 7 ... Gate, 8
A, 8B, 8C, 8D ... Mode discrimination unit, 9 ... OR circuit,
10 ... Counter, 11 ... Latch circuit, 12 ... One-shot multivibrator, 14 ... Clock pulse oscillator,
13 ... I / O interface, 15-1, 15-2,
15-3 ... Ring counter, 16-1, 16-2, 16
-3 ... One-shot multivibrator, 17-1, 1
7-2, 17-3 ... PLL (phase locked loop)
Circuit, 18 ... CPU, 19 ... Numeric keypad, 20 ... Display.

Claims (2)

[Claims] 1. A synchronizing signal generating circuit for inputting a pulse signal which is periodically repeated for a short time and continuously generating a synchronizing pulse signal which is synchronized with the pulse signal, and which generates a clock pulse of a predetermined period. A clock generating means for inputting the input pulse signal, and counting the pulse interval of the input pulse signal a plurality of times using the clock pulse
Counting means, and an average of counting results of a plurality of times of the first counting means,
Alternatively, a calculating means for calculating a value such as weighting of the variation, a second counting means for counting the average value using the clock pulse, and continuously outputting a pulse at a time interval corresponding to the average value, 2. A synchronizing signal generating circuit, comprising: a phase adjusting means for outputting the pulse output from the second counting means by matching the phase of the pulse output with the phase of the input pulse. 2. A gate circuit that opens and closes at an interval according to the pulse interval of the input pulse signal so that only the significant pulse portion of the input pulse signal is input to the first counting means. 1. The synchronization signal generation circuit described in 1.