JPH05121684A - Cmos semiconductor device provided with protective diode - Google Patents
Cmos semiconductor device provided with protective diodeInfo
- Publication number
- JPH05121684A JPH05121684A JP3305691A JP30569191A JPH05121684A JP H05121684 A JPH05121684 A JP H05121684A JP 3305691 A JP3305691 A JP 3305691A JP 30569191 A JP30569191 A JP 30569191A JP H05121684 A JPH05121684 A JP H05121684A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- concentration
- type diffusion
- semiconductor device
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 230000001681 protective effect Effects 0.000 title abstract description 6
- 238000009792 diffusion process Methods 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 238000010586 diagram Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、ＣＭＯＳ半導体装置
に関し、特に入力及び出力回路の静電破壊に対する保護
ダイオードを備えたＬＤＤ構造のＣＭＯＳ半導体装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS semiconductor device, and more particularly to an LDD structure CMOS semiconductor device having a protection diode against electrostatic breakdown of input and output circuits.
【０００２】[0002]
【従来の技術】従来、ＣＭＯＳ半導体装置の入力回路に
は、内部の素子を保護するために抵抗やＰＮ接合ダイオ
ードからなる保護回路が設けられている。かかる保護回
路の構成例として、例えば「ＣＭＯＳＶＬＳＩ設計の原
理」（富沢孝，松山泰男監訳，丸善発行，第196 頁）
に、図６に示すような標準的な入力保護回路が開示され
ている。図において、101 は入力パッド、102はＰチャ
ネルＭＯＳＦＥＴ、103 はＮチャネルＭＯＳＦＥＴ、Ｒ
は保護抵抗、Ｄ1 ，Ｄ2 は保護ダイオード、Ｃは入力容
量である。2. Description of the Related Art Conventionally, an input circuit of a CMOS semiconductor device is provided with a protection circuit composed of a resistor and a PN junction diode for protecting internal elements. As a configuration example of such a protection circuit, for example, "Principle of CMOS VLSI design" (translated by Takashi Tomizawa, Yasuo Matsuyama, published by Maruzen, p. 196)
Discloses a standard input protection circuit as shown in FIG. In the figure, 101 is an input pad, 102 is a P-channel MOSFET, 103 is an N-channel MOSFET, R
Is a protection resistor, D 1 and D 2 are protection diodes, and C is an input capacitance.
【０００３】一方、近年ＣＭＯＳデバイスの微細化に伴
い、ＭＯＳＦＥＴのチャネル長が短くなり短チャネル効
果とホットキャリア効果が問題になってきており、これ
らの問題に対応するため、各種のＬＤＤ構造のＣＭＯＳ
デバイスが提案されている。例えば、本件出願人は特開
平３−１８４３７２号において、ＮチャネルＭＯＳＦＥ
Ｔの低濃度ソース・ドレイン領域の形成後、Ｐチャネル
ＭＯＳＦＥＴの低濃度ソース・ドレイン領域の形成前
に、熱処理を加えることにより、ＮチャネルＭＯＳＦＥ
Ｔの低濃度ソース・ドレイン領域とゲート電極のオーバ
ーラップを増やして、ドレイン・ウェル間の空乏層がゲ
ートの側壁まで到達しないようにし、ゲートの側壁での
ホットエレクトロンの注入を防止するようにしたＣＭＯ
Ｓ半導体装置の製造方法を提案している。On the other hand, in recent years, with the miniaturization of CMOS devices, the channel length of MOSFET has become shorter, and the short channel effect and hot carrier effect have become problems. To cope with these problems, various LDD structure CMOSs are used.
A device has been proposed. For example, the applicant of the present application has disclosed in Japanese Patent Laid-Open No. 3-184372 that N-channel MOSFE
After forming the low-concentration source / drain regions of T and before forming the low-concentration source / drain regions of the P-channel MOSFET, heat treatment is performed to obtain N-channel MOSFE.
The overlap between the low concentration source / drain region of T and the gate electrode is increased so that the depletion layer between the drain and well does not reach the side wall of the gate, and hot electron injection on the side wall of the gate is prevented. CMO
An S semiconductor device manufacturing method is proposed.
【０００４】[0004]
【発明が解決しようとする課題】ところで、ＣＭＯＳ半
導体装置の入力及び出力回路の静電破壊に対する保護ダ
イオードのＰＮ接合部の構造は、一般的にＭＯＳＦＥＴ
のソース・ドレイン領域のＰＮ接合の構造と同じに形成
されている。そのため、前記従来提案のＣＭＯＳ半導体
装置の製造方法を用いて保護ダイオードを形成する場
合、図７に示すように、Ｎ型保護ダイオードのＰＮ接合
部は、Ｐウェル102 と低濃度ｎ型拡散層103の接合面で
構成される。なお図７において、101 はＰ型基板、104
は高濃度ｎ型拡散層、105 はフィールド酸化膜、106 は
ゲート電極である。By the way, the structure of the PN junction of the protection diode against electrostatic breakdown of the input and output circuits of the CMOS semiconductor device is generally MOSFET.
Is formed to have the same structure as the PN junction of the source / drain regions. Therefore, when the protection diode is formed by using the method of manufacturing the CMOS semiconductor device proposed in the related art, as shown in FIG. 7, the PN junction portion of the N-type protection diode includes the P well 102 and the low concentration n-type diffusion layer 103. It is composed of joint surfaces. In FIG. 7, 101 is a P-type substrate and 104
Is a high-concentration n-type diffusion layer, 105 is a field oxide film, and 106 is a gate electrode.
【０００５】この結果、Ｎ型保護ダイオードのＰＮ接合
のブレークダウン電圧は、通常のＰウェルと高濃度ｎ型
拡散領域の接合部におけるブレークダウン電圧よりも上
昇してしまい、静電破壊に対する保護機能が低下してし
まう。As a result, the breakdown voltage of the PN junction of the N-type protection diode becomes higher than the breakdown voltage at the junction between the normal P-well and the high-concentration n-type diffusion region, and the protection function against electrostatic breakdown is provided. Will decrease.
【０００６】本発明は、ホットキャリア効果に対する信
頼性の高いＬＤＤ構造のＣＭＯＳ半導体装置に保護ダイ
オードを設けた場合における上記問題点を解消させるた
めなされたもので、製造工程を複雑化させることなく静
電耐圧を向上させた保護ダイオードを備えたＣＭＯＳ半
導体装置を提供することを目的とする。The present invention has been made in order to solve the above problems when a protection diode is provided in a CMOS semiconductor device having an LDD structure which is highly reliable against the hot carrier effect. An object of the present invention is to provide a CMOS semiconductor device including a protection diode having an improved breakdown voltage.
【０００７】[0007]
【課題を解決するための手段及び作用】上記問題点を解
決するため、本発明は、図１の概念図に示すように、半
導体基板１に形成された入力及び出力保護ダイオードを
備えたＬＤＤ構造のＣＭＯＳ半導体装置において、Ｐウ
ェル２内に形成されているＮチャネルＭＯＳＦＥＴのソ
ース・ドレイン領域は高濃度ｎ型拡散層４が低濃度ｎ型
拡散層３に完全に覆われている構造を有しており、前記
入力及び出力保護ダイオードの中のＰウェル２内に形成
されているＮ型保護ダイオードの活性領域には、前記Ｎ
チャネルＭＯＳＦＥＴのソース・ドレイン領域を構成し
ている低濃度ｎ型拡散層３を設けずに、Ｎ型保護ダイオ
ードのＰＮ接合面をＰウェル２と高濃度ｎ型拡散層４の
接合部で構成するものである。In order to solve the above problems, the present invention provides an LDD structure having input and output protection diodes formed on a semiconductor substrate 1, as shown in the conceptual diagram of FIG. In the CMOS semiconductor device, the source / drain region of the N-channel MOSFET formed in the P well 2 has a structure in which the high concentration n-type diffusion layer 4 is completely covered with the low concentration n-type diffusion layer 3. In the active region of the N-type protection diode formed in the P well 2 of the input and output protection diodes,
Without providing the low-concentration n-type diffusion layer 3 forming the source / drain region of the channel MOSFET, the PN junction surface of the N-type protection diode is formed by the junction of the P well 2 and the high-concentration n-type diffusion layer 4. It is a thing.
【０００８】このように構成したＣＭＯＳ半導体装置に
おいては、Ｐウェル２内に構成するＮ型保護ダイオード
がＰウェル２と高濃度ｎ型拡散領域４の接合面で形成し
ているので、低濃度ｎ型拡散領域を形成する場合より
も、ＰＮ接合のブレークダウン電圧は低く設定され、Ｃ
ＭＯＳＦＥＴの静電耐圧を向上させることができる。ま
た製造工程時には、保護ダイオード部を低濃度ｎ型拡散
領域形成時にレジストパターンでマスクすればよいの
で、使用マスクを変更するだけでよく、製造工程を増加
させることなく容易に形成することができる。In the CMOS semiconductor device having the above structure, since the N-type protection diode formed in the P-well 2 is formed at the junction surface between the P-well 2 and the high-concentration n-type diffusion region 4, the low-concentration n-type diode is formed. The breakdown voltage of the PN junction is set lower than that in the case of forming the type diffusion region, and C
The electrostatic breakdown voltage of the MOSFET can be improved. Further, during the manufacturing process, the protective diode portion may be masked with the resist pattern when the low-concentration n-type diffusion region is formed. Therefore, it is only necessary to change the mask used, and it is possible to easily form the protective diode portion without increasing the manufacturing process.
【０００９】[0009]
【実施例】次に実施例について説明する。図２は、本発
明に係る保護ダイオードを備えたＣＭＯＳ半導体装置の
第１実施例を示す断面構成図である。図２において、11
はＰ型基板、12はＮウェル、13はＰウェル、14は低濃度
ｎ型拡散層、15は低濃度ｐ型拡散層、16は高濃度ｎ型拡
散層、17は高濃度ｐ型拡散層、18はフィールド酸化膜、
19はゲート電極、20は絶縁膜、21はメタル層である。ま
たこの構成のＣＭＯＳ半導体装置の等価回路を図３に示
す。図３において、31はＮ型保護ダイオード、32はＰ型
保護ダイオード、33はＰチャネルＭＯＳＦＥＴ、34はＮ
チャネルＭＯＳＦＥＴ、35は入力端子である。EXAMPLES Next, examples will be described. FIG. 2 is a cross-sectional configuration diagram showing a first embodiment of a CMOS semiconductor device having a protection diode according to the present invention. In FIG. 2, 11
Is a P type substrate, 12 is an N well, 13 is a P well, 14 is a low concentration n type diffusion layer, 15 is a low concentration p type diffusion layer, 16 is a high concentration n type diffusion layer, and 17 is a high concentration p type diffusion layer. , 18 is a field oxide film,
Reference numeral 19 is a gate electrode, 20 is an insulating film, and 21 is a metal layer. An equivalent circuit of the CMOS semiconductor device having this structure is shown in FIG. In FIG. 3, 31 is an N-type protection diode, 32 is a P-type protection diode, 33 is a P-channel MOSFET, and 34 is N-type.
The channel MOSFET, 35 is an input terminal.
【００１０】通常、ＭＯＳＦＥＴのゲート酸化膜の静電
耐圧は数十Ｖ程度しかないため、図３の等価回路に示す
ように、入力端子35と接地ＶSS間にＮ型保護ダイオード
31を、入力端子35と電源ＶDD間にＰ型保護ダイオード32
を接続し、印加静電電圧による電荷を吸収する役目を行
わせている。これらの保護ダイオードのブレークダウン
電圧を低下させ、ゲート酸化膜の保護機能を向上させる
ためには、ウェルと接合している拡散層の濃度を上げれ
ばよい。前記従来提案の製造方法を、そのまま適用した
場合、Ｎ型保護ダイオードの活性領域がＮチャネルＭＯ
ＳＦＥＴのソース・ドレイン領域と同じ構造になるの
で、活性領域内の高濃度ｎ型拡散層は低濃度ｎ型拡散層
に完全に覆われてしまうことになる。その結果、Ｎ型保
護ダイオードはＰウェルと低濃度ｎ型拡散層によるＰＮ
接合となり、ブレークダウン電圧が高濃度ｎ型拡散層に
よる接合よりも高くなり、保護機能が低下してしまう。Normally, the electrostatic breakdown voltage of the gate oxide film of the MOSFET is only about several tens of volts, so as shown in the equivalent circuit of FIG. 3, an N-type protection diode is provided between the input terminal 35 and the ground V SS.
31 is a P-type protection diode 32 between the input terminal 35 and the power supply VDD.
Are connected to perform the role of absorbing the electric charge due to the applied electrostatic voltage. In order to reduce the breakdown voltage of these protection diodes and improve the protection function of the gate oxide film, the concentration of the diffusion layer that is in contact with the well may be increased. If the manufacturing method proposed in the related art is applied as it is, the active region of the N-type protection diode is N-channel MO.
Since it has the same structure as the source / drain region of the SFET, the high concentration n-type diffusion layer in the active region is completely covered with the low concentration n-type diffusion layer. As a result, the N-type protection diode has a PN due to the P-well and the low-concentration n-type diffusion layer.
As a result, the breakdown voltage becomes higher than that of the junction formed by the high-concentration n-type diffusion layer, and the protection function deteriorates.
【００１１】しかし本発明においては、上記実施例で示
すように、Ｎ型保護ダイオード31のＰＮ接合面が、低濃
度ｎ型拡散層４を設けずに、Ｐウェル13と高濃度ｎ型拡
散層16とで形成されるようにしているので、従来の提案
のＣＭＯＳ半導体装置の製造方法をそのまま用いて保護
ダイオードを形成した場合よりも、ブレークダウン電圧
を低下させることができる。そしてこのように低濃度ｎ
型拡散層を設けずに、高濃度ｎ型拡散層16を設ける場合
には、このＣＭＯＳ半導体装置の低濃度ｎ型拡散層形成
時に使用するレジストパターンと高濃度ｎ型拡散層形成
時に使用するレジストパターンを変えて、Ｎ型保護ダイ
オードの領域には低濃度ｎ型拡散層４が形成されず、高
濃度ｎ型拡散層16のみ形成されるようにすればよい。However, in the present invention, as shown in the above embodiment, the PN junction surface of the N-type protection diode 31 does not have the low-concentration n-type diffusion layer 4 and the P well 13 and the high-concentration n-type diffusion layer are not provided. Therefore, the breakdown voltage can be lowered as compared with the case where the protection diode is formed by using the conventional method of manufacturing the CMOS semiconductor device proposed as it is. And in this way low concentration n
When the high-concentration n-type diffusion layer 16 is provided without providing the type diffusion layer, the resist pattern used when forming the low-concentration n-type diffusion layer and the resist used when forming the high-concentration n-type diffusion layer of this CMOS semiconductor device The pattern may be changed so that the low concentration n-type diffusion layer 4 is not formed in the region of the N-type protection diode and only the high concentration n-type diffusion layer 16 is formed.
【００１２】次に図４に基づいて本発明の第２実施例を
説明する。図４は保護ダイオードを備えたＣＭＯＳ半導
体装置の出力回路を示す断面構成図で、図２に示した第
１実施例と同一又は対応する部分には同一符号を付して
示している。この実施例は、Ｎ型保護ダイオードを構成
する高濃度ｎ型拡散層16を拡散抵抗として用い、これを
保護抵抗としての機能をもたせるようにしたもので、そ
の等価回路を図５に示す。この実施例では、Ｎ型保護ダ
イオード31を構成する高濃度ｎ型拡散層16を拡散抵抗36
として用いるようにしたものを示したが、Ｐ型保護ダイ
オード32を構成する高濃度ｐ型拡散層17を拡散抵抗とし
て使用するようにしても何ら差し支えない。なお図５に
おいて、37は出力端子である。Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a cross-sectional configuration diagram showing an output circuit of a CMOS semiconductor device having a protection diode, and the same or corresponding parts as those of the first embodiment shown in FIG. 2 are designated by the same reference numerals. In this embodiment, the high-concentration n-type diffusion layer 16 constituting the N-type protection diode is used as a diffusion resistance, and this diffusion resistance 16 functions as a protection resistance. An equivalent circuit thereof is shown in FIG. In this embodiment, the high-concentration n-type diffusion layer 16 which constitutes the N-type protection diode 31 is replaced by the diffusion resistor 36.
However, the high-concentration p-type diffusion layer 17 forming the P-type protection diode 32 may be used as a diffusion resistor without any problem. In FIG. 5, 37 is an output terminal.
【００１３】[0013]
【発明の効果】以上実施例に基づいて説明したように、
本発明によれば、ホットキャリア効果に対する信頼性の
高いＬＤＤ構造のＣＭＯＳ半導体装置において、Ｐウェ
ル内のＮ型保護ダイオードのＰＮ接合を、低濃度ｎ型拡
散層を設けずにＰウェルと高濃度ｎ型拡散層の接合部で
構成したので、製造工程を複雑化させることなく、静電
耐圧を向上させた保護ダイオードを備えたＣＭＯＳ半導
体装置を実現することができる。As described above on the basis of the embodiments,
According to the present invention, in a CMOS semiconductor device having an LDD structure with high reliability against the hot carrier effect, the PN junction of the N-type protection diode in the P-well and the P-well with a high concentration is provided without providing the low-concentration n-type diffusion layer. Since it is composed of the junction of the n-type diffusion layers, it is possible to realize a CMOS semiconductor device including a protection diode with improved electrostatic breakdown voltage without complicating the manufacturing process.
【図１】本発明に係る保護ダイオードを備えたＣＭＯＳ
半導体装置を説明するための概念図である。1 a CMOS with a protection diode according to the invention, FIG.
It is a conceptual diagram for explaining a semiconductor device.
【図２】本発明の第１実施例を示す断面構成図である。FIG. 2 is a sectional configuration diagram showing a first embodiment of the present invention.
【図３】第１実施例の等価回路図である。FIG. 3 is an equivalent circuit diagram of the first embodiment.
【図４】本発明の第２実施例を示す断面構成図である。FIG. 4 is a sectional configuration diagram showing a second embodiment of the present invention.
【図５】第２実施例の等価回路図である。FIG. 5 is an equivalent circuit diagram of the second embodiment.
【図６】一般的なＣＭＯＳ半導体装置の入力保護回路を
示す回路構成図である。FIG. 6 is a circuit configuration diagram showing an input protection circuit of a general CMOS semiconductor device.
【図７】従来提案のＬＤＤ構造のＣＭＯＳ半導体装置の
製造方法を用いて形成した保護ダイオードを備えたＣＭ
ＯＳ半導体装置の断面構成図である。FIG. 7 is a CM including a protection diode formed by using a method of manufacturing a CMOS semiconductor device having an LDD structure proposed in the related art.
It is a cross-sectional block diagram of an OS semiconductor device.
１ Ｐ型基板 ２ Ｐウェル ３ 低濃度ｎ型拡散層 ４ 高濃度ｎ型拡散層 ５ フィールド酸化膜 ６ ゲート電極 1 P-type substrate 2 P-well 3 Low concentration n-type diffusion layer 4 High concentration n-type diffusion layer 5 Field oxide film 6 Gate electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/784 7342−4Ｍ Ｈ０１Ｌ 27/08 ３２１ Ｈ 8225−4Ｍ 29/78 ３０１ Ｐ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical indication location H01L 29/784 7342-4M H01L 27/08 321 H 8225-4M 29/78 301 P
Claims (2)
護ダイオードを備えたＬＤＤ構造のＣＭＯＳ半導体装置
において、Ｐウェル内に形成されているＮチャネルＭＯ
ＳＦＥＴのソース・ドレイン領域は高濃度ｎ型拡散層が
低濃度ｎ型拡散層に完全に覆われている構造を有してお
り、前記入力及び出力保護ダイオードの中のＰウェル内
に形成されているＮ型保護ダイオードの活性領域には、
前記ＮチャネルＭＯＳＦＥＴのソース・ドレイン領域を
構成している低濃度ｎ型拡散層を設けずに、Ｎ型保護ダ
イオードのＰＮ接合面がＰウェルと高濃度ｎ型拡散層の
接合部で構成されていることを特徴とする保護ダイオー
ドを備えたＣＭＯＳ半導体装置。1. A CMOS semiconductor device having an LDD structure including an input protection diode and an output protection diode formed on a semiconductor substrate, wherein an N channel MO formed in a P well is formed.
The source / drain region of the SFET has a structure in which the high-concentration n-type diffusion layer is completely covered by the low-concentration n-type diffusion layer, and is formed in the P-well in the input and output protection diodes. In the active region of the N-type protection diode,
The low concentration n-type diffusion layer forming the source / drain region of the N-channel MOSFET is not provided, and the PN junction surface of the N-type protection diode is formed by the junction of the P well and the high concentration n-type diffusion layer. A CMOS semiconductor device having a protection diode characterized by being provided.
度ｎ型拡散層を拡散抵抗として用いることを特徴とする
請求項１記載の保護ダイオードを備えたＣＭＯＳ半導体
装置。2. A CMOS semiconductor device having a protection diode according to claim 1, wherein a high-concentration n-type diffusion layer forming the N-type protection diode is used as a diffusion resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3305691A JPH05121684A (en) | 1991-10-25 | 1991-10-25 | Cmos semiconductor device provided with protective diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3305691A JPH05121684A (en) | 1991-10-25 | 1991-10-25 | Cmos semiconductor device provided with protective diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05121684A true JPH05121684A (en) | 1993-05-18 |
Family
ID=17948203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3305691A Pending JPH05121684A (en) | 1991-10-25 | 1991-10-25 | Cmos semiconductor device provided with protective diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05121684A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996021247A1 (en) * | 1994-12-29 | 1996-07-11 | Philip Shiota | Method for fabricating devices for electrostatic discharge protection and voltage references, and the resulting structures |
| EP0834928A1 (en) * | 1996-10-04 | 1998-04-08 | Xerox Corporation | Integrated circuit diode with a charge injecting node |
| EP0845829A2 (en) * | 1996-11-12 | 1998-06-03 | Xerox Corporation | RF switching cells |
| JP2006286800A (en) * | 2005-03-31 | 2006-10-19 | Ricoh Co Ltd | Semiconductor device |
| JP2007139664A (en) * | 2005-11-21 | 2007-06-07 | Nec Electronics Corp | Battery voltage monitoring device |
-
1991
- 1991-10-25 JP JP3305691A patent/JPH05121684A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996021247A1 (en) * | 1994-12-29 | 1996-07-11 | Philip Shiota | Method for fabricating devices for electrostatic discharge protection and voltage references, and the resulting structures |
| EP0834928A1 (en) * | 1996-10-04 | 1998-04-08 | Xerox Corporation | Integrated circuit diode with a charge injecting node |
| EP0845829A2 (en) * | 1996-11-12 | 1998-06-03 | Xerox Corporation | RF switching cells |
| EP0845829A3 (en) * | 1996-11-12 | 1999-05-06 | Xerox Corporation | RF switching cells |
| JP2006286800A (en) * | 2005-03-31 | 2006-10-19 | Ricoh Co Ltd | Semiconductor device |
| JP2007139664A (en) * | 2005-11-21 | 2007-06-07 | Nec Electronics Corp | Battery voltage monitoring device |
| JP4620571B2 (en) * | 2005-11-21 | 2011-01-26 | ルネサスエレクトロニクス株式会社 | Battery voltage monitoring device |
| JP2011043505A (en) * | 2005-11-21 | 2011-03-03 | Renesas Electronics Corp | Battery voltage measuring device |
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