JPH0512062A - Step break processing system - Google Patents

Abstract

PURPOSE:To easily designate the number of steps even to a main routine calling a sub-routine on the step break processing system in an information processing system equipped with a step break function and an instruction break function. CONSTITUTION:The system is provided with an instruction analysis means 103 analyzing an execution instruction during an information processing system 100 uses a step break function 101, a counting stop means 104 stopping the counting of the execution instruction in the step break function when the execution of the sub-routine call instruction is detected, a starting means 105 designating the next instruction of the sub-routine call instruction to the instruction break function 102 to start the usage, and a counting restarting means 106 permitting the step break function to restart the counting of the number of execution instructions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a step break processing method in an information processing system having a step break function and an instruction break function.

An information processing system may be provided with a step break function and an instruction break function as effective functions for debugging a program. The step break function stops the processing each time the information processing system executes one instruction of the debug target program,
Alternatively, the processing is stopped after executing a predetermined number of instructions, and the instruction break function is to stop the processing after the information processing system executes a predetermined instruction.

While the information processing system is executing a certain program, after executing a program (hereinafter referred to as a subroutine) shared by the programs, the original program (hereinafter referred to as a main routine) is continuously executed again. There are not a few cases.

[0004]

2. Description of the Related Art FIG. 4 is a diagram showing an example of a conventional information processing system, FIG. 5 is a diagram showing an example of a debug target program, and FIG. 6 is a diagram showing an example of a step break process in FIG. is there.

The information processing system shown in FIG. 4 comprises a processor 1 for executing a program, a step break unit 2 for realizing a step break function, and an instruction break unit 3 for realizing an instruction break function. .

When the debug executor inputs a designated step number N and a start signal ST ₂ to the step break section 2 when debugging a program using the step break function, the step break section 2 registers the designated step number register. After accumulating the designated step number N input in 21, the execution start signal st ₂ is transmitted to the processing device 1.

The processing device 1 which has received the execution start signal st ₂
Sequentially accumulates the instruction address a indicating the storage area of the instruction to be executed in the instruction address register 11,
Each instruction constituting the program to be debugged specified by is sequentially executed by the instruction execution unit 12. The instruction execution signal e is transmitted to the step break unit 2 every time the instruction execution unit 12 executes one instruction.

The step break unit 2 includes an instruction execution unit 12
Each time the instruction execution signal e is transmitted from the designated step number register 21, the designated step number N accumulated in the designated step number register 21 is decremented by "1" step, and when the designated step number N becomes zero, the processing device 1 is processed. The execution stop signal sp ₂ is transmitted to the terminal.

The processing device 1 which has received the execution stop signal sp _2.
Stops the execution of the program to be debugged. When the debug executor inputs the designated instruction address A and the start signal ST ₃ to the instruction break unit 3 when debugging the program using the instruction break function, the instruction break unit 3 stores the designated instruction address register 31 in the designated instruction address register 31. After accumulating the input designated instruction address A, the execution start signal st ₃ is transmitted to the processor 1.

The processing device 1 which has received the execution start signal st _3.
In the same manner as described above, the instruction address a indicating the storage area of the instruction to be executed is sequentially accumulated in the instruction address register 11,
Each instruction constituting the debug target program specified by the instruction address a is sequentially executed by the instruction executing section 12, and the instruction address a accumulated in the instruction address register 11 is also transmitted to the instruction break section 3.

The instruction break unit 3 receives the instruction address a transmitted from the instruction address register 11 and the designated instruction address A stored in the designated instruction address register 31.
When the instruction address a matches the designated instruction address A, the execution stop signal sp _{3 is} sent to the processing device 1.
To convey.

The processor 1 which has received the execution stop signal sp _3.
Stops the execution of the program to be debugged. As described above, the state of the information processing system after the instruction of the debug target program is executed by the designated step number N and the state of the information processing system after the instruction designated by the designated instruction address A can be confirmed.

Here, it is assumed that the main routine MR as shown in FIG. 5, for example, is debugged by using the step break function. In FIG. 5, the main routine MR
Each instruction address a of is indicated by steps S1 _M , S2 _M , ..., But the instruction specified by step S3 _M suspends the execution of the main routine MR, executes the subroutine SR, and then executes the main routine MR. the execution resumed, indicating that the subroutine call instruction SCI for executing instructions after designated sequentially by the following steps S4 _M in step S3 _M.

4 to 6, the debug executor desires to stop the information processing system after executing the main routine MR up to step S10 _M , and specifies the designated number of steps N = “10” and the start signal ST _2. When is input to the step break unit 2, the step break unit 2 accumulates the designated step number N = “10” in the designated step number register 21 and then outputs the execution start signal st ₂ to the processing device 1 in the same manner as described above. convey, also receives the execution start signal st ₂ processing apparatus 1, in the same manner as described above, step S1 as an instruction address a to the instruction address di Resta 11 _M, S
By sequentially accumulating 2 _M and S3 _M , each instruction of the main routine MR is executed by the instruction execution unit 12, and the instruction execution signal e is transmitted to the step break unit 2, and the step break unit 2 further executes the instruction execution. Each time the signal e is received, the designated step number N (= “10”) is set to “9”, “8”, “7”.
And update.

After executing the subroutine call instruction SCI designated by step S3 _M of the main routine MR, the processor 1 sequentially accumulates steps S1 _{S to} S4 _S as the instruction address a in the instruction address register 11. Each instruction of the subroutine SR is executed by the instruction execution unit 12
And executes the instruction execution signal e to the step break unit 2.

As a result, the step break unit 2 has the designated step number N (= “7”) in the designated step number register 21 by the time the processing apparatus 1 finishes executing the subroutine SR.
Is updated to "3".

The processor 1 executes the instruction designated by step S4 _S of the subroutine SR,
At step S4 _M of the main routine MR designated by the subroutine call instruction SCI, the instruction address a
Is stored in the instruction address register 11, the instruction execution unit 12 executes the instruction next to the subroutine call instruction SCI of the main routine MR, the instruction execution signal e is transmitted to the step break unit 2, and the instruction execution signal e is also transmitted. The received step break unit 2 updates the designated step number N = “3” in the designated step number register 21 to “2”.

Thereafter, the processor 1 sequentially accumulates the steps S5 _M and S6 _M as the instruction address a in the instruction address register 11 and executes the respective instructions of the main routine MR by the instruction execution section 12 and the step break. Part 2
The instruction execution signal e to the step break unit 2
Is the designated number of steps N = each time the instruction execution signal e is received.
When "2" is updated to "1" and "0" and the designated step number N becomes "0", the execution stop signal sp ₂ is transmitted to the processing device 1 and stopped.

As a result, the processing apparatus 1 stops after executing the main routine MR up to step S6 _M , which is contrary to the wish of the debug executor who wished to execute the main routine MR up to step S10 _M. Becomes

[0020]

As is clear from the above description, in the conventional information processing system, the step break unit 2 counts all the instructions executed by the processing device 1 and determines the designated step number N. Since the subtraction is performed, it becomes difficult to stop at the desired step S10 _M when the main routine MR as illustrated in FIG. 5 is to be debugged.
There is a problem that it is difficult to meet the expectations of the debug executor, such as stopping the subroutine SR other than the above during execution.

[0021] In order to solve such a problem, by sequentially selectively using a step break portion 2 and the instruction break unit 3, temporarily stopped by executing the processing device 1 until the main routine MR subroutine call instruction SCI (step S3 _M) Then, the processing device 1 may be executed until the final step S4 _S of the subroutine SR and temporarily stopped, and then the steps S4 _{M and} after of the main routine MR may be executed. Since it is necessary to use the break portions 3 frequently, it takes a long time for debugging work, and there is a possibility that an artificial error is caused in many cases, which is not necessarily a sufficient solution.

An object of the present invention is to make it possible to easily specify the specified number of steps in the step break function even for a main routine that calls and executes a subroutine.

[0023]

FIG. 1 is a diagram showing the principle of the present invention. In FIG. 1, reference numeral 100 denotes an information processing system which is a target of the present invention, and 101 and 102 denote a step break function and an instruction break function included in the information processing system 100.

Reference numeral 103 is an instruction analyzing means provided in the information processing system 100 according to the present invention. 104 is a counting stop means provided in the information processing system 100 according to the present invention.

Reference numeral 105 is a starting means provided in the information processing system 100 according to the present invention. Reference numeral 106 is a counting restarting unit provided in the information processing system 100 according to the present invention.

[0026]

The command analyzing means 103 is the information processing system 10.
0 analyzes whether a subroutine call instruction is executed while 0 is using the step break function 101.

The counting stopping means 104 is the instruction analyzing means 10
3 detects the execution of a subroutine call instruction,
The counting of the number of executed instructions in the step break function 101 is stopped.

When the instruction analyzing means 103 detects the execution of the subroutine call instruction, the starting means 105 designates the instruction next to the subroutine call instruction to the instruction break function 102 and starts using it.

The counting restart means 106 restarts counting of the number of executed instructions in the step break function 101 when the instruction break function 102 detects the execution of an instruction next to the subroutine call instruction.

The starting means 105 specifies the address A indicating the storage area of the instruction next to the subroutine call instruction to the instruction break function 102, and the instruction break function 102
Is considered to stop the process when the address of the instruction executed by the information processing system 100 matches the address A specified by the activation unit 105.

Therefore, even when the main routine including the subroutine call instruction is to be debugged, the step break function can be used by considering only the number of steps in the main routine, which improves the efficiency of the debugging work and is convenient for the debug executor. Significantly improved.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 2 is a diagram showing an information processing system according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of a step break process in FIG. The same reference numerals denote the same objects throughout the drawings. The debug target program is as shown in FIG.

In FIG. 2, a step break unit 2 and an instruction break unit 3 are shown as means for realizing the step break function 101 and the instruction break function 102 in FIG. 1, and the instruction analysis unit 103 in FIG.
Is provided with a subroutine call instruction detecting section 4, and as the counting stopping means 104 in FIG.
1, a starting unit 6 is provided as the starting unit 105 in FIG. 1, and the counting restarting unit 10 in FIG.
A counting restart unit 7 is provided as 6.

In FIGS. 2, 3 and 5, the debug executor desires to stop the main routine MR after executing up to step S10 _M , and designates the specified number N of steps.
= “10” and the start signal ST ₂ are changed to the step break unit 2
When you input to, the step break unit 2
After the designated step number N = “10” input to the designated step number register 21 is accumulated, the execution start signal st ₂ is transmitted to the processing device 1.

The processing device 1 which has received the execution start signal st ₂
In the same manner as described above, the steps S1 _M , S2 _M and S3 _M are sequentially stored in the instruction address register 11 as the instruction address a, and each instruction i of the main routine MR stored in the instruction register 13 is stored in the instruction execution unit. 12 and the instruction execution signal e is transmitted to the step break unit 2.

As a result, the step break unit 2 receives the designated number of steps N (= "1" each time the instruction execution signal e is received.
0 ") is updated to" 9 "," 8 ", and" 7 ". On the other hand, the subroutine call instruction detection unit 4 analyzes whether or not the instruction i is the subroutine call instruction SCI each time the instruction i executed by the processing device 1 is accumulated in the instruction register 13, and the instruction address a = step S1 _M Since neither of the instructions i stored in the instruction register 13 in S2 _M and S2 _M is the subroutine call instruction SCI, the step break unit 2 continues the above operation without outputting the detection signal d, but the instruction address a = In step S3 _M , it is detected that the instruction i stored in the instruction register 13 is the subroutine call instruction SCI, and the detection signal d is output and transmitted to the counting stop unit 5 and the activation unit 6.

Upon receiving the detection signal d, the counting stop unit 5 transmits the counting stop signal p to the step break unit 2,
After that, even if the instruction execution signal e is received from the instruction execution unit 12,
Number of designated steps N (= designated step number register 21
Specify not to subtract "7").

Upon receiving the detection signal d, the starting unit 6 sends the starting signal ST ₃ to the instruction break unit ₃ and the address a of the instruction next to the subroutine call instruction SCI (= step S3 _M ) as the designated instruction address A. = Step S4 _M
Enter and.

Upon receiving the start signal ST ₃ , the instruction break unit 3 stores the designated instruction address A (= step S4 _M ) input to the designated instruction address register 31 and then transmits it from the instruction address register 11. The instruction address a is collated with the designated instruction address A (= step S4 _M ) accumulated in the designated instruction address register 31.

On the other hand, the processing device 1 has a main routine MR.
Of, after executing the subroutine call instruction SCI specified by the step S3 _M, instruction address di Resta 1
1 sequentially stores steps S1 _{S to} S4 _S as the instruction address a, and each instruction i of the subroutine SR stored in the instruction register 13 is executed by the instruction execution section 12 and the instruction execution signal e is sent to the step break section 2. Is transmitted, but the step break unit 2 which receives the count stop signal p
Holds the designated step number N = “7” in the designated step number register 21 without updating even when the instruction execution signal e is received.

The processing device 1 executes the instruction i designated by the step S4 _S of the subroutine SR, so that the step S4 _M of the main routine MR designated by the subroutine call instruction SCI is used as the instruction address a. The instruction i, which is stored in the register 11 and next to the subroutine call instruction SCI of the main routine MR, is stored in the instruction register 13, and is executed by the instruction execution unit 12 and the instruction execution signal e is transmitted to the step break unit 2.

On the other hand, the instruction break unit 3 collates the instruction address a transmitted from the instruction address register 11 with the designated instruction address A (= step S4 _M ) stored in the designated instruction address register 31. , Step S4 as the instruction address a in the instruction address register 11
_{When M} is accumulated, the execution stop signal sp ₃ is transmitted to the counting restart unit 7.

Upon receiving the execution stop signal sp ₃ , the counting restart unit 7 stops the specified number of steps N (= ““ in the specified step number register 21 after receiving the counting stop signal p to the step break unit 2). The counting restart signal r for restarting the subtraction of 7 ”) is transmitted to the step break unit 2.

Upon receiving the counting restart signal r, the step break unit 2 outputs the instruction execution unit 12 by executing the instruction i next to the subroutine call instruction SCI in the main routine MR stored in the instruction register 13. Upon receiving the instruction execution signal e, the designated step number N (= “7”) is immediately subtracted by “1” step to update the designated step number N = “6”.

Thereafter, the processing unit 1 determines that the instruction address register
11 as the instruction address a in step S5_MThrough S10
_MAre sequentially stored and then stored in the instruction register 13.
Each instruction i of the routine routine MR is executed by the instruction execution unit 12.
And the instruction execution signal e is sent to the step break unit 2.
Upon transmission, the step break unit 2 causes the instruction execution signal e
From the specified number of steps N (= “6”) each time
In the instruction address register 11 after subtraction to the "1" step
Command address a of step S10_MAt that stage,
Since the designated step number N is updated to "0", the processing device 1
Execution stop signal sp ₂To convey.

The processing device 1 which has received the execution stop signal sp _2.
Stops the execution of the main routine MR. As is apparent from the above description, according to the present embodiment, the step break unit 2 stops the subtraction of the designated step number N while the processing device 1 is executing the subroutine SR, so that the processing device 1 debugs. desired by the practitioner, so that the stop after executing the main routine MR until step S10 _M.

It is to be noted that FIGS. 2, 3 and 5 are merely examples of the present invention until now. For example, the configuration of the program to be debugged is not limited to that shown in the figure, and there are a plurality of main routines MR. Subroutine SR is called or subroutine S called from the main routine MR
Many other variations, such as R calling another subroutine SR, are considered, but in any case, the effect of the present invention does not change. Further, the information processing system 1 to which the present invention is applied
The configuration of 00 is not limited to that shown in the figure, and for example, the subroutine call instruction detecting unit 4, the counting stopping unit 5, the starting unit 6, and the counting resuming unit 7 are realized by a program, and many other modifications are possible. However, the effect of the present invention does not change in any case.

[0048]

As described above, according to the present invention, in the information processing system, even when the main routine including the subroutine call instruction is to be debugged, the step break function is used by considering only the number of steps in the main routine. This makes it possible to significantly improve the efficiency of the debugging work and the convenience for the debug executor.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is an information processing system according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a step break process in FIG.

FIG. 4 is a diagram showing an example of a conventional information processing system.

FIG. 5 is a diagram showing an example of a debug target program.

6 is a diagram showing an example of a step break process in FIG.

[Explanation of symbols]

1 processor 2 step break section 3 Instruction break section 4 Subroutine call instruction detector 5 Counting stop 6 start-up section 7 Count restart unit 11 Instruction Address JILLESTA 12 Instruction execution unit 13 Instruction register 21 Specified step number register 31 Designated instruction address register 100 information processing system 101 Step break function 102 Instruction break function 103 Command analysis means 104 counting stop means 105 Starting means 106 counting restart means

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventors, various bridges Atsushi             3-9-18 Shin-Yokohama, Kohoku Ward, Yokohama City, Kanagawa Prefecture             Issue Fujitsu Comunication System             Within Co., Ltd. (72) Inventor Masaki Suzuki             1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture             Within Fujitsu Limited

Claims (2)

[Claims] 1. A step break function (1) for stopping processing after executing a specified number of steps (N) of instructions.
01) and an instruction break function (102) for stopping processing after executing a specified instruction, the information processing system (100) includes the step break function (101). Instruction analysis means (103) for analyzing whether or not to execute a subroutine call instruction during use
A counting stop means (104) for stopping the counting of the number of executed instructions in the step break function (101) when the instruction analysis means (103) detects the execution of the subroutine call instruction; and the instruction analysis means. When (103) detects the execution of the subroutine call instruction, the instruction break function (102) specifies an instruction next to the subroutine call instruction to start using, and an instruction break function (105). A counting restart means (106) for restarting counting of the number of executed instructions in the step break function (101) is provided when (102) detects execution of an instruction next to the subroutine call instruction. Step break processing method. 2. The starting means (105) designates an address (A) indicating a storage area of an instruction next to the subroutine call instruction to the instruction break function (102), and the instruction break function (102) is set. 2. The step according to claim 1, wherein the processing is stopped when the address of the instruction executed by the information processing system (100) matches the address (A) specified by the starting means (105). Break processing method.