JPH05120016A - Execution method for parallel logic-type language - Google Patents

Abstract

PURPOSE:To execute a program generated by means of parallel logic-type language at high speed by fetching the parallelism of the instruction levels of parallel logic-type language. CONSTITUTION:At the time of compiling the program 11 mentioned by parallel logic-type language by a compiler 12, the compiler 12 generates an instruction string consisting of respective codes for unifying the arguments A1, A2,... of a goal and the arguments A1, A2,... of a clause, a code for guard and a code for a body like a successive execution instruction string 14. The code for executing the arguments A1, A2,... of the goal and that of the arguments A1, A2,... of the clause are combined to a common VLIW instruction so as to generate a VLIW instruction string 15. When a VLIW parallel computer 16 executes the VLIW instruction string 15, the arguments of the goal and the arguments of the clause are simultaneously unified and it is executed at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to VLIW (very long).
instruction word) on a parallel computer of GHC, P
The present invention relates to an execution method of a parallel logic type language capable of executing a program created by the parallel logic type language at high speed by taking out the instruction level parallelism of the parallel logic type language such as arlog and KL1.

In recent years, a technique for generating a compile code so as to extract instruction level parallelism from a target language and executing the compile code in parallel by the VLIW method has attracted attention. In most cases, the target language heretofore was FORTRAN, which is mainly used for numerical calculation.

On the other hand, little research and development has been done to efficiently execute a parallel logic language called an artificial intelligence language on such a computer system. For parallel logic programming languages, the features of VLI can be used effectively.
There is a need for a technique that can be efficiently executed on a W parallel computer.

[0004]

2. Description of the Related Art Conventionally, parallel logic languages such as GHC, Parlog, and KL1 have been executed by a single serial processor or a system in which a plurality of serial processors are connected. In a computer system in which a plurality of processors are connected, so-called parallel execution was realized in each processor, but the parallel execution in this case was goal-level parallel execution, and instruction-level parallel execution was not realized.

[0005]

The present invention is based on GHC, P
It aims at providing a means for drawing out the parallelism at the instruction level, converting it to the compiled code of the VLIW parallel computer, and executing it at high speed by paying attention to the characteristics of the parallel logic type language such as arlog and KL1.

[0006]

FIG. 1 is a principle explanatory view of the present invention corresponding to claim 1. In FIG. According to the invention of claim 1, when compiling the guard part of the parallel logic language,
The code that performs unification of the goal argument and one close argument is compiled so as to be incorporated in a common VLIW instruction, and when the guard unit of the parallel logic language is executed, the VLIW parallel computer 16 and the goal argument
Unify the two closed arguments simultaneously.

For example, when compiling the program 11 described in the parallel logic type language shown in FIG. 1 by the compiler 12, the compiler 12 produces a sequential execution instruction sequence 14 based on the result of the syntax analysis and the semantic analysis. , Goal arguments A1, A2, ... and close arguments A1, A2
Each code for unification of ... and gu
An instruction sequence including a code for ard and a code for body is generated. Based on the sequential execution instruction sequence 14, goal arguments A1, A2, ... And close argument A
The codes for performing 1, A2, ... Are combined with a common VLIW instruction to generate a VLIW instruction sequence 15.

When this VLIW instruction sequence 15 is executed by the VLIW parallel computer 16, unification of the goal argument and one closing argument is performed at the same time, which results in high speed execution. In this example, VLI
The W instruction assumes that it can perform four operations at a time. In Fig. 1, in order to make it easier to catch
Although the codes for 1 to A4 are placed in each field without being mixed, in practice, the instructions may be mixed.

FIG. 2 is an explanatory view of the principle of the present invention corresponding to claim 2. According to the second aspect of the present invention, the code for performing the argument setting process of a plurality of body goals is common VLIW.
The VLIW parallel computer 16 compiles so as to be incorporated into an instruction, and the VLIW parallel computer 16 does not set the selected closing arguments one by one for each body goal, but simultaneously for a plurality of body goals.

For example, when compiling the program 11 described in the parallel logic type language shown in FIG. 2 by the compiler 12, the compiler 12 produces a sequential execution instruction sequence 14 based on the result of the syntax analysis and the semantic analysis. To he
An instruction sequence including a code for ad, a code for guard, and a code for each body goal a (A1), b (A2), c (A3) is generated. Based on this sequential execution instruction sequence 14, each of the body goals a (A1), b
The codes for (A2) and c (A3) are set to the common VLI.
Combined with the W instruction, the VLIW instruction sequence 15 is generated.

When this VLIW instruction sequence 15 is executed by the VLIW parallel computer 16, the three child goals of the body are generated at the same time. If there are four or more child goals to be generated, all four fields of the VLIW instruction will be filled.

FIG. 3 is an explanatory view of the principle of the present invention corresponding to claim 3. In the invention according to claim 3, the code for creating the list or vector structure used as the argument of the selected body goal for closing is compiled into a VLIW instruction that is combined with the code for the processing that does not depend on data in advance. , The VLIW parallel computer 16 does not create the list or vector structure at the time when it is needed in the instruction execution, but creates it in a data-independent part in advance.

For example, when compiling the program 11 written in the parallel logic type language shown in FIG. 3 by the compiler 12, the compiler 12 produces a sequential execution instruction sequence 14 based on the result of the syntax analysis and the semantic analysis. To he
An instruction sequence including a code for ad, a code for guard, and a code for each body goal a (A1), b (A2), c (A3) is generated. When the VLIW instruction sequence 15 is generated based on the sequential execution instruction sequence 14, the data of the list [a, b, c, d] used as the argument of the body goal b () and the preprocessing are performed. VLIW in which the code that creates the list [a, b, c, d] is combined with the code that does not depend on the data when the data dependence of
It is converted into an instruction and the VLIW instruction sequence 15 is generated.

That is, in this example, of the body goals, the list of the second argument of b / 2 is generated in advance by using the empty field of the VLIW instruction. The list created here is used when creating a b / 2 child goal. As a result, at the time of execution by the VLIW parallel computer 16, it is possible to save the time for creating complicated data structures such as lists and vectors.

[0015]

According to the present invention, as shown in FIGS. 1 to 3, the features of the parallel logic language language are utilized to compile into the VLIW instruction sequence 15 to bring out the parallelism at the instruction level. High-speed execution by the computer 16 becomes possible.

[0016]

Embodiments of the present invention will be described below by using KL1 as an example of a parallel logic language. The present invention can be similarly implemented for other parallel logic languages.

The parallel logic language KL1 is a language designed based on Flat GHC (Flat Guarded Horn Clauses) as is well known. The KL1 program is represented as a set of closes having the following syntax.

H: -G ₁ , ..., G _m | B ₁ , ..., B _n . (M ≧ 0, n ≧ 0) where H is the close head, G _i is the guard goal, and B is
_i is called a body goal. The operator “|” is called a commitment bar, and the part preceding the closing bar in the closing is called the guard part (or the passive part), and the part following the part is called the body part (or the active part).

Here, only a built-in predicate can be written as a guard goal. This is a restriction adopted in consideration of efficient realization while maintaining the language description capability of GHC. The origin of “flat” of flat GHC comes from this limitation. In addition, two types of built-in predicates and user-defined predicates can be written in the body goal, and the user-defined predicate has a priority for specifying the execution order and the processor to be executed when executing in a multiprocessor environment. This can be done by adding a function called a pragma for specifying.

How the KL1 program is executed will be described below. Now, suppose that the following program is given and the goal H is given. (The left side of "|" is the guard part and the right side is the body part.)
At this time, the goal H is executed according to the following rules. 1) What is written to the left of the commitment bar “|”,
To be precise, the head of a candidate clause and the goal H that calls that clause (Unification), and the execution of a guard goal may be executed in parallel for multiple candidate clauses. However, they must not embody H. If you try to materialize, the identification that causes the materialization will be interrupted. 2) What is written to the right of the commitment bar “|”,
That is, the body goal of a clause may instantiate the goal H that called that clause, but it can only do so if H is the only "selected" clause from among multiple candidate clauses.

FIG. 4 shows an example of a parallel logic language program, and shows a prime number generation program described in KL1. This program 11 finds prime numbers up to "Max".

Now, as a top-level goal, "pr
When "images (10, Res)" is given, the answer is "Res", and the list [2, 3, 5, 7] is returned. The calculation process will be described below.

First, when a top-level goal is given, the close guard part of the primes is successfully executed, and the body part is executed. At this time, gen (1,1
Two goals, 0, Ns) and shift (Ns, Ps) are generated. In terms of meaning, these two goals may be executed first.

If gen (1,10, Ns) is executed first, the execution of the first closed guard part of gen succeeds, so execution can continue as it is. If Ns, Ps) is executed first, the execution is interrupted by the unification of the first argument of the head part. This execution is suspended until the value of the variable Ns is determined. Therefore, in this program, gen
(1,10, Ns) always ends earlier.

Gen (1,10, Ns) returns a list whose elements are integers from +1 to (Max-1) given by Ns as the first argument. After that, shift (N
s, Ps) is executed. In the execution of shift, the head section divides the list into a Car section and a Cdr section, and then the filters (Xs, P, Ys) and shift (Y
s, Zs1) two goals are generated. even here,
Either of these goals may be executed first, but
If (Ys, Zs1) is executed first, the execution is interrupted because the first argument is not determined.

In the filter, the list obtained by removing the integer of the second argument and its multiple from the given list is returned to the third argument. As a result of these executions, a prime number is obtained. In the prime number generation program shown in FIG. 4, the filter / 3 program is taken as an example to explain how this program is compiled into the VLIW instruction and executed.

First, the results of compiling this program into a normal instruction code are shown in FIGS. 5 and 6. The code string shown here is called KL1-B and is an abstract instruction set of KL1. The instruction code used here is briefly described below.

[Try_me_else Label] The address indicated by Label is set in the register (ACP) indicating the next candidate close. If an instruction following this instruction fails or execution is interrupted, ACP
Branch to the address indicated by.

[Wait_list Reg] It is checked whether the data pointed to by the register indicated by Reg is a list. If it is a list, move to the next instruction. If it is not a list, branch to the ACP address (set by the try_me_else instruction).

[Read_car Ai, Aj] The car part of the list indicated by the register Ai is read and placed in the register Aj.

[Read_cdr Ai, Aj] The cdr portion of the list indicated by the register Ai is read and placed in the register Aj.

[Integer Ai] It is checked whether the content of the register Ai is an integer. If it is an integer, execute the next instruction. If it is not an integer, AC
Branch to address P.

[Modulo Ai, Aj, Ak] An integer modul held in the registers Ai, Aj.
Take o and put the result in the register Ak.

[Put_constantConst, Ai] The constant Const is placed in the register Ai. [Not_equal Ai, Aj] If the contents (integers) of the registers Ai, Aj are not the same,
Execute the next instruction, and if the same, branch to the ACP address.

[Collect_list Ai] The cons cell of the list pointed to by the register Ai is collected when a certain condition is satisfied.

[Put_list Ai] One cons cell for structuring the list is allocated and designated from the register Ai.

[Write_car_value Ai, Aj] Put the contents of the register Aj in the car part of the list pointed to by the register Ai. [Write_cdr_variableAi, Aj] One variable cell is allocated, placed in the cdr portion of the list pointed to by the register Ai, and pointed by the register Aj.

[Get_list_value Ai, Aj] Contents of register Aj (in most cases, undefined variable)
And unify the contents of the register Ai (this is a list). In many cases, the contents of Ai are A
Processing is completed by transferring to j.

[Put_value Ai, Aj] The contents of the register Ai are transferred to the register Aj. [Equal Ai, Aj] If the contents (integers) of the registers Aj, Aj are the same, the next instruction is executed, and if they are not the same, branch to the address of the ACP.

[Wait_constant Const, Ai] It is checked whether the content of the register Ai matches Const. If they are the same, execute the next instruction, and if they are not the same, branch to the ACP address.

[Collect_value Ai] The data pointed to by the register Ai is recursively collected. [Get_constantConst, Ai] It is checked whether the content of the register Ai matches Const. If Ai is undefined, set Const to Ai
To. If Ai is the same as Const, the next instruction is executed. If they are not the same, execution fails.

[Proceed] One new goal is taken out from the goal management area (this is called a goal stack), and goal reduction is started.

[Suspend Label] The execution of the goal indicated by Label is suspended, and this goal is hooked to the variable that caused the suspension of execution.

[Execute Label] Branches to the code address indicated by Label. [Create_goal Label] One area is reserved for placing the argument and code address of the goal indicated by Label. This is called a goal record.

[Set_value Ai, Gj] The content of the register Ai is placed at the position of Gj in the argument slot of the goal record. [Enqueue_goal Label] Place the goal record indicated by Label at the top of the goal stack.

[Write_car_constant Ai, Const] Cons in the car part of the list indicated by the register Ai.
put t. [Write_cdr_constant Ai, Const] Cons in the cdr part of the list indicated by the register Ai.
put t.

Sequential execution instruction sequence 14 shown in FIGS. 5 and 6.
4, the instruction sequence from (1) to (17) is the first filter close, (18) to (29) shown in FIG.
4 corresponds to the second filter close shown in FIG. 4, and the instruction sequence from (30) to (34) corresponds to the third filter close shown in FIG. (35) is an instruction for performing processing when execution is interrupted.

An instruction sequence as shown in FIGS.
It is converted into the VLIW instruction sequence 15 for execution by the LIW parallel computer 16. FIG. 7 shows V used in the embodiment of the present invention.
An example of a LIW parallel computer is shown.

The VLIW parallel computer 1 shown in FIG.
The instruction format executed by 6 is as shown in FIG. 7A, and the number of instruction fields is 3. Here, it is assumed that the function of each command field is uniform. However, the number of instruction fields and the homogeneity / inhomogeneity of each field depend on the individual architecture of the target parallel computer, and thus it is not essential to determine that the number of fields is 3 and that the fields are homogeneous. The VLIW parallel computer 16 reads a VLIW instruction having an instruction format as shown in (a) from the memory into the instruction cache 70, and for each instruction field, the decoder 7
1 is used for decoding, and the arithmetic unit 72 executes arithmetic operations simultaneously based on the decoding result. Arithmetic unit 7
2 accesses the data cache 73.

Sequential execution instruction sequence 14 shown in FIGS. 5 and 6.
Is converted into a VLIW instruction sequence 15, it is assumed that the number of instruction fields is 3, and the function of each field is uniform, so if there is no dependency between instructions, embed them in the instruction field one after another. Go!

In the dependency relationship between instructions, certain data is set in the argument register and then referred to as data dependency,
There is an inverse dependency called update after reference, and an output dependency that guarantees the order in which data is set in the same register.

In the present example, these dependencies are
Judges whether the register numbers of the instruction arguments are the same.
That is, if the same register number is used,
It is assumed that there is a dependency relationship, and the fields of the same VLIW instruction are not filled.

In the example of FIG. 5, since the instruction (1) must be executed before the instruction (2), the instructions (1) and (2) cannot be incorporated in one VLIW instruction. In order to show these relationships, a graph showing the dependency relationship between instructions as shown in FIG. 8 is created. The numerical values shown in FIG. 8 correspond to the instruction numbers (1) to (17) shown in FIG. In order to compile the VLIW instruction sequence 15, it is sufficient to fill the instruction code based on the graph shown in FIG.

The result of compiling in this way is shown in FIG. In this example, the target close is relatively easy, so
Although only two are used, it can be seen that it took 10 steps to execute 17 steps when executed sequentially.

In step 2 of the instruction sequence shown in FIG. 9A, it is simultaneously checked whether the first argument is a list and whether the second argument is data having an integer type. ing. In step 3, the list given by the first argument is decomposed at the same time. Further, in step 4, it is simultaneously checked whether or not the car part of the list given by the first argument is data having an integer type, and the operation of placing an integer 0 in the register. By compiling in this way, unification in the guard part can be performed at the same time.

In the compilation result shown in FIG. 9A,
The structure used in the body is not pre-made in the guard. When further optimization is performed by performing such an operation, the result is as shown in FIG.

However, in this case, if this close is not selected and another close is selected,
An operation such as releasing the memory area for the structure created in advance is required. However, in this case,
It can be executed in steps, and it is expected that the speed will be about twice as fast as the sequential case.

The above is a description of performing unification of the goal argument and one close argument in the execution of the guard unit at the same time. Next, an example of a method of simultaneously executing the closed body part in which many goals are written in the following body part will be described. Consider the following close.

P (X, Y):-true | q (x), r ([100 | X], Y), s ([Y], X), t (Y, X). The compile code for sequential execution of this example is shown in FIG.
And the sequential execution instruction sequence 14 shown in FIG.

When this instruction is sequentially executed, it takes 20 steps. The number of steps is 20 when execution is not interrupted, and the 21st instruction is an instruction for performing processing when execution is interrupted.

Now, the instruction sequence shown in FIGS. 10 and 11 is
Consider execution on a VLIW parallel computer 16 having three instruction fields shown in FIG. Most of this sequence of instructions is used to prepare the arguments for the goal of the body part. Therefore, consider preparing the arguments of this body goal in parallel.

In this example, steps (2) to (5), steps (6) to (12), and steps (13) to (19).
Are the argument preparation parts for t / 2, s / 2, and r / 2, respectively. This argument preparation part is simply set in the goal record of the value of the data in the current execution environment. Since the destination is always a new memory area, there is no need to consider the data dependency, and the data is simply set. The instruction sequence may be arranged in each field.
However, create_goal, enqueue_g
It is easier to make hardware if an instruction that may access a global variable such as oal is not placed in one VLIW instruction.

FIG. 12 shows an example of a compilation result obtained by converting the sequential execution instruction sequence 14 shown in FIGS. 10 and 11 into a VLIW instruction sequence. By assembling the compiled code as shown in FIG. 12, it can be executed in 8 steps, and it can be seen that the speed is more than doubled compared with 20 steps in the case of sequential execution.

[0064]

As described above, according to the present invention,
A program written in a parallel logic language such as a KL1 program can be used for VLI by utilizing the characteristics of the parallel logic language.
High-speed execution can be achieved by compiling and executing the instruction sequence of the W-type parallel computer.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating the principle of the present invention.

FIG. 3 is a diagram illustrating the principle of the present invention.

FIG. 4 is a diagram showing an example of a parallel logic language program for explaining an embodiment of the present invention.

FIG. 5 is a diagram showing an example of compilation into a sequential execution instruction sequence.

FIG. 6 is a diagram showing an example of compilation into a sequential execution instruction sequence.

FIG. 7 is a diagram showing an example of a VLIW parallel computer used in an embodiment of the present invention.

FIG. 8 is an explanatory diagram of a dependency relationship between instructions for explaining an embodiment of the present invention.

FIG. 9 is a diagram showing a compilation result according to an embodiment of the present invention.

FIG. 10 is a diagram showing an example of compiling a body part into a sequence of sequential execution instructions.

FIG. 11 is a diagram illustrating an example of compiling a body part into a sequential execution instruction sequence.

FIG. 12 is a diagram showing a compilation result according to an embodiment of the present invention.

[Explanation of symbols]

 10 Goal to be executed 11 Program of parallel logic language 12 Compiler 13 Compile code 14 Sequential execution instruction sequence 15 VLIW instruction sequence 16 VLIW parallel computer

Claims (3)

[Claims] 1. A goal of compiling a guard part of a parallel logic language language in a parallel logic language language execution method for executing a program (11) created by a parallel logic language language on a VLIW parallel computer (16). The code that performs the unification of the arguments of
A method for executing a parallel logic language characterized by compiling so as to be embedded in a LIW instruction and performing unification of a goal argument and one closed argument at the same time by a VLIW parallel computer in executing a guard part of the parallel logic language .. 2. In a parallel logic language execution method for executing a program (11) created by a parallel logic language language on a VLIW parallel computer (16), a common code for setting arguments of a plurality of body goals is shared. Compile to be incorporated into the VLIW instruction of
A method for executing a parallel logic language, characterized in that the selected closing arguments are not set for each body goal one at a time, but for a plurality of body goals simultaneously. 3. A list or a list used as an argument of a selected closed body goal in a parallel logic language execution method for executing a program (11) created by a parallel logic language language on a VLIW parallel computer (16). When the list or vector structure is needed in the VLIW parallel computer by compiling the vector structure creation processing code into a VLIW instruction that is combined with the previous data independent processing code. A parallel logic language execution method characterized in that it is created in advance in a place that does not depend on data, instead of in.