JPH0511897A - Information processing unit - Google Patents

Abstract

PURPOSE:To offer the information processing unit which operates with small current consumption. CONSTITUTION:Normal processes which do not require high-speed operation are performed with a low-speed clock and a low voltage to reduce the current consumption. For specific processes which require the high-speed operation, the clock and voltage are switched to a high-speed clock and a high voltage and the high-speed operation is performed for a certain period. Namely, the clocks and voltages are switched with a frequency switching signal and a voltage switching signal generated by a CPU block 10 according to the process contents. Consequently, the processes which require the high speed operation are not reduced in speed and the current consumption is reducible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device that operates with low current consumption, and more particularly to a portable information processing device such as a notebook computer.

[0002]

2. Description of the Related Art Due to recent technological innovations, small and lightweight portable personal computers have become mainstream. When such a portable personal computer is used outdoors, power is usually supplied by an internal battery such as a battery. However, since the internal battery installed in a portable computer is limited to a small one,
There is very little time that a computer can be used on a single charge. For this reason, many portable personal computers have been devised in various ways to reduce current consumption.

[0003]

By the way, CMOS (Complement) often used in portable personal computers.
In an (ary MOS) IC, there is a correlation between the voltage, the frequency, and the current consumption. The higher the voltage, the faster the operation, but the current consumption increases accordingly. For this reason, there is a contradiction at the device level in a device such as a portable personal computer that requires high processing speed and low current consumption at the same time.

It is an object of the present invention to provide an information processing apparatus which solves such a contradiction and is capable of simultaneously increasing the processing speed and reducing the current consumption.

[0005]

In order to solve the above-mentioned problems, the information processing apparatus of the present invention operates with a low-speed clock and a low voltage for normal processing, and with a high-speed clock and a high voltage only for a specific processing. Operate.

[0006]

According to the information processing apparatus of the present invention, normal processing which does not require high-speed operation is executed under a low-speed clock and a low voltage, and current consumption is reduced. Then, the specific processing that requires high-speed operation is switched to the high-speed clock and the high voltage and is executed at high speed for a certain period. In this way, the clock and voltage are switched according to the processing content, so that the current consumption can be reduced without reducing the processing speed that requires high-speed operation.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a circuit configuration diagram of an information processing apparatus according to an embodiment of the present invention. The information processing apparatus of this embodiment includes
CPU block 10 for controlling the entire apparatus and external device 1
An input / output block 110 for controlling the liquid crystal display device 70, a video block 210 for controlling the liquid crystal display device 290, and a power supply device 310 for supplying electric power to these blocks are provided. Further, a frequency switching signal is given from the CPU block 10 to the video block 210, and the power supply 3
A voltage switching signal is applied to the CPU 10 from the CPU block 10. The voltage value of the power supplied from the power supply device 310 to each block can be switched by this voltage switching signal. As described above, the frequency switching signal and the voltage switching signal generated from the CPU block 10 switch between the first mode in which the low-speed clock and the low voltage operate and the second mode in which the high-speed clock and the high voltage operate.

Next, regarding the configuration of the CPU block 10, the input / output block 110 and the video block 210,
This will be described with reference to FIGS. FIG. 2 shows the CPU block 1
It is a block diagram of 0. The CPU block 10 includes a CPU 20 that controls the entire apparatus, a coprocessor 30 such as a floating point arithmetic processor, a crystal oscillator 40 that generates a clock pulse having a frequency of 40.0 MHz, and 3
A crystal oscillator 50 that generates a clock pulse having a frequency of 2.0 MHz, and a main RAM 6 that stores an operating system and application programs.
0 and EP that stores BIOS (basic I / O system)
A ROM 70 and a control unit 80 for exchanging signals with the input / output block 110 and the video block 210 are provided. In addition, the control unit 80 has a CP
CPU controller 81 for controlling U20, main RAM 60 and system bus, and CPU controller 81
The voltage value of the signal from the crystal oscillators 40 and 50 given to
A voltage converter 82 for converting V to 3V, and a voltage converter 83 for converting the voltage value of the output signal from the CPU controller 81 to the input / output block 110 and the video block 210 from 3V to 5V are provided. Further, the voltage converter 83 outputs a frequency switching signal to the video block 210 and a voltage switching signal to the power supply device 310. C
PU 20, coprocessor 30, main RAM 60, EP
The voltage values of the ROM 70 and the CPU controller 81 are
By applying the voltage switching signal to the power supply device 310, the voltage is changed between 3V and 5V in real time. The operation of the apparatus main body is determined in synchronization with the frequency of the clock signal to the CPU 20. Therefore, simply lower the frequency of the clock signal to the CPU before lowering the voltage,
It is possible to drop the clock frequency of all other devices synchronously. For this reason, all control signals are output via the CPU block 10.

FIG. 3 is a block diagram of the input / output block 110. The input / output block 110 includes a crystal oscillator 12 that generates a clock pulse having a frequency of 20.0 MHz.
0, and a crystal oscillator 130 that generates clock pulses having frequencies of 16.0 MHz, a VFO circuit 140 that is a variable frequency generation circuit, and a real-time clock 15
0, and a control unit 160 that controls the external device 170
Also, a control unit 164 is provided. The control unit 160 includes an input / output controller 161 for performing DMA (direct memory access) control, FDD (floppy disk device) control, interrupt control, printer control, and the like, and signals from the CPU block 10 and the like given to the input / output controller 161. A voltage converter 162 for converting a voltage value from 5V to 3V, and an input / output controller 161.
From 5V to the external device 170 output signal voltage value from 5V
The voltage converter 163 which converts into V is provided. Further, the control unit 164 is provided with a timer control circuit, an RS-232C control circuit, or the like. Further, the external device 170 includes an FDD, a printer, a mouse,
There are RS-232C and keyboard. Also, the external device 170 has a 5V interface for compatibility with conventional devices. Therefore, the voltage conversion circuit 163 is provided so that the signal voltage to the external device 170 does not change even if the internal voltage changes. The voltage value of the input / output controller 161 changes in real time between 3V and 5V when the voltage switching signal from the CPU block 10 is applied to the power supply device 310. Clock-related signal lines such as the real-time clock 150 and P
The VFO circuit 140 to the FDD based on the circuit system in which the voltage characteristic is related in the analog circuit such as the LL circuit is
Must operate at constant voltage. Therefore, these interfaces are 5V level interfaces. The controller unit 160 operates normally even when the voltage becomes 3V because the signal from the CPU block 10 has a low frequency. However, the controller unit 164 includes circuits such as a timer control circuit and an RS-232C control circuit that must not change the frequency in real time. Therefore, the voltage cannot be lowered to 3V, so that the device is operated at a voltage of 5V.

FIG. 4 is a block diagram of the video block 210. The video block 210 includes a crystal oscillator 22 that generates a clock pulse having a frequency of 21.0 MHz.
0, a frequency selector 230 that inputs a frequency switching signal from the CPU block 10 and converts the frequency of a clock pulse generated in the crystal oscillator 220, an SRAM 240 that stores text data, and a DRAM 250 that stores graphic data. , A CG (character generator) 260 for converting data from the CPU block 10 into a character pattern, a GDC (graphic display controller) 270 for controlling screen display, and a control unit 280 for controlling a liquid crystal display 290. . The control unit 280 has an SRAM
A video controller 281 for controlling the 240 and the like, and a frequency selector 230 for giving the video controller 281
From the voltage converter 282 for converting the voltage value of the signal from the CPU block 10 and the signal from the CPU block 10 from 5V to 3V, and the voltage value of the output signal to the liquid crystal display 290 from 3V to 5V.
And a voltage converter 283 for converting to V. A frequency switching signal is sent from the CPU block 10 to the video block 210. This is video block 2
It is necessary to drop the frequency when the voltage V _DD within 10 becomes 3V. Further, if the clock frequency given to the video block 210 and the value of the frequency given to the CPU block 10 are significantly different, the video block 210 may malfunction. Therefore, the CPU block 1
When dropping the frequency given to 0, video block 2
The frequency given to 10 is also dropped at the same time. S
RAM240, DRAM250, CG260, GDC2
70 and the voltage value of the video controller 281 are CP
When the voltage switching signal from the U block 10 is applied to the power supply device 310, the voltage changes from 3V to 5V in real time. Further, the crystal oscillator 220 always operates at a voltage of 5V. This is because the output is not stable when the voltage changes. Further, the external interface such as the CPU block 10 is 5V single in order to keep the bus specifications the same as before. Therefore, the voltage converter 282 converts the voltage value of the external signal from 5V to 3V.

The feature of this embodiment is that it operates under a low speed clock and a low voltage in normal processing, and when a specific factor such as an I / O access or an interrupt occurs, it operates at a high speed for a predetermined time. Switch to clock and high voltage. If a certain IC operates at 5V and the delay time from the input to the output is 10 ns, the delay time increases to 20 ns at the operation at 3V. Therefore, in order to operate normally at 3V, it is necessary to reduce the frequency as compared with when operating at 5V. The frequency is proportional to the current consumption, and the square of the voltage is proportional to the power consumption. For this reason, in this embodiment, the epoch-making low current consumption is realized by simultaneously reducing the frequency and the voltage. The clock switching is completely performed only by the circuit, and the timing of this switching is matched with the refresh period. This is because the bus is released during the refresh period, and the bus always occurs at regular intervals. Further, when the voltage is switched, the level of the interface between the ICs also changes at the same time. Since it usually takes several ms to several tens of ms to change the voltage, n
For a signal line changing on the s order, the change in voltage is so small that it can be ignored. However, if abnormal noise occurs in the voltage or the change time is so short that it cannot be ignored, reversal of the level between the interfaces may occur, so be careful. Further, in this embodiment, the lowest frequency that can be switched is the clock frequency corresponding to the lowest performance of the conventional model. Regarding the voltage value, the value corresponding to the lowest frequency is also the lowest voltage value. With such consideration, it is possible to operate with the current consumption corresponding to the minimum clock and the minimum voltage that does not impair the compatibility with the conventional model.

In this embodiment, since the switching of the voltage value and the frequency is completely controlled by hardware without the intervention of software, it is not necessary to change the existing program. An example of a circuit for switching the voltage value of the power supplied from the power supply device 310 to each block by hardware is shown in FIGS. In FIG. 5A, the terminal 350
The voltage signal of 7V to 15V from the power supply device 310 (usually the output from the Ni-Cd storage battery) is applied to the FET.
351 causes the voltage to drop to a maximum of 3 V, and the terminal 35
It is output from 2. Then, the voltage signal output from this terminal 352 is sent to each block. More specifically, the voltage from the control IC 353 is applied to the gate of the FET 351 at certain intervals, and the voltage value output from the terminal 352 is adjusted. Further, a feedback signal is given to the control IC 353 to adjust the interval of the voltage applied to the FET 351.
This feedback signal changes according to the resistance value ratio of the resistors 354 and 355. That is, the resistors 354 and 355.
The voltage value of the voltage signal output from the terminal 352 is switched in accordance with the resistance value ratio of Therefore, the resistor 35
5, a resistor 356 is provided in parallel, and the value of the feedback signal is changed by applying a voltage switching signal to the gate of the FET 357 to switch the voltage value of the voltage signal output from the terminal 352. A problem with such a circuit is that noise such as undershoot occurs during the output in the intermediate state where the feedback signal is changing. In order to solve this problem, FIG.
As shown in (a), the capacitor 35 is connected to the other end of the resistor 354.
In some cases, 8 is set. Moreover, another circuit example in which noise is not generated is shown in FIG. In FIG. 5B, the terminal 3
The voltage signal of 5V from the power supply device 310 and the voltage signal of 3V from the three-terminal regulator 362, which are given to 60, are selected by the FET 361, and one of the voltage signals is output from the terminal 363. A voltage switching signal is applied to the gate of the FET 361, and the voltage value of the voltage signal output from the terminal 363 is switched in a time of about several ms. In this circuit, noise like that generated in the circuit of FIG. 5A does not occur. That is, the voltage switching signal, which causes the voltage signal to change in real time as in the waveform diagram of FIG. 6, instantaneously switches between ON and OFF, so that noise such as undershoot does not occur. Like the graphic DRAM 250 in the video block 210 of FIG. 4, the memory is not SRAM but DR.
In the case of AM, it is usually impossible to change the voltage like + 5V to + 3V. This is because even if the cell is charged with a high level voltage at + 3V, it may be determined to be a low level voltage at + 5V. Therefore, as shown in FIG. 8, a refresh signal is input for each constant voltage in the voltage change period. As a result, the voltage can be changed even in the DRAM.

Further, the timing of voltage switching and frequency switching will be described with reference to FIG. Switching of the clock signal can be performed on the order of ns, but switching of the voltage takes about 5 ms to 20 ms. Therefore, even if the switching of the voltage is performed too frequently like the switching of the frequency of the clock, there is a possibility that the voltage variation is increased and the opposite effect is obtained. Therefore, change the time to switch the frequency (ms to several s) and the time to switch the voltage,
The time for switching the voltage is set to several seconds to several tens of seconds. Specifically, in order to drop the voltage from 5V to 3V, the voltage switching signal is dropped to the low level after several seconds or more have passed since the frequency switching signal went to the low level. Further, in order to raise the voltage from 3V to 5V, the voltage is raised after the frequency switching signal becomes high level, and the actual frequency is not made high until the voltage rises completely. However, when raising the voltage in this way, even if high-speed processing is required immediately, it is necessary to wait until the voltage is completely raised. This time is a factor of performance degradation. Therefore, as shown in FIG. 9, a voltage monitoring IC is provided,
The frequency high speed permission signal 372 that goes to a high level is output when the voltage becomes 4.5 V, which enables high speed operation.
The frequency fast enable signal 372 allows the system to speed up quickly and minimize performance degradation. By switching in this way, it is possible to always obtain the highest performance and the lowest power consumption while operating various applications.

Further, as the clock frequency at the low speed in the power save mode which is the first mode, the clock frequency corresponding to the lowest performance of the conventional model is used and the compatibility with the existing program is maintained. This is because if the frequency is further lowered, malfunction may occur depending on the existing program. With this kind of consideration,
The CPU 20 can be operated with the lowest clock that does not impair compatibility, and the current consumption of the information processing device can be reduced. And when switching the frequency from low speed to high speed, instead of switching to the highest frequency,
The CPU controller 81 functions to return to the clock frequency specified in advance. By this switching, compatibility of existing programs at high speed can be maintained. In addition, in order for the user to know at which frequency the CPU 20 is currently operating, the L for display is displayed in a different color for each frequency.
The ED (diode) is lit. For example, 16MH
Is green at 10 MHz, orange at 10 MH, red at 5 MH, and so on. In addition, the user is 5MH
When z is set, low voltage operation is automatically performed. FIG. 10 shows a schematic diagram of such a display LED. The LED 402 indicating the clock frequency is laid out second from the left. When the LED 402 is off, it means that the LED is in the power-off state or in the power save mode and operating at a low speed. When the power is off, all other LEDs 401, 403-4
Since 08 is also turned off, the user can know the power save mode by the display of the LED 402. That is, the user operates the information processing apparatus in the power save mode when, for example, the rightmost LED 408 that displays the remaining battery level is on and the LED 402 that displays the clock frequency is off. I understand that.

The information processing apparatus according to the present embodiment normally operates at a low speed clock and a low voltage, and operates at a high speed clock and a high voltage for a certain period depending on a specific factor. A normal mode (second mode) operating with a clock and a high voltage can be selected. These modes are set in advance in the system environment table, and are automatically initialized when the information processing apparatus is powered on. Further, even when the information processing apparatus is operating, it can be changed by a desired combination operation of a plurality of keys of the keyboard device.
That is, while operating in the power save mode, for example, "C
By pressing the "TRL" key, the "GRPH" key, and the "P" key, the mode is changed to the normal mode. On the contrary, it is possible to change to the power save mode by performing the same key operation during the operation in the normal mode. As described above, since such a mode change is performed during the refresh period, an error does not occur even when the mode is changed during the execution of the application program.

Next, the details of the power save mode will be described. The power save mode is different from the conventional power management in that the CPU clock is switched and the voltage is switched in a short time (second unit).
This is a method of reducing power consumption. In the power save mode, the clock frequency and the low voltage are usually low, and the clock frequency and the high voltage are switched to the high speed only when a specific factor such as a key input occurs. This is because with word processing software or the like, it is necessary to operate at a high clock frequency only during conversion and key input, and a slow clock frequency is sufficient for the time of thinking a sentence. In the power save mode, the power consumption is reduced by providing the minimum clock frequency at which the application program or the like can operate without problems and by setting the voltage to a low voltage. Certain factors that change the clock frequency and voltage include I /
O access, interrupt, etc. First, I / O access will be described. A typical application program used by a user is analyzed to extract I / O access required to operate at a high-speed clock frequency. Then, only when the extracted I / O access occurs, the clock frequency is increased for a certain period. Next, the interrupt will be described. The information processing device is operated at the high-speed clock frequency for a certain period even after the return (EOI) command is returned only in a specific interrupt cycle of the keyboard device, RS-232C, hard disk device, etc. is there.

[0018]

According to the information processing apparatus of the present invention, normal processing that does not require high-speed operation is executed under a low-speed clock and a low voltage to reduce current consumption. Then, the specific processing that requires high-speed operation is switched to the high-speed clock and the high voltage and is executed at high speed for a certain period. In this way, the clock and voltage are switched according to the processing content, so that the current consumption can be reduced without reducing the processing speed that requires high-speed operation.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a CPU block.

FIG. 3 is a circuit configuration diagram of an input / output block.

FIG. 4 is a circuit configuration diagram of a video block.

FIG. 5 is a circuit diagram of a voltage switching circuit.

FIG. 6 is a waveform diagram showing voltage fluctuations.

FIG. 7 is a waveform diagram showing voltage fluctuations.

FIG. 8 is a waveform diagram showing voltage fluctuations.

FIG. 9 is a circuit diagram of a monitoring IC.

FIG. 10 is a schematic view showing a display LED.

[Explanation of symbols]

10 ... CPU block 110 ... Input / output block 170 ... External device 210 ... Video block 290 ... Liquid crystal display 310 ... Power supply device

Claims (10)

[Claims] 1. An information processing apparatus, wherein normal processing operates with a low-speed clock and a low voltage, and operates only with a high-speed clock and a high voltage only in a specific processing. 2. A high-speed clock and a high voltage are constantly determined by determining which of an external power source and a built-in battery is supplying power, and when the external power source is supplying power, the switching process of the switching means is invalidated. The information processing apparatus according to claim 1, further comprising: a determination unit that operates in accordance with item 1. 3. The information processing apparatus according to claim 1, wherein the clock frequency display diode is turned off while operating at a low speed clock and a low voltage. 4. A low speed clock and low voltage operation,
2. The information processing apparatus according to claim 1, wherein the switching of the operation with the high speed clock and the high voltage is performed without changing the software. 5. A first mode, which normally operates with a low-speed clock and a low voltage, and operates with a high-speed clock and a high voltage for a certain period depending on a specific factor, and a second mode which always operates with a high-speed clock and a high voltage. An information processing apparatus comprising a switching means. 6. An information processing apparatus equipped with a keyboard device, which normally operates at a low speed clock and a low voltage and operates at a high speed clock and a high voltage for a certain period depending on a specific factor, and a always high speed clock and A switching means for switching the second mode operating at a high voltage; and a selection means capable of selecting one of the first mode and the second mode by a desired combination operation of a plurality of keys of the keyboard device. Information processing device. 7. A determination is made as to whether power is being supplied from an external power source or a built-in battery, and when power is being supplied from an external power source, the switching processing of the switching means is invalidated and always executed in the second mode. The information processing apparatus according to claim 5 or 6, further comprising: a determination unit that causes the determination. 8. The information processing apparatus according to claim 5, wherein the clock frequency display diode is turned off while operating in the first mode and at a low speed clock and low voltage. 9. The information processing apparatus according to claim 5, wherein a refresh signal is input for each constant voltage while the high voltage and the low voltage are switched in the first mode. 10. The information processing apparatus according to claim 5, wherein the switching of the mode by the switching unit is performed without changing the software.