JPH05115057A - Video signal conversion circuit - Google Patents

Abstract

PURPOSE:To provide a processing circuit capable of effectively suppressing the occurrence of line flicker in the video signal conversion circuit converting a video signal of the non-interlace system into a video signal of the interlace system. CONSTITUTION:A processing circuit 4 is provided with a comparator 14 comparing luminance components of video signals on scanning lines at both sides with each object scanning line inbetween and selecting a larger luminance component and a subtractor circuit 15 subtracting a luminance component of a video signal on an object scanning line from the luminance component selected by the comparator 14, and also with a gate circuit 16 comparing a difference signal outputted from the subtractor 15 with a prescribed value and passing a difference signal when the difference signal is larger, a coefficient circuit 17 multiplying a prescribed coefficient with a difference signal passing through the gate circuit 16 and with an adder circuit 18 adding an output of the coefficient circuit 17 with a luminance component on the object scanning line.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a video signal output from an information processing device such as a personal computer.
The present invention relates to a video signal conversion circuit for converting a video signal according to a television broadcasting system such as NTSC, PAL, SECAM, and HDTV.

[0002]

2. Description of the Related Art Recently, personal computers have become widely used in homes. A personal computer is usually an input device such as a keyboard or a mouse, a device body that executes various arithmetic processes based on commands and data input by operating the input device, a CRT that displays input data or arithmetic process results, and the like. The display device is a non-interlaced system for outputting video to the display device.

On the other hand, NTSC, PAL, SECA
All current television broadcasts such as M are performed by the interlace system. HDTV broadcasting is also performed by the interlace system.

Therefore, in order to display the video signal output from the computer on the television receiver, a video signal conversion circuit for scanning conversion of the non-interlace system to the interlace system is used.

[0005]

However, when the non-interlace system is converted to the interlace system, the problem of line flicker occurs. When displaying a moving image, this is not a serious problem, but when displaying a still image including characters and figures, considerable flickering occurs. Since there are many still images including characters and figures in computer images, line flicker becomes severe and unsightly when displayed on a television receiver.

The principle of occurrence of line flicker will be briefly described. For example, when a luminance signal exists only in one horizontal scanning line in an odd field, this luminance signal appears only in the odd field and appears in the even field. do not do. As a result, in NTSC, HDTV, etc., about every 1/30 second,
In PAL, SECAM, etc., a luminance signal appears every 1/25 second, and it becomes perceptible to the human eye as flicker. This is line flicker. The larger the difference in brightness, the more noticeable the line flicker becomes.
It is known that the closer to the screen or the larger the screen, the greater the degree to the viewer's eyes.

As a method of suppressing the line flicker, there is a method of filtering in the vertical direction. In this case, although the line flicker is suppressed, there is a problem that the entire screen is blurred.

In addition, a method has been devised in which white or a pixel close to white which is vertically adjacent to black or a pixel close to black is changed to gray. In this case, for example, a character composed of a thin line is not displayed. Although most of the pixels that make up the character and the like are gray, in pixels such as "I" where the pixels are vertically arranged, most of the pixels except the pixels at the upper and lower ends remain white. Therefore,
If many characters are displayed on the screen, most of the characters will be slightly dark, but the screen will be unsightly, with only the vertical lines included in the characters remaining white.

An object of the present invention is to solve the above-mentioned problems of blurring of the entire screen, darkening of characters composed of thin lines, and conspicuous vertical lines included in characters, and yet Another object is to provide a video signal conversion circuit that can effectively suppress the occurrence of line flicker.

[0010]

A video signal conversion circuit according to the present invention comprises a processing circuit for performing line flicker suppression processing on a non-interlaced video signal, and a storage means for storing the video signal processed by the processing circuit. And a control means for reading out the video signals from the storage means in the order according to the interlace method and outputting the video signals in a predetermined format.

Further, the processing circuit compares the video signals on the two scanning lines on both sides of each scanning line to be processed (target scanning line) with each other, and selects a high-luminance video signal. Means, subtraction means for creating a difference signal by subtracting the video signal on the target scanning line from the video signal selected by the selection means, and comparing the difference signal output from the subtraction means with a predetermined value, When the difference signal is larger, an adjusting unit that outputs an adjusting value obtained by performing a predetermined function process on the difference signal, and an adjusting value output from the adjusting unit are added to the video signal on the target scanning line. And adding means.

[0012]

In the above processing circuit, the selection means allows
The video signals of the pixels (adjacent pixels) on both sides in the direction orthogonal to the scanning line direction sandwiching the pixel on the target scanning line (target pixel) are compared with each other, and the video signal with the higher luminance is displayed for each target pixel. Then, the subtracting means creates a difference signal by subtracting the video signal of the target pixel from the video signal selected as described above, and further the adjusting means determines that the difference signal is larger than a predetermined value. As a result, a location where there is a risk of occurrence of line flicker, that is, a target pixel to be subjected to the line flicker suppression process is specified.

The adjusting means applies a predetermined 1 to the difference signal, for example.
An adjustment value for the line flicker suppressing process is created by performing a functional process such as multiplying by a coefficient less than. The addition means adds the adjustment value to the video signal of the target pixel and outputs the addition result as a new video signal for the target pixel.

As a result, only when a pair of adjacent pixels existing across the target pixel have a luminance difference larger than a predetermined value, that is, the location where line flicker may occur, the The video signal of the target pixel is changed and set so that the brightness difference becomes small, and line flicker is prevented.

It should be noted that the luminance component is extracted from the video signal, the line flicker occurrence location is specified based on the luminance component, and the line flicker suppressing process is applied to the luminance component, so that the human eye can see it. It is possible to more accurately determine a portion that appears as flicker, and it is possible to perform more effective flicker suppression processing.

[0016]

According to the video signal conversion circuit of the present invention, a portion where there is a risk of occurrence of line flicker is accurately determined, and the line flicker suppressing process is applied only to that portion. The occurrence of line flicker is effectively suppressed while maintaining the image quality without causing the blur.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a video signal conversion circuit according to the present invention for an NTSC television receiver will be described below with reference to FIGS.

FIG. 1 shows the overall structure of a circuit for converting a non-interlaced video signal output from a computer (not shown) into an interlaced NTSC composite video signal for output. The non-interlaced R / G / B signals from the computer are
Input to matrix circuit (1), matrix circuit
In (1), the R, G, and B component video signals are matrix-converted into luminance and color component video signals and output. In this embodiment, the Y, R-Y, and B-Y component video signals are output by matrix conversion.

The output of the matrix circuit (1) is a filter
Input in (2). The filter (2) is a video signal (YR-
The high frequency component (Y · B−Y) is cut and output, and the output of the filter (2) is input to the A / D conversion circuit (3). A /
The D conversion circuit (3) converts the video signal (Y, RY, BY) from an analog signal to a digital signal and outputs it.

Among the outputs of the A / D conversion circuit (3), the Y signal is input to the processing circuit (4), and the RY signal and the BY signal are input to the delay circuit (5). The processing circuit (4) performs a process of suppressing line flicker, and its specific configuration and operation will be described later. The delay circuit (5) is RY
The signal and the BY signal are subjected to a delay process (a delay of one horizontal scanning period in this embodiment) corresponding to the delay amount of the Y signal by the processing circuit (4).

Output (Y signal) of the processing circuit (4) and delay circuit
The output of (5) (the RY signal and the BY signal) is input to and stored in the frame memory (6). Further, the horizontal and vertical synchronizing signals are sent from the above-mentioned computer to the write control circuit.
Input in (7). In the write control circuit (7), the A / D
A clock required for conversion and a control signal to be stored in the frame memory (6) are created, and the A / D conversion circuit (3),
Processing circuit (4), delay circuit (5), and frame memory (6)
Is supplied to.

1, 2, 3, 4, ... In the frame memory (6)
・ Video signals (Y, R, Y, B, Y) stored in non-interlace like lines are 1, 3, 5, ...
It is read by interlacing like 2, 4, 6, ... Lines. Then, the video signals (Y, R, Y, BY) read from the frame memory (6) are transferred to the D / A conversion circuit.
It is input to (8) and converted from a digital signal to an analog signal.

The output of the D / A conversion circuit (8) is the filter (9).
Is input to the encoder (10) and unnecessary high-frequency components are cut, and then input to the encoder (10), converted into a signal for a television receiver such as a composite signal, and output. or,
In the read control circuit (11), a control signal for reading the frame memory (6), a clock necessary for D / A conversion, etc., and horizontal and vertical sync signals such as NTSC are created, and the frame memory (6) , D / A conversion circuit (8) and encoder (10).

As shown in FIG. 2, the processing circuit (4) has a first delay circuit (12) having a delay time of one horizontal scanning period (1H).
And a second delay circuit (13), the Y signal output from the A / D conversion circuit (3) is the first and second delay circuits (12) and (13).
After being delayed by 2H, it is connected to one input end of the comparison circuit (14). Also, at the other input end of the comparison circuit (14),
The Y signal from the A / D conversion circuit (3) is directly connected. As a result, the comparison circuit (14) compares the two input signals and outputs the higher luminance value for each target pixel.

The signal A output from the comparison circuit (14) and the Y signal B delayed by 1H by the first delay circuit (12) are
Each of them is connected to both input terminals of the subtraction circuit (15), whereby the difference (AB) between both signals is output to the gate circuit (16).

The gate circuit (16) outputs the same value to the coefficient circuit (17) when the value of each pixel of the difference signal (AB) is equal to or more than a predetermined value, and outputs the value as it is to the coefficient circuit (17). 0 is the coefficient circuit (1
It is output to 7). The coefficient circuit (17) multiplies the output signal of the gate circuit (16) by a predetermined coefficient. In the case of the present embodiment, the shift register constitutes the coefficient circuit (17),
By shifting the 8-bit data by 1 bit, the value of the signal is attenuated to 1/2.

The output of the coefficient circuit (17) is the first delay circuit (12).
Is added to the Y signal delayed by 1H by the adder circuit (18) and output to the frame memory (6).

According to the processing circuit (4) configured as described above, there is a difference in luminance larger than a predetermined value between pixels (adjacent pixels) above and below a pixel (target pixel) on one horizontal scanning line. If not, that is, if there is no fear of occurrence of line flicker, the output of the gate circuit (16) becomes 0, so the addition circuit (1
8) is an addition with 0, and the value of the input signal is output to the frame memory (6) without any change.

On the other hand, when there is a luminance difference larger than a predetermined value between pixels (adjacent pixels) above and below a pixel (target pixel) on one horizontal scanning line, that is, when line flicker may occur. Of the difference from the Y signal of the adjacent pixel, the larger difference is output from the gate circuit (16), and the difference signal is further attenuated to 1/2 by the coefficient circuit (17). Is input to the adder circuit (18).

As a result, of the luminance difference between the Y signal of the target pixel and the Y signal of the adjacent pixel, one half of the larger difference is obtained.
The signal to which the value of is added is output to the frame memory (6). As a result, the difference in luminance between the odd field and the even field is reduced, and the line flicker is suppressed.

FIG. 3 illustrates the operation of the processing circuit (4). For simplification of the description, it is assumed that the pixels on each horizontal scanning line have the same brightness, and the brightness changes in the horizontal direction. It is omitted, and only the brightness change in the vertical direction is abstracted.

Non-interlaced video signal in the figure
If there is a luminance change as shown in (a), if the process of the present invention is not performed and this is simply converted into an interlace system, odd-numbered lines 1H, 3H, 5H shown in (b) in the figure are displayed.
The odd field is constructed by ... and in the figure
The even fields 2H, 4H, 6H, ... Shown in (c) form an even field. In this case, a high-luminance pixel exists in the fifth field of the odd field, but no high-luminance pixel of the same level exists in the corresponding portion of the even field, which causes line flicker.

On the other hand, when the above-mentioned processing according to the present invention is performed, the 4th H is the target scanning line, and the 5th H and the 4th H
When the difference (A-B) between the brightness values exceeds a predetermined value, that is, at a place where there is a risk of flickering, the difference between the brightness values
A half value of (AB) is added to the luminance value of the 4th H which is the target scanning line, as indicated by the broken line in (c) of the figure. After that, if the 6th H is the target scanning line and the difference (AB ') between the 5H and 6H luminance values exceeds a predetermined value, then the difference (AB') between the luminance values is halved. The value of 1 is added to the luminance value of the 6th H, which is the target scanning line, as indicated by the broken line in (c) of the figure.

As a result, the frame memory (6) shown in FIG.
Therefore, there is no large difference in luminance between the odd field and the even field read according to the interlace method, and line flicker is suppressed.

According to the present invention, in the non-interlaced video signal, the difference in the luminance is small as described above only when the pixels above and below a certain pixel have pixels brighter than a predetermined difference. When the signal value is changed so that there is no pixel brighter than a predetermined difference, the value of the video signal does not change, so that line flicker is effectively suppressed without causing blurring of the entire screen.

Further, since the value is changed in the direction of increasing the brightness, there is no problem that a character composed of a thin line becomes dark and a vertical line included in the character is conspicuous on the contrary.

Furthermore, since the processing is performed not by the video signals of the R, G, B components but by the video signals of the luminance / color components, the portion where humans flicker as line flicker, that is, the portion where the difference in luminance is large is accurately detected. In addition, it is possible to easily determine and perform the flicker suppressing process. However, the circuit is simplified by performing the line flicker suppression processing only on the change of the luminance component which is more sensitive to the human eye than the change of the color component and not performing the line flicker suppression processing on the color component. Planned.

The above description of the embodiments is for explaining the present invention, and should not be construed as limiting the invention described in the claims or reducing the scope. The configuration of each part of the present invention is not limited to the above embodiment, and it is needless to say that various modifications can be made within the technical scope described in the claims.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a video signal conversion circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a processing circuit for suppressing line flicker.

FIG. 3 is a waveform diagram illustrating an operation of the processing circuit.

[Explanation of symbols]

 (4) Processing circuit (14) Comparator (15) Subtraction circuit (16) Gate circuit (17) Coefficient circuit (18) Addition circuit

Front page continuation (72) Inventor Isao Tsukaune 2-18 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (2)

[Claims] 1. A video signal conversion circuit for converting a non-interlaced video signal into an interlaced video signal, a processing circuit for performing line flicker suppressing processing on the non-interlaced video signal, and a processing circuit The processing circuit stores a video signal, and a control means for reading out the video signal from the storage means in an order according to the interlace system and outputting the video signal in a predetermined format. 2 on both sides of the line (target scan line)
Selecting means for selecting a high-luminance video signal by comparing the video signals on the one scanning line with each other, and creating a difference signal by subtracting the video signal on the target scanning line from the video signal selected by the selecting means Subtracting means for comparing the difference signal output from the subtracting means with a predetermined value, and when the difference signal is larger, an adjusting means for outputting an adjustment value obtained by performing a predetermined function process on the difference signal. And a summing means for adding the adjustment value output from the adjusting means to the video signal on the target scanning line. 2. A video signal conversion circuit for converting a non-interlaced video signal into an interlaced video signal, and a processing circuit for performing line flicker suppression processing on a luminance component in the non-interlaced video signal; A delay circuit that performs a delay process for synchronizing a color component in an interlaced video signal with a luminance component output from the processing circuit, and a luminance component and a color component output from the processing circuit and the delay circuit are stored. The processing circuit includes a storage unit and a control unit that reads out the luminance component and the color component from the storage unit in the order according to the interlace method and outputs them as a video signal of a predetermined format. 2 on both sides of the scan line (target scan line)
The luminance component of the video signal on the target scanning line is selected from the luminance component selected by the selection unit that compares the luminance components in the video signals on the book scanning lines with each other, and the luminance component selected by the selection unit. A subtraction means for creating a subtracted difference signal, and an adjustment obtained by comparing the difference signal output from the subtraction means with a predetermined value and performing a predetermined function process on the difference signal when the difference signal is larger. A video signal conversion circuit comprising: an adjusting unit that outputs a value; and an adding unit that adds the adjustment value output from the adjusting unit to the luminance component of the video signal on the target scanning line.