JPH05114655A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to cut easily a fuse which constitutes a part of a redundancy circuit. CONSTITUTION:A fuse 16, which constitutes a redundancy circuit formed on a semiconductor chip 7, is formed on a surface protective film 9 and made of a material identical to a base metal B of a CCB bump 6. A cutting portion of the fuse 16 consists of one metal layer of the base metal BLM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effectively applied to a semiconductor integrated circuit device having a redundant circuit.

[0002]

2. Description of the Related Art Recently, in semiconductor integrated circuit devices,
The circuit function and the storage capacity are being increased.

However, it has become difficult to keep the manufacturing yield of semiconductor chips above a practical level as the circuit functions and storage capacities increase.

With the improvement of circuit functions and the increase of storage capacity,
This is because the elements, wirings, and the like become finer and the semiconductor chip becomes larger, so that the defect occurrence rate due to foreign matters and the like increases.

There is a redundant configuration technique as a technique for suppressing the decrease in the manufacturing yield of semiconductor chips due to the occurrence of this defect.

In the redundant configuration technology, a spare element that can replace a defective portion is provided in advance in the semiconductor chip, and when a defect occurs, the defective portion and the spare element are replaced to repair the semiconductor chip. Is.

Switching between the defective portion and the spare element is
This is done by cutting a fuse forming a part of the redundant circuit. The method of cutting the fuse includes, for example, a laser method and an electric fusing method.

The fuse is usually made of polysilicon, for example. In this case, the fuse is patterned at the same time when the gate electrode of the MOS • FET is patterned, for example, from the viewpoint of manufacturing ease. That is, the fuse in this case is formed in the lowermost layer of the semiconductor chip.

Therefore, when the fuse in this case is cut by a laser or the like, a predetermined region such as an insulating film or a wiring above the fuse is removed to expose a part of the fuse, and then the exposed portion is exposed. Cutting is performed by irradiating a laser beam.

A fuse forming a part of the redundant circuit is described in, for example, Japanese Patent Laid-Open No. 62-119938.

The fuse of this document is made of a refractory metal such as molybdenum (Mo), tungsten (W) or chromium (Cr).

In this prior art, when the fuse is cut, the insulating film that covers the fuse is perforated with an opening through which a part of the fuse is exposed, and then the processing atmosphere is exposed to the oxidizing atmosphere. The fuse to be irradiated is irradiated with a laser beam to sublimate the fuse material in the beam irradiation portion to cut the fuse.

That is, when the fuse is cut, by oxidizing the fuse and lowering its melting point, the fuse can be cut with a relatively low beam energy, and damage to elements and wiring around the fuse due to laser beam irradiation is prevented. It is suppressed.

[0014]

However, the present inventor has found that the above-mentioned conventional technique has the following problems.

That is, first of all, in any of the above-mentioned conventional techniques, when the fuse is blown, a predetermined region portion such as an insulating film or a wiring above the fuse must be removed, so that the fuse cutting process becomes complicated. There was a problem.

This problem becomes more serious as the number of wiring layers increases when the fuse is provided in a relatively lower layer of the semiconductor chip. This is because the insulating film above the fuse is thickened and the number of wiring layers is increased, which makes it difficult to remove them.

Further, in any of the above-mentioned conventional techniques, since the insulating film in the region where the fuse is cut is opened, impurity ions and the like enter through the opening, and the reliability of the semiconductor integrated circuit device is deteriorated. there were.

Further, in the case of the prior art in which the fuse is formed in the lowermost layer of the semiconductor chip described above, it is not possible to form the wiring or the like directly on the fuse, so that there is a problem that the layout rule of the wiring is restricted.

The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of facilitating the cutting process of a fuse forming a part of a redundant circuit.

Another object of the present invention is to provide a technique capable of suppressing a decrease in reliability of a semiconductor integrated circuit device due to a cutting process of a fuse forming a part of a redundant circuit.

Further, another object of the present invention is to provide a technique capable of relaxing the layout rule of the wirings constituting the semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will be apparent from the description of the specification and the accompanying drawings.

[0023]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the first invention is a semiconductor integrated circuit device structure in which a fuse forming a part of a redundant circuit formed on a semiconductor chip is made of a transition metal and is provided on a surface protection film of the semiconductor chip. It is what

A second invention is a semiconductor integrated circuit device structure in which a fuse protection film for protecting the fuse is formed on at least a cut region of the fuse on the main surface of the semiconductor chip.

A third invention is a method of manufacturing a semiconductor integrated circuit device having a redundant circuit on a semiconductor chip, wherein the redundant circuit is formed when an electrode conductor pattern is formed on an insulating film which is an upper layer of the semiconductor chip. A method of manufacturing a semiconductor integrated circuit device in which fuses forming a part of the above are simultaneously patterned.

A fourth aspect of the present invention is a method of manufacturing a semiconductor integrated circuit device in which at least a cut region of the fuse is irradiated with an energy beam in a predetermined reaction gas atmosphere to selectively perform CVD to form a fuse protective film. To do.

A fifth invention is a method of manufacturing a semiconductor integrated circuit device, wherein a fuse protection film for protecting the fuse is formed on at least a cut region of the fuse on the main surface of the semiconductor chip. A method for manufacturing a semiconductor integrated circuit device in which the fuse protection film is formed by cutting the fuse with a laser beam or a focus ion beam, and then irradiating the exposed region of the fuse with an energy beam to selectively perform CVD. ..

According to a sixth aspect of the present invention, when patterning a base metal for CCB bumps or a base metal for TAB on a surface protection film of a semiconductor substrate having a semiconductor chip, at least the base metal for CCB bumps or the base metal for TAB is formed. Simultaneously patterning a fuse, which is a part of a redundant circuit of a semiconductor chip, on the surface protection film by using some constituent materials, and depositing a fuse protection film on the semiconductor substrate on which the fuse is formed. A step of forming a photoresist pattern on the fuse protection film, exposing only the fuse protection film portion on the CCB bump base metal or the TAB bump base metal; and using the photoresist pattern as an etching mask, CCB
A step of removing only the fuse protection film portion on the bump base metal or the TAB bump base metal, and forming bumps for forming CCB bumps or TAB bumps on the semiconductor substrate using the photoresist pattern as a deposition mask. A method for manufacturing a semiconductor integrated circuit device, the method including the step of depositing a working metal.

[0030]

According to the first aspect of the invention described above, since the fuse is exposed from the beginning, the fuse can be cut without performing the conventional process of removing the insulating film or the wiring for covering the fuse. You can

Further, when the fuse is cut, since the opening is not formed in the insulating film covering the semiconductor chip, the problem of the prior art in which impurity ions and the like enter from the opening can be avoided.

Further, since the fuse is provided on the surface protection film, the wiring in the wiring layer below the surface protection film is not regulated as much as before by the presence or absence of the fuse, so that the wiring layout rule is relaxed as compared with the conventional case. can do.

According to the above-mentioned second invention, since the corrosion, oxidation and peeling of the fuse due to the impurity ions and water can be suppressed, the fuse resistance caused by the corrosion, oxidation and peeling of the fuse can be suppressed. It is possible to suppress the fluctuation of the value, and it is possible to suppress the malfunction of the redundant circuit due to the fluctuation of the fuse resistance value.

According to the above-described third invention, when the electrode conductor pattern is patterned, the fuse is simultaneously patterned, so that a new photomask for patterning the fuse is not required. Further, the number of manufacturing steps does not increase because the fuse is formed. That is, the fuse can be formed without increasing the number of photomasks and manufacturing steps.

According to the above-mentioned fourth invention, the fuse protection film can be formed without increasing the number of photomasks and without significantly increasing the number of manufacturing steps.

According to the fifth aspect, the exposed portion of the fuse exposed by the cutting process is covered with the fuse protective film again, so that impurity ions, moisture, etc. are prevented from entering from the exposed portion of the fuse. It becomes possible.

According to the above-described sixth invention, the photoresist pattern used as the etching mask when the fuse protection film portion on the base metal is removed by etching is used as the deposition mask at the time of forming bumps. It is possible to form the fuse protection film without increasing the number of manufacturing steps and without significantly increasing the number of manufacturing steps.

[0038]

1 is a sectional view of a fuse forming a part of a redundant circuit of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a partial sectional view of a semiconductor integrated circuit device having the fuse of FIG. 3 is an enlarged cross-sectional view of the CCB bump and the underlying metal, FIG. 4 is an overall enlarged plan view of the semiconductor chip having the fuse of FIG. 1, FIG. 5 is a circuit diagram showing the connection state of the fuse of FIG. 1, and FIG. 1 is an enlarged cross-sectional view of the fuse and the semiconductor substrate thereunder, FIG. 7 is an overall enlarged plan view of the fuse of FIG. 1, and FIGS. 8 to 12 are perspective views of main parts for explaining an example of the method of forming the fuse of FIG. FIG. 13 is a cross-sectional view of an essential part of a semiconductor substrate showing a fuse during a cutting process, FIG. 14 is a cross-sectional view of an essential part of a semiconductor substrate showing a fuse after a cutting process, FIG.
FIG. 15 is an overall plan view of the fuse after the cutting process of FIG. 14.

The semiconductor integrated circuit device of the first embodiment shown in FIG. 2 is, for example, a chip carrier 1a.

The package substrate 2 constituting the chip carrier 1a is made of a ceramic material such as mullite.

Electrodes 3a and 3b are formed on the upper and lower surfaces of the package substrate 2, respectively.

The electrodes 3a and 3b are electrically connected by an internal wiring 4 formed inside the package substrate 2 and made of, for example, tungsten.

The electrodes 3b on the lower surface of the package substrate 2 are
CCB (Controlled Collapse Bonding) bumps 5 are joined. The CCB bump 5 is made of, for example, a tin (Sn) / Ag alloy (melting point: about 250 to 260 ° C.) containing about 3.5 wt% silver (Ag).

In addition, the electrode 3a on the upper surface of the package substrate 2
A CCB bump 6 having a diameter smaller than that of the CCB bump 5 is bonded to. CCB bump 6 is, for example, 1 to 5% by weight.
Lead (Pb) / Sn alloy containing about Sn (melting point: 3
20 to 330 ° C.).

The CCB bump 6 is a base metal (base metal for CCB bump) B formed on the main surface side of the semiconductor chip 7.
It is joined to the LM. That is, the semiconductor chip 7 is
It is mounted on the electrode 3 a of the package substrate 2 via the CCB bump 6. In addition, BLM is Ball Limitting M
Abbreviation for etalization.

As shown in FIG. 3, the base metal BLM is formed by stacking, for example, three types of metal layers 8a to 8c in order from the lower layer.

The lowermost metal layer 8a is made of, for example, Cr and has a thickness of, for example, about 0.05 to 0.2 μm. The intermediate metal layer 8b is made of, for example, copper (Cu) and has a thickness of, for example, about 0.5 to 2.0 μm. Further, the uppermost metal layer 8c is, for example, gold (Au).
And has a thickness of, for example, about 0.1 to 0.2 μm.

The base metal BLM made of such metal layers 8a to 8c is electrically connected to the extraction electrode 11 through the through hole 10 formed in the surface protection film 9.

The surface protective film 9 is made of, for example, silicon dioxide (S
io ₂ ) or silicon nitride (Si ₃ N ₄ ) and SiO ₂
Which is a final insulating film of the insulating films formed on the semiconductor chip 7.

The extraction electrode 11 is made of, for example, aluminum (Al) or an Al alloy, and is electrically connected to a semiconductor integrated circuit, which will be described later, formed on the main surface of the semiconductor chip 7 (see FIG. 2).

The semiconductor chip 7 is hermetically sealed by a cap 12, as shown in FIG. Cap 12
Is made of, for example, aluminum nitride (AlN), and is joined to the upper surface of the package substrate 2 via the solder 13 for sealing. The solder 13 for sealing is, for example, about 10% by weight of S.
Pb / Sn alloy containing n (melting point: 290 to 300 ° C.
Degree).

The package substrate 2 and the cap 12 at the joint between the cap 12 and the package substrate 2 are connected.
In order to improve the wettability of the sealing solder 13, a bonding metal layer 14 made of, for example, Au / nickel (Ni) / titanium (Ti) is formed on each surface of the.

The back surface of the semiconductor chip 7 is joined to the bottom surface of the cap 12 via the heat transfer solder 15.
The heat transfer solder 15 is, for example, the same Pb as the sealing solder 13.
/ Sn alloy. In addition, on the lower surface of the cap 12,
In order to improve the wettability of the heat transfer solder 15, the above-mentioned joining metal layer 14 is formed.

Next, FIG. 4 shows an overall plan view of the main surface side of the semiconductor chip 7 of the first embodiment. A semiconductor integrated circuit such as an SRAM (Static RAM) circuit with logic is formed on the main surface of the semiconductor chip 7. The semiconductor integrated circuit is formed of, for example, BiC-MOS.

At the center of the main surface of the semiconductor chip 7, for example, a predetermined logic circuit block (not shown) forming a SRAM circuit with logic is arranged.

On both sides of the main surface of the semiconductor chip 7, for example, memory circuit blocks M having the same word / bit configuration.
Are arranged in multiple numbers.

In each of the memory circuit blocks M, for example, a plurality of memory cells composed of a predetermined number of MOS.FETs and a peripheral circuit of the memory are formed.

Then, in each memory circuit block M, for example, a spare memory cell (not shown) is formed. The spare memory cell is a spare memory cell that is replaced with the defective memory cell when a defective memory cell (not shown) occurs. That is, the semiconductor chip 7 of the first embodiment
A redundant circuit is formed in.

A fuse, which will be described later, for switching between the defective memory cell and the spare memory cell is formed in a region F in each memory circuit block M, for example.

The region F is formed, for example, on the peripheral circuit formation region of the memory and between the CCB bumps 6.
The CCB bump 6 may not be formed on the memory cell formation region.

The connection state of the fuse is shown in FIG. A fuse 16 is provided between the ground line GND and the power supply line V _EE.
And the resistor R ₁ are connected in series.

The ground line GND has, for example, 0V.
A voltage of about a certain degree is supplied to the power supply line V _EE , for example, −
A negative voltage of about 4V is supplied. Also, the resistance R ₁
Is, for example, about 200 KΩ. The resistance of the fuse 16 depends on the fuse material, but is about 10Ω, for example.

A resistor R ₂ and a diode D ₃ are connected to a terminal T between the fuse 16 and the resistor R ₁ . The resistors R ₁ and R ₂ are connected to the ground line GND through the diodes D ₁ and D ₂ , respectively.

The terminal T of the fuse 16 and the resistor R ₁ is
Through the resistor R ₂ , for example, an n-channel MOS FET
It is connected to a gate electrode 17 (hereinafter referred to as nMOS).

The purpose of the diodes D _{1 to} D ₃ and the resistor R ₂ is to
This is to prevent charges generated during laser cutting from reaching the gate portion of the MOS and causing gate breakdown. That is, when positive charges are generated, the positive charges escape to the ground line GND by the diodes D ₁ and D ₂ , and when negative charges are generated, the negative charges escape to the power supply line V _EE by the diode D _3. It has become. In addition, the electric charge that cannot escape escapes energy due to the resistance R _2.
The S gate is not destroyed.

The nMOS 17 is connected to the switching circuit section in the spare decoder circuit (not shown). The switching circuit section is a circuit section for replacing a defective memory cell with a spare memory cell by cutting the fuse 16.

In the first embodiment, when the fuse 16 is connected as shown in FIG. 5, the resistance R ₁ is sufficiently larger than the resistance of the fuse 16 in the gate electrode of the nMOS 17, so that the fuse 16 and the resistance are The voltage of the ground line GND (for example, about 0V) is supplied through R ₂ .
Therefore, the nMOS 17 is in the "ON" state, and the switching circuit section is in the non-operating state.

On the other hand, although not shown in FIG. 5, when the fuse 16 is blown, the voltage of the negative power supply line V _EE (for example, −4) is passed through the resistor R ₁ to the gate electrode of the nMOS 17.
(About V) is supplied, the nMOS 17 turns off.
In this state, the switching circuit section operates to replace the defective memory cell with the spare memory cell.

By the way, in the first embodiment, as will be described later, the fuse 16 is made of the constituent material of the base metal BLM described above. That is, the fuse 16 has excellent corrosion resistance.

Therefore, in the first embodiment, as shown in FIG. 1, the fuse 16 is formed in a state of being exposed on the upper surface of the surface protective film 9.

Therefore, in the first embodiment, when the fuse 16 is cut by a laser or the like, it is not necessary to form an opening in the surface protection film 9, so that the cutting process of the fuse 16 is facilitated. It is possible to prevent the phenomenon that impurity ions or the like enter from the opening.

An enlarged sectional view of the fuse 16 is shown in FIG.
The semiconductor substrate 18 shown in FIG. 6 is made of, for example, p-type silicon (Si) single crystal.

In the semiconductor substrate 18, for example, the buried layer 1
9 is formed. The buried layer 19 includes, for example, n-type impurities such as antimony (Sb) or arsenic (As).
Has been introduced.

As the upper layer of the buried layer 19, for example, a p-type S
An epitaxial layer 20 made of i single crystal is formed. The epitaxial layer 20 is formed with a lead diffusion layer 21 and resistance diffusion layers 22a and 22b.

For example, phosphorus (P) or As, which is an n-type impurity, is introduced into the extraction diffusion layer 21. Also,
Boron (B), which is a p-type impurity, is introduced into the resistance diffusion layers 22a and 22b.

The resistance values of the resistors R ₁ and R ₂ shown in FIG. 5 are set by the resistance value of the epitaxial layer 20 between the resistance diffusion layers 22a and 22b.

The diodes D _{1 to} D ₃ of FIG. 5 are formed by the epitaxial layer 20 and the n-type buried layer 19. That is, in this structure, the resistor and the diode are integrated.

Elements such as resistors and diodes are electrically isolated by the isolation groove 23 and the field insulating film 24.

On the semiconductor substrate 18, interlayer insulating films 25a to 25e made of, for example, SiO ₂ and the surface protection film 9 are sequentially deposited from the lower layer.

Of the interlayer insulating films 25a to 25e, for example, the interlayer insulating films 25a to 25c have their upper surfaces flattened.

This is also because by flattening the upper surface of the surface protective film 9 below the fuse 16, the disconnection failure of the fuse 16 due to the step of the underlying layer is suppressed and the reliability of the fuse 16 is ensured. ..

Between the interlayer insulating films 25a and 25b, first layer wirings 26a1 to 26a1 made of, for example, Al or Al alloy are formed.
6a4 is formed.

Among them, the first layer wirings 26a1 and 26a4
Is a through hole 27a formed in the interlayer insulating film 25a.
The lead diffusion layers 21, 2 through 1, 27a4, respectively.
It is electrically connected to 1.

The first layer wirings 26a2 and 26a3 are
Through holes 27a2 perforated in the interlayer insulating film 25a,
27a3 through resistance diffusion layers 22a and 22a, respectively.
It is electrically connected to b.

Between the interlayer insulating films 25b and 25c, second layer wirings 26b1 and 2b made of, for example, Al or Al alloy are formed.
6b2 is formed.

The second-layer wiring 26b1 is electrically connected to the first-layer wiring 26a1 through a through hole 27b1 formed in the interlayer insulating film 25b.

The second layer wiring 26b2 is electrically connected to the first layer wiring 26a3 through a through hole 27b2 formed in the interlayer insulating film 25b.

Between the interlayer insulating films 25c and 25d, third layer wirings 26c1 and 2c made of, for example, Al or Al alloy are formed.
6c2 is formed.

Among them, the third layer wiring 26c1 is electrically connected to the second layer wiring 26b1 through a through hole 27c1 formed in the interlayer insulating film 25c.

The third layer wiring 26c1 is formed, for example, in FIG.
It is electrically connected to the ground line GND shown in.

The third layer wiring 26c2 is electrically connected to the second layer wiring 26b2 through a through hole 27c2 formed in the interlayer insulating film 25c.

Between the interlayer insulating films 25d and 25e, fourth layer wirings 26d1 and 2 made of, for example, Al or Al alloy are formed.
6d2 is formed.

Among them, the fourth layer wiring 26d2 is electrically connected to the third layer wiring 26c2 through a through hole 27d1 formed in the interlayer insulating film 25d.

The fourth layer wiring 26d1 is formed, for example, in FIG.
It is electrically connected to the ground line GND shown in.

Fifth layer wirings 26e1 and 26e2 made of, for example, Al or Al alloy are formed on the interlayer insulating film 25e.

Among them, the fifth layer wiring 26e2 is electrically connected to the fourth layer wiring 26d2 through the through hole 27e1 formed in the interlayer insulating film 25e.

The fifth-layer wiring 26e1 has, for example, the structure shown in FIG.
It is electrically connected to the ground line GND shown in.

In the first embodiment, the third layer wiring 26c1, the fourth layer wiring 26d1 and the fifth layer wiring 26
A part of e1 also extends below the fuse 16.

This is due to the following two reasons, for example. First, by flattening the upper surface of the surface protective film 9 below the fuse 16, the fuse 16 caused by the step difference in the base is formed.
This is to suppress the disconnection failure of and to ensure the reliability of the fuse 16.

Second, when the fuse 16 is cut by a laser or the like, the third layer wiring 26c1 and the fourth layer wiring 26d1 are used.
And by making the fifth-layer wiring 26e1 have a function as a laser shield (energy beam shield),
This is to suppress damage to the elements, wirings, etc. below the fuse 16 due to irradiation with laser or the like.

The third layer wiring 26c1 and the fourth layer wiring 2
The reason why 6d1 and the fifth layer wiring 26e1 are integrated with the laser shield is that, for example, when the laser shield is isolated, carriers such as electric charges generated during laser irradiation are charged in the laser shield, This is to prevent the damage to the elements, wiring, etc., because of that.

The fuse 16 is formed on the surface protection film 9.
Are formed. By the way, if the cut portion 16a of the fuse 16 is composed of the three types of metal layers 8a to 8c of the base metal BLM shown in FIG. 3, the cutting process by a laser or the like becomes difficult.

Therefore, in the first embodiment, the cut portion 16a of the fuse 16 is composed of, for example, only the metal layer 8a. That is, the cut portion 16a is composed of only the Cr layer, for example.

Both ends of the metal layer 8a, that is, the fuse 1
Both ends of 6 are through holes 2 formed in the surface protective film 9.
The fifth layer wiring 26e is provided through 7f1 and 27f2, respectively.
It is electrically connected to 1, 26e 2.

However, the non-cutting portion 16b of the fuse 16
1, 16b2 are formed by sequentially stacking the metal layers 8a to 8c from the lower layer in FIG.

In the first embodiment, the non-cutting portion 16b2 is arranged so as to cover the stepped portion formed on the upper surface of the surface protective film 9 between the fifth layer wirings 26e1 and 26e2. This is because three layers of 8a-8
By arranging the non-cutting portion 16b2 composed of c,
This is for suppressing the disconnection failure of the fuse 16 due to the step of the base and ensuring the reliability of the fuse 16.

An overall enlarged plan view of the fuse 16 is shown in FIG. As shown in FIG. 7, a plurality of fuses 16 are arranged as needed.

The cut portion 16a of each fuse 16 is thinner than the other portions so as to be easily cut. In Example 1, the width W1 of the cut portion 16a is, for example, 15 μm.
It is below.

Further, the non-cutting portion 16b1 of the fuse 16
Are commonly connected to the respective cut points 16a, and a part thereof extends so as to surround a part of the outer periphery of the fuse 16 group. That is, the non-cut point 16b1
Has a function as a guard ring.

The reason why the non-cutting portion 16b1 has a function as a guard ring is as follows.

The first is to prevent a high voltage from being externally applied to the fuse 16 due to static electricity or the like, and to prevent a disconnection defect of the fuse 16.

Secondly, carriers such as electric charges generated when the fuse 16 is cut by a laser or the like are easily released, and other adverse effects are not caused.

The third reason is to suppress the entry of impurity ions and the like.

Further, in the first embodiment, the through hole 27f1 for connecting the non-cutting portion 16b1 and the fifth layer wiring 26e1 extends along the non-cutting portion 16b1.

The reason for extending the through hole 27f1 is that even if a crack or the like occurs in the surface protective film 9 due to a difference in thermal expansion coefficient between the fuse 16 and the surface protective film 9, it is necessary to prevent the crack from spreading. This is because it is blocked by the hole 27f1.

The other non-cutting portion 16b2 of the fuse 16 is arranged separately.

Next, an example of a method of manufacturing the semiconductor integrated circuit device of the first embodiment will be described with reference to FIGS.

Here, after the method of forming the fuse 16 is described, the method of cutting the fuse 16 will be described, and further the steps up to packaging of the semiconductor chip 7 will be described.

From the step of forming the fuse 16 to the step of cutting, the semiconductor chip 7 is cut into a semiconductor wafer (not shown).
This is a step to be performed before the separation from the.

First, as shown in FIG. 8, the through hole 10 and the through holes 27f1 and 27f are formed in the surface protective film 9.
2 (see FIG. 6) are simultaneously perforated by a photolithography technique, and then metal layers 8a to 8c are sequentially deposited on the surface protective film 9 from the lower layer by, for example, a sputtering method.

Subsequently, a photoresist (hereinafter simply referred to as resist) film is deposited on the metal layer 8c and patterned by photolithography technique to form resist patterns 28a and 28b.

The resist pattern 28a is a pattern for patterning the fuse 16 (see FIG. 7) described above.

The pattern portion 28a1 of the resist pattern 28a is a portion for forming the cut portion 16a (see FIG. 7) of the fuse 16, and the pattern portion 28a2.
Is a portion for forming the non-cut portion 16b2 (see FIG. 7) of the fuse 16.

In the first embodiment, when forming the resist pattern 28a, the width W2 of the pattern portion 28a1 is set.
Is set to be equal to or less than the side etching amount in the wet etching step for patterning the metal layers 8b and 8c.

The resist pattern 28b is the above-mentioned CC.
It is a pattern for forming a base metal BLM (see FIG. 3) for the B bumps 6.

Next, the metal layers 8b and 8c are patterned by, for example, a wet etching method. At this time, since the wet etching proceeds isotropically, as shown in FIG. 9, portions of the metal layers 8b and 8c below the outer periphery of the resist patterns 28a and 28b are also removed by etching.

By the way, in the first embodiment, since the width W2 of the pattern portion 28a1 is set to be equal to or less than the side etching amount in this wet etching step, the metal layer 8
When the pattern formation of b and 8c is completed, the pattern portion 2
Below 8a1, only the metal layer 8a remains, as shown in FIG.

Since the metal layers 8b and 8c remain below the pattern portion 28a2, the resist pattern 28a is formed.
Remains as is. That is, the pattern portion 28a1 is
It remains as it is while being supported by the pattern portion 28a2.

Then, as shown in FIG. 11, the metal layer 8a is patterned by a dry etching method using the resist patterns 28a and 28b as an etching mask, and then the resist patterns 28a and 28b are removed.
As shown in FIG. 12, the fuse 16 and the base metal BL
M is formed at the same time.

As described above, in the first embodiment, since the fuse 16 and the base metal BLM are patterned at the same time, it is not necessary to manufacture a new photomask for forming the fuse 16, and the fuse 16 is formed. No additional manufacturing steps are added to form.

After that, the CCB bumps 6 are formed on the base metal BLM by, for example, the lift-off method or the metal mask vapor deposition method.

Then, after performing a probe test on each semiconductor chip 7 on the semiconductor wafer, based on the result of the test, as shown in FIG. 13, for example, a laser beam is applied to a predetermined cut point 16a of the fuse 16. The (energy beam) LB ₁ is irradiated, and the fuse 16 is cut as shown in FIGS. 14 and 15.

In the first embodiment, since the cut portion 16a of the fuse 16 is composed of only one metal layer 8a (see FIG. 6) as described above, the fuse 16 is cut with relatively low energy. It is possible.

In the first embodiment, the fuse cutting process with the laser beam LB ₁ is performed in the oxidizing atmosphere. This is to facilitate the fuse cutting process by oxidizing the fuse 16 to facilitate sublimation.

After that, the probe test is conducted again, fail marks are put on the semiconductor chips 7 that have not passed the test, and then the semiconductor chips 7 are separated from the semiconductor wafer. Then, only the non-defective ones of the separated semiconductor chips 7 are
After mounting on the package substrate 2 shown in FIG. 2, the cap 12 is hermetically sealed to manufacture the chip carrier 1a.

As described above, according to the first embodiment, the following effects can be obtained.

(1) Since the fuse 16 is provided on the surface protection film 9, the step of removing the insulating film or the wiring for covering the fuse, which is required in the conventional case, is not required when the fuse 16 is cut. Thus, the cutting process of the fuse 16 can be made easier than ever before.

(2) When the fuse 16 is cut, the surface protection film 9 covering the semiconductor chip 7 need not be perforated with an opening, so that the problem of the prior art that impurity ions or the like enter through the opening is avoided. It becomes possible to do.

(3) Since the cut portion 16a of the fuse 16 is composed of only the metal layer 8a, the fuse 16 can be cut with relatively low energy when the fuse 16 is cut by a laser or the like. For this reason, it is possible to suppress damage to the elements and wirings below the fuse 16 due to laser irradiation and the like.

(4). Below the fuse 16, the third layer wiring 2 is formed.
6c1, fourth layer wiring 26d1 and fifth layer wiring 26e1
A part of the fuse 16 is extended, and the extended portion is provided with a function as a laser shield, so that the element, wiring, etc. below the fuse 16 caused by the cutting process of the fuse 16 by the laser beam LB ₁ or the like. It is possible to suppress damage.

(5). Third layer wiring 26c1, fourth layer wiring 26
By integrating d1 and the fifth layer wiring 26e1 and the laser shield, carriers such as electric charges generated during laser irradiation are transferred to the third layer wiring 26c1 and the fourth layer wiring 26d.
Since it can escape through the first and fifth layer wirings 26e1, it is possible to suppress damages to the elements and wirings due to the carriers.

(6). The third layer wiring 26 is provided below the fuse 16.
C1 and the fourth layer wiring 26d1 and a part of the fifth layer wiring 26e1 are extended, and the upper surface of the surface protective film 9 below the fuse 16 is made flat, thereby suppressing the disconnection failure of the fuse 16 caused by the step difference in the ground. Can fuse 16
It is possible to secure the reliability of.

(7). A part of the non-cutting portion 16b1 of the fuse 16 is extended to a part of the outer periphery of the fuse 16 group, and the extended portion has a function as a guard ring. It is possible to suppress the disconnection defect of the fuse 16 due to the above. Further, carriers such as electric charges generated during the cutting process of the fuse 16 are not cut at the non-cutting point 16b1.
It is possible to escape via. Furthermore, it becomes possible to suppress the intrusion of impurity ions and the like.

(8). By extending the through hole 27f1 along a part of the outer periphery of the fuse 16 group, the surface protection film is caused by the difference in thermal expansion coefficient between the fuse 16 and the surface protection film 9. Even if a crack occurs in 9, it is possible to suppress the spread of the crack.

(9). From the above (2) to (8), the fuse 16
It is possible to secure the reliability and yield of the semiconductor chip 7 having

(10). When the underlying metal BLM is patterned, the fuse 16 is simultaneously patterned, so that it is not necessary to manufacture a new photomask for patterning the fuse 16. Further, no manufacturing process is added to form the fuse 16. That is, the fuse 16 can be formed without increasing the photomask and the manufacturing process.

[0147]

Second Embodiment FIG. 16 is a sectional view of a semiconductor integrated circuit device which is another embodiment of the present invention, and FIG. 17 is a TAB bump and a T.
FIG. 18 is a cross-sectional view of a base metal for AB, FIG. 18 is a cross-sectional view of a fuse forming a part of a redundant circuit of the semiconductor integrated circuit device shown in FIG. 16, and FIG. 19 is an enlarged cross-sectional view of the fuse of FIG.
0 is a plan view of the fuse shown in FIG. 18, FIG. 21 is a cross-sectional view of an essential part of the semiconductor substrate showing the fuse during the cutting process, and FIG.
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate showing a fuse after cutting processing.

The semiconductor integrated circuit device of the second embodiment shown in FIG. 16 is, for example, a QFP (Quad Flat Package) 1b.

The semiconductor chip 7 mounted on the die pad 29 is sealed by a package body 30 made of, for example, an epoxy resin.

The semiconductor chip 7 is TAB (Tape
It is electrically connected to a lead 33 through a bump 31 for automated bonding and a TAB lead 32.

The bump 31 for TAB is, for example, A
The TAB lead 32 is made of, for example, Cu, and the lead 33 is made of, for example, 42 alloy.

As shown in FIG. 17, the TAB bump 31 is electrically connected to the extraction electrode 11 through a base metal (TAB base metal) IF.

The base metal IF is, for example, three kinds of metal layers 8
a to 8c are laminated in order from the lower layer.

However, in the second embodiment, the metal layer 8a is
Is made of, for example, Ti. The metal layer 8b is made of Ni. Further, the metal layer 8c is made of Au, for example.

By the way, also in the second embodiment, as shown in FIG.
As shown in, the fuse 16 is formed on the surface protective film 9 and is made of the constituent material of the underlying metal IF.

Therefore, also in the second embodiment, as in the first embodiment, it is not necessary to form an opening in the surface protective film 9 when the fuse 16 is cut, so that the fuse 16 can be cut easily. Moreover, it is possible to prevent a phenomenon in which impurity ions or the like enter from the opening.

However, also in the second embodiment, as shown in FIG. 19, the cut portion 16a of the fuse 16 is composed of only the metal layer 8a forming the underlying metal IF (see FIG. 17), for example.

Therefore, also in the second embodiment, as in the first embodiment, when the fuse 16 is cut by the laser beam or the like, the fuse 1 is relatively low in energy.
It is possible to cut 6.

Further, the non-cutting portion 16b1 of the fuse 16
, 16b2 are metal layers 8a to 8b constituting the underlying metal IF.
8c.

In the second embodiment, the non-cutting portion 16b
1, 16b2 are arranged so as to overlap the underlying step of the surface protective film 9. The cut portion 16a is formed on a relatively flat surface of the surface protective film 9. this is,
Suppressing disconnection failure of the fuse 16 due to the step difference in the base,
This is to ensure the reliability of the fuse 16.

In the second embodiment, the fuse 1
The laser shield is not provided below 6. That is, it is possible to arrange a predetermined wiring below the fuse 16. Therefore, it is possible to relax the wiring layout rule.

FIG. 20 shows an overall plan view of the fuse 16 of the second embodiment. In the second embodiment, the non-cutting portions 16b1 of the fuse 16 are, for example, individually separated.

Such a fuse 16 is the same as in the first embodiment.
Similarly to, the base metal IF is patterned at the same time. Therefore, like the first embodiment, the fuse 16 can be formed without increasing the photomask and the number of manufacturing steps.

When the fuse 16 is cut,
Similar to the first embodiment, first, based on the result of the probe inspection performed on the semiconductor chip 7, as shown in FIG. 21, the laser beam LB ₁ is irradiated to the cut portion 16a of the predetermined fuse 16, The fuse 16 is blown, as shown at 22.

As described above, according to the second embodiment, the following effects can be obtained in addition to the effects (1) to (3) and (10) obtained in the first embodiment.

That is, since the laser shield is not provided below the fuse 16, a predetermined wiring can be arranged below the fuse 16, so that the wiring layout rule can be relaxed as compared with the conventional case.

[0167]

[Embodiment 3] FIG. 23 is an overall enlarged plan view of a fuse forming a part of a redundant circuit of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 24 is a sectional view of the fuse shown in FIG. is there.

In the third embodiment, FIG. 23 and FIG.
As shown in FIG.
A guard ring 34 formed separately from the fuse 16
It is arranged so as to completely surround the group. As a result, the effect of the guard ring can be improved as compared with the case of the first embodiment.

As shown in FIG. 24, the guard ring 34 is formed by stacking metal layers 8a to 8c constituting the fuse 16 in order from the lower layer.

Therefore, in the third embodiment, the guard ring 34 also includes the fuse 16 and the base metal BLM.
(Or underlying metal IF) and patterned at the same time.

However, the cut portion 16a of the fuse 16 is
Is composed of only the metal layer 8a as in the first and second embodiments.

As shown in FIGS. 23 and 24, the guard ring 34 has a plane annular fifth layer wiring 26e through a through hole 27f3 formed in the surface protection film 9.
Electrically connected to 3.

The through hole 27f3 is used for the guard ring 3
4 extends so as to completely surround the fuse 16 group. Accordingly, even if a crack occurs in the surface protective film 9 due to a difference in thermal expansion coefficient between the fuse 16 and the surface protective film 9, it is possible to prevent the crack from spreading.

Below the fuse 16, the laser shield 35 is provided separately from the fifth layer wiring 26e1. As a result, similarly to the first embodiment, it is possible to suppress damage to the elements and wirings below the fuse 16 due to the cutting process of the fuse 16 by the laser or the like.

Further, the laser shield 35 flattens the upper surface of the surface protective film 9 below the cut portion 16a of the fuse 16. As a result, the reliability of the fuse 16 can be secured as in the first embodiment.

As described above, according to the third embodiment, the following effects can be obtained in addition to the effects (1) to (3) and (10) obtained in the first embodiment.

(1). Since the laser shield 35 is provided below the fuse 16, the fuse 16 formed by a laser or the like is provided.
It is possible to suppress damage to the elements, wirings and the like below the fuse 16 due to the cutting process.

(2). By providing the laser shield 35 below the fuse 16 and flattening the upper surface of the surface protective film 9 below the fuse 16, the fuse 1 caused by the step difference in the base is formed.
The disconnection defect of 6 can be suppressed, and the reliability of the fuse 16 can be ensured.

(3) By arranging the guard ring 34 so as to completely surround the fuse 16 group, the effect of the guard ring can be improved as compared with the case of the first embodiment.

(4). By extending the through hole 27f3 so as to completely surround the fuse group 16, the surface protection film 9 is caused by a difference in thermal expansion coefficient between the fuse 16 and the surface protection film 9. Even if a crack occurs, it is possible to prevent the crack from spreading.

[0181]

[Fourth Embodiment] FIG. 25 is an overall enlarged plan view of a fuse constituting a part of a redundant circuit of a semiconductor integrated circuit device according to another embodiment of the present invention. FIG. 26 is a cross-sectional view of the main part of the fuse shown in FIG. It is a figure.

In the fourth embodiment, FIG. 25 and FIG.
As shown in FIG. 6, the uncut portion 16b1 of the fuse 16
Is extended so as to completely surround the fuses 16 group,
Also serves as a guard ring.

In the fourth embodiment, the non-cutting portion 16b
Since 1 also serves as a guard ring, the area of the region where the fuse 16 is arranged can be reduced as compared with the third embodiment. In addition, in the case of the fourth embodiment, the fuse 16 is larger than that in the case of the third embodiment without causing a large area increase.
It is possible to increase the number of.

The non-cutting portion 16b1 is, as shown in FIGS. 25 and 26, through the through hole 27f4 perforated in the surface protective film 9 and the plane annular fifth layer wiring 26.
It is electrically connected to e4.

The through hole 27f4 is formed in the non-cutting portion 16
The fuses 16 are extended along b1 so as to completely surround the fuses. As a result, like the third embodiment, even if a crack occurs in the surface protective film 9 due to a difference in thermal expansion coefficient between the fuse 16 and the surface protective film 9, it is possible to prevent the crack from spreading. Is possible.

Similar to the first embodiment, a part of the fifth-layer wiring 26e4 extends below the fuse 16 and has the function of a laser shield.

As a result, similarly to the first embodiment, it is possible to suppress damage to the elements and wirings below the fuse 16 due to the cutting process of the fuse 16 by the laser beam or the like.

Further, similar to the first embodiment, the fifth layer wiring 2
Since the upper surface of the surface protection film 9 below the cut portion 16a of the fuse 16 is made flat by the extended portion of 6e4, the disconnection defect of the fuse 16 is suppressed, and the reliability of the fuse 16 is ensured. Is possible.

As described above, according to the fourth embodiment, the following effects can be obtained in addition to the effects (1) to (6), (9) and (10) obtained in the first embodiment. It will be possible.

(1) By arranging the non-cutting portion 16b1 so as to completely surround the fuse group 16, the effect of the guard ring can be improved as compared with the case of the first embodiment.

(2). By extending the through hole 27f4 so as to completely surround the fuse group 16, the surface protection film 9 is caused by the difference in thermal expansion coefficient between the fuse 16 and the surface protection film 9. Even if a crack occurs, it is possible to prevent the crack from spreading.

(3). Since the non-cutting portion 16b1 also serves as a guard ring, the area of the region of the fuse 16 is the same as in the third embodiment.
It is possible to reduce the size. Moreover, the number of fuses 16 can be increased as compared with the case of the third embodiment without causing a large increase in area.

[0193]

[Embodiment 5] FIG. 27 is a sectional view showing the principal part of a semiconductor integrated circuit device according to an embodiment of the present invention. FIGS. 28 to 31 are explanatory views of an example of a method for manufacturing the semiconductor integrated circuit device of FIG. 27. Figure 3
4 is an explanatory diagram of an example of a method of cutting the fuse of the semiconductor integrated circuit device of FIG.

In the fifth embodiment, as shown in FIG. 27, the fuse 16 is covered and protected by the fuse protection film 36 deposited on the surface protection film 9. As a result, in the fifth embodiment, it is possible to suppress corrosion, oxidation, peeling, etc. of the fuse 16 due to impurity ions, water, and the like.

The fuse protection film 36 is made of, for example, SiO ₂ , and the semiconductor chip 7 except for the upper surface of the base metal BLM.
Is deposited almost all over the main surface of. The thickness of the fuse protection film 36 varies depending on, for example, the material of the fuse protection film 36 and the heat treatment condition after the formation of the fuse protection film 36, and therefore cannot be generally stated, but is set in the range of, for example, about 50 nm to 500 nm.

This is because if the fuse protection film 36 is too thin, impurity ions, water, etc. may permeate, and if it is too thick, the fuse protection film 36 will crack when the fuse 16 is cut and the fuse protection film 36 will not be cut. This is because it is considered that another fuse 16 adjacent to the fuse 16 may be adversely affected.

Next, an example of a method of manufacturing the semiconductor integrated circuit device of the fifth embodiment will be described with reference to FIGS.

First, as shown in FIG. 28, a fuse protection film 36 is deposited on the surface protection film 9 by the CVD method or the like so as to cover the fuse 16 and the underlying metal BLM, and then a resist film is formed on the fuse protection film 36. 28 is applied. Note that this stage is a stage before the semiconductor chip 7 is cut out from a semiconductor wafer (not shown).

Subsequently, the resist film 28 is patterned by the photolithography technique, and as shown in FIG. 29, a resist pattern such that only the fuse protection film 36 portion on the upper surface of the base metal BLM is exposed on the surface protection film 9. 28c is formed.

Then, using the resist pattern 28c as an etching mask, the portion of the fuse protection film 36 on the upper surface of the base metal BLM is removed by etching. As a result, as shown in FIG. 30, the upper surface of the base metal BLM is exposed.

Finally, the resist pattern 28c is formed as shown in FIG.
After removal as shown in FIG.
The CCB bump 6 shown in is formed.

Next, an example of a method for cutting the fuse 16 of the semiconductor integrated circuit device of the fifth embodiment will be described with reference to FIGS.

First, in the vacuum processing chamber, as shown in FIG. 32, a predetermined portion of the fuse protection film 36 is irradiated with, for example, a focused ion beam FIB to remove the fuse protection film 36 portion. Then, by this, the fuse 1
Part 6 is exposed. This process may be performed before or after cutting the semiconductor chip 7 from a semiconductor wafer (not shown).

Then, continuously without breaking the vacuum, as shown in FIG.
As shown in FIG. 3, the cut portion 16a of the fuse 16 is irradiated with the focused ion beam FIB to cut the fuse 16.

This fuse 16 has a focused ion beam F
The cutting is not limited to the cutting by the IB, but can be variously changed, and may be cut by the laser beam, for example. When cutting with a laser beam, the beam passes through the fuse protection film and is absorbed by the fuse, and the fuse is vaporized and cut by heat.

However, in the case of using the focused ion beam FIB, as compared with the case of using the laser beam, the following first
~ The third effect is obtained.

First, in the case of a laser beam, the fuse protection film 36 is destroyed by the impact when the fuse 16 is vaporized and expanded, so that the fuse protection film 36 is easily cracked by the impact, but the focused ion is focused. Beam F
In the case of IB, since the fuse protection film 36 is removed by etching with ions, cracks or the like are unlikely to occur in the fuse protection film 36.

Secondly, in the case of the laser beam, the beam may pass through the transparent film and damage elements and wirings below the fuse 16, but in the case of the focused ion beam FIB, There is no such worry.

Thirdly, in the case of a laser beam, since the fuse protection film 36 is destroyed by the impact of the vaporization and expansion of the fuse 16, the fragments of the fuse protection film 36 may be foreign matters, but the focused ion beam In the case of FIB, there is no such concern.

After the fuse 16 is cut in this way, in the fifth embodiment, as shown in FIG. 34, in the exposed portion of the fuse 16 exposed by the fuse cutting process in a predetermined reaction gas atmosphere, for example, Selective CVD by irradiating laser beam (energy beam) LB _2.
Then, the fuse protection film 36a covering the exposed portion is formed. The fuse protection film 36a is also made of SiO ₂ , for example. This makes it possible to prevent impurity ions, moisture, etc. from entering from the exposed portion of the fuse 16. When forming the fuse protection film 36a, the reaction gas may be supplied only to the film formation region by a gas nozzle or the like.

However, the energy beam used for forming the fuse protection film 36a is not limited to the laser beam LB ₂ and can be variously changed. For example, a focused ion beam or an electron beam may be used. Further, the fuse protection film 36a may be patterned by, for example, a normal photolithography technique.

As described above, in the fifth embodiment, the following effects can be obtained.

(1). By covering the fuse 16 formed on the surface protection film 9 of the semiconductor chip 7 with the fuse protection film 36, corrosion, oxidation and peeling of the fuse 16 caused by impurity ions, water, etc. Since it is possible to suppress the fluctuation of the fuse resistance value due to corrosion, oxidation, peeling, etc. of the fuse 16,
It is possible to suppress the malfunction of the redundant circuit due to the fluctuation of the fuse resistance value.

(2). Focusing the fuse 16 on the ion beam FI
By cutting with B, it is possible to suppress the occurrence of cracks or the like in the fuse protection film 36 during the fuse cutting process. In addition, it is possible to reduce the damage given to the elements and wirings below the fuse 16 during the fuse cutting process. Further, it is possible to reduce foreign substances and the like generated during the fuse cutting process.

(3) By covering the exposed portion of the fuse 16 exposed by the fuse cutting process with the fuse protective film 36a again, it is possible to prevent impurity ions, moisture, etc. from entering through the exposed portion of the fuse 16. Therefore, the fuse 16 can be prevented from corrosion, oxidation, peeling, and the like.

(4). Due to the above (1) to (3), the yield and reliability of the semiconductor integrated circuit device can be improved.

[0217]

Sixth Embodiment FIGS. 35 and 36 are explanatory views of an example of a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

In the sixth embodiment, the structure of the semiconductor integrated circuit device is the same as that of the fifth embodiment shown in FIG. 27, but the manufacturing method is different. Hereinafter, an example of a method for manufacturing the semiconductor integrated circuit device according to the sixth embodiment will be described with reference to FIGS.

First, as in the fifth embodiment, as shown in FIG.
As shown in FIG.
After forming a resist pattern 28c exposing only the fuse protection film 36 portion on the upper surface of the above, the fuse protection film 36 portion on the base metal BLM is removed by etching using the resist pattern 28c as an etching mask. In addition,
This step is a step before cutting the semiconductor chip 7 (see FIG. 27) from a semiconductor wafer (not shown), as in the case of the fifth embodiment.

Subsequently, in the sixth embodiment, as shown in FIG. 36, a Pb / Sn alloy for forming, for example, CCB bumps 6 (see FIG. 27) on a semiconductor wafer while leaving the resist pattern 28c. A solder (metal for bump formation) 37 made of, for example, is deposited by a vapor deposition method or the like.

That is, in the sixth embodiment, the resist pattern 28c used as the etching mask when the fuse protection film 36 is formed is used as it is as the deposition mask for forming the CCB bumps. Therefore, it is not necessary to manufacture a new photomask.

Next, by removing the resist pattern 28c, the solder 37 on the resist pattern 28c is removed, and the solder 37 is left only on the base metal BLM. Then, after that, heat treatment is applied to the solder 3 on the base metal BLM.
7 is heated and melted to form a hemispherical CCB bump 6 (see FIG. 27) by surface tension.

As described above, in the sixth embodiment, the following effects can be obtained in addition to the effects obtained in the fifth embodiment.

That is, the resist pattern 28c used as an etching mask when the fuse protection film 36 is formed.
Is used as a deposition mask for the solder 37 for forming CCB bumps, without increasing the number of photomasks and without significantly increasing the number of manufacturing steps.
It is possible to manufacture a semiconductor integrated circuit device having the fuse protection film 36. Therefore, it is possible to manufacture a highly reliable semiconductor integrated circuit device without significantly increasing the manufacturing cost or manufacturing time of the semiconductor integrated circuit device.

[0225]

[Embodiment 7] FIG. 37 is a fragmentary sectional view of a semiconductor integrated circuit device according to another embodiment of the present invention, FIG. 38 is a fragmentary plan view of the semiconductor integrated circuit device of FIG. 37, and FIG. 39 is a semiconductor of FIG. It is explanatory drawing of the manufacturing method example of an integrated circuit device.

In the seventh embodiment, as shown in FIGS. 37 and 38, the fuse protection film 36 is formed only in the cut region of the fuse 16.

The cut area of the fuse 16 is the fuse 16
Is a region between the metal layers 8c and 8c of the non-cutting portions 16b ₁ and 16b ₂ and is a region that covers the surface of the metal layer 16a between the non-cutting portions 16b ₁ and 16b ₁ .

However, the fuse protection film 36 is formed so as to slightly overlap the non-cutting portions 16b ₁ and 16b ₂ of the fuse 16.

This is the non-cutting portion 16b of the fuse 16.
₁ , 16b ₂ are the uppermost metal layer 8 made of Au or the like.
Since the fuse protection function is provided by c, if the fuse protection film 36 is slightly applied to the metal layers 8c and 8c of the non-cut portions 16b ₁ and 16b ₂ , the desired protection of the fuse 16 can be achieved. Because you can.

Then, in the seventh embodiment, as shown in FIG. 38, the fuse protection film 36 is used for each fuse 1.
6 are arranged so as to be separated from each other.

As a result, for example, when the predetermined fuse 16 is cut, the fuse protection film 3 covering the fuse 16 is formed.
Even if a crack occurs in the fuse 6, there is no concern that the crack will spread to the fuse protection film 36 covering the other fuses 16 adjacent thereto.

To form such a fuse protection film 36, for example, in a predetermined reaction gas atmosphere, as shown in FIG.
As shown in FIG. 6, only the cut region of the fuse 16 may be irradiated with the laser beam LB ₂ or the like to selectively perform CVD to form the fuse. When forming the fuse protection film 36 of the seventh embodiment, the reactive gas may be supplied only to the film formation region, as in the fifth embodiment.

However, the energy beam used for forming the fuse protection film 36 is not limited to the laser beam LB ₂ and can be variously changed. For example, a focused ion beam or an electron beam may be used. Further, the fuse protection film 36 may be patterned by, for example, a normal photolithography technique.

As described above, in the seventh embodiment, in addition to the effects obtained in the fifth embodiment, the following effects can be obtained.

(1) By arranging the fuse protection film 36 for each fuse 16 so as to be separated from each other, for example, when the fuse 16 is cut, the fuse protection film 36 covering the fuse 16 is cracked. Also,
Since there is no concern that the crack will spread to the fuse protection film 36 that covers the other fuse 16, it is possible to prevent the reliability of the other fuse 16 from being lowered due to the crack. Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved.

(2). By selectively forming the fuse protection film 36 by the laser CVD method, the fuse protection film 36 can be formed without increasing the number of photomasks and significantly increasing the number of manufacturing steps. Can be formed. Therefore, it is possible to manufacture a highly reliable semiconductor integrated circuit device without significantly increasing the manufacturing cost or manufacturing time of the semiconductor integrated circuit device.

[0237]

[Embodiment 8] FIG. 40 is a sectional view showing the principal part of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIGS.
FIG. 8 is an explanatory diagram of an example of a method for manufacturing the semiconductor integrated circuit device 0.

In the eighth embodiment, as shown in FIG. 40, fuse protection is provided, for example, between the opposing surfaces of the package substrate 2 and the semiconductor chip 7 in the package consisting of the package substrate 2 of the chip carrier 1a and the cap 12. The membrane 36b is filled.

The fuse protection film 36b is made of, for example, polyparaxylene or polyimide. As a result, as in the case of the fifth embodiment, it is possible to suppress corrosion, oxidation, peeling and the like of the fuse 16 due to impurity ions, water and the like.

However, the fuse protection film 36b does not necessarily have to be filled in the package or between the opposing surfaces of the package substrate 2 and the semiconductor chip 7, and is injected into the package to at least cover the fuse 16. Just go.

To manufacture such a chip carrier 1a, for example, the following is performed. First, as shown in FIG. 41, the semiconductor chip 7 is mounted on the package substrate 2 via the CCB bumps 6.

Subsequently, as shown in FIG. 42, the fuse protection film 3 made of, for example, polyparaxylene or polyimide is provided between the opposing surfaces of the semiconductor chip 7 and the package substrate 2.
Fill 6b.

After that, the joining metal layer 14 of the package substrate 2 and the joining metal layer 14 of the leg portion of the cap 12 (see FIG. 40) are joined by soldering, and at the same time, the back surface of the semiconductor chip 7 and the inner wall surface of the cap 12 are joined. 1 is manufactured by soldering to the metal layer 14 for joining described above to manufacture the chip carrier 1a shown in FIG.

As described above, in the eighth embodiment, for example, by filling the fuse protection film 36b between the opposing surfaces of the package substrate 2 and the semiconductor chip 7, corrosion of the fuse 16 caused by impurity ions, moisture, etc. Since the oxidation and peeling can be suppressed, the fluctuation of the fuse resistance value due to the corrosion, the oxidation and the peeling of the fuse 16 can be suppressed, and the malfunction of the redundant circuit due to the fluctuation of the fuse resistance value can be suppressed. It becomes possible to do. Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved.

Although the invention made by the present inventor has been concretely described based on the embodiments, the present invention is not limited to the above-mentioned embodiments 1 to 8 and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, in the first embodiment described above, the case where the base metal for the CCB bump is made of Cr / Cu / Au has been described. The base metal is a metal layer for the purpose of adhesion to the base and a metal. It suffices to have a structure in which a metal layer for the purpose of preventing the diffusion of atoms constituting the layer and a metal layer for the purpose of preventing surface oxidation etc. are laminated, for example, T
i / Ni / Au laminated film or Ti / Platinum (Pt)
You may comprise by the laminated film of / Au.

In the first embodiment, the case where the laser shield and the wiring below the fuse are integrated has been described, but the present invention is not limited to this, and is shown in, for example, FIGS. 43 and 44. So that the laser shield 35
And the fifth-layer wiring 26e1 may be separated from each other.

Further, in the first embodiment, the case where a part of the non-cut portion of the fuse is extended so as to surround a part of the fuse group has been described. However, the present invention is not limited to this and, for example, As shown in FIGS. 45 and 46, it is possible to connect one of the non-cut portions 16b1 in common and extend the through hole 27f1.

Further, as shown in FIGS. 47 and 48,
The uncut portion 16b1 of the fuse 16 may extend along the outer periphery of the fuse 16 group so as to completely surround the fuse 16 group. In this case, the effect of the guard ring can be improved more than in the case of the first embodiment.

In the first embodiment, the third to fifth parts are used.
Although part of the layer wiring is used as the laser shield, only part of the fourth and fifth layer wiring or part of the fifth layer wiring may be used as the laser shield. In this case, the wiring layer below the laser shield can be used freely as a wiring channel.

In the second embodiment, for example, T
The case where the base metal for the AB bump is made of Ni / Au has been described. The base metal is a metal layer for the purpose of adhesion to the base and a metal for the purpose of preventing diffusion of atoms forming the metal layer. It suffices to have a structure in which a layer and a metal layer for the purpose of preventing surface oxidation etc. are laminated.
It may be formed of a laminated film of / Cu / Au or a laminated film of Ti / Pt / Au.

In the second embodiment, the case where the laser shield is not provided has been described, but the present invention is not limited to this. For example, as shown in FIG. 49 and FIG. The laser shield 34 may be provided below.

In the first and second embodiments, the case where the fuse is blown by the laser beam has been described. However, the present invention is not limited to this, and various modifications are possible. It is also possible to blow the fuse with an energy beam.

In the first to fourth embodiments, the upper insulating film is the surface protective film, but the present invention is not limited to this. For example, the interlayer insulating film forming the uppermost wiring layer among the wiring layers. Also good.

Further, in the above-mentioned Examples 5 to 7, the case where the fuse protective film is SiO ₂ has been described.
The present invention is not limited to this, and various changes can be made. For example, a Si ₃ N ₄ , PSG (Phospho Silicate Glass) film, or a laminated film thereof may be used.

FIG. 51 shows a fuse protection film 36c having a laminated structure.
For example: The insulating film 36 at the bottom of the fuse protection film 36c
The c ₁ is made of, for example, SiO ₂ and has a function of suppressing the generation of cracks in the fuse protection film 36c due to the stress of the fuse 16. The intermediate insulating film 36c ₂ is made of, for example, Si ₃ N ₄ , and has a function of suppressing entry of impurity ions, moisture, and the like. Uppermost insulating film 36c ₃ is made of, for example, of SiO _2.

In the above description, the case where the invention made by the present inventor is mainly applied to the SRAM with logic which is the background field of application has been described, but the invention is not limited to this and various applications are possible, for example, DRAM. (Dynam
icRAM), memory such as SRAM or DR with logic
It can also be applied to other semiconductor integrated circuit devices such as AM.

Further, it is needless to say that the present invention can be applied not only to the BiC-MOS semiconductor integrated circuit device but also to the semiconductor integrated circuit device formed of CMOS or BiP.

[0259]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1) According to the above-mentioned first aspect of the invention, since the fuse is exposed from the beginning, the fuse can be removed without performing the conventional process of removing the insulating film or the wiring for covering the fuse. Can be cut. Therefore, the fuse cutting process can be made easier than ever before.

Further, when the fuse is cut, the opening is not formed in the insulating film covering the semiconductor chip, so that it is possible to avoid the problem of the prior art in which impurity ions and the like enter from the opening.

Further, since the fuse is provided on the surface protection film, the wiring in the wiring layer below the surface protection film is not regulated as much by the presence or absence of the fuse as before, so the wiring layout rule is relaxed as compared with the conventional case. It becomes possible to do.

(2) According to the second invention, it is possible to suppress the corrosion, oxidation and exfoliation of the fuse due to the impurity ions, water and the like. It is possible to suppress the fluctuation of the fuse resistance value and the malfunction of the redundant circuit due to the fluctuation of the fuse resistance value. Therefore, the yield and reliability of the semiconductor integrated circuit device can be improved.

(3) According to the above-mentioned third invention, when the electrode conductor pattern is patterned, the fuse is simultaneously patterned. Therefore, it is necessary to manufacture a new photomask for patterning the fuse. There is no. Also,
No additional manufacturing steps are required to form the fuse. That is, the fuse can be formed without increasing the photomask and the number of manufacturing steps.

(4) According to the fourth invention, the fuse protection film can be formed without increasing the number of photomasks and without significantly increasing the number of manufacturing steps. Therefore, it is possible to manufacture a highly reliable semiconductor integrated circuit device without causing a significant increase in manufacturing cost or manufacturing time.

(5) According to the fifth aspect of the invention, the exposed portion of the fuse exposed by the cutting process is covered with the fuse protective film again to suppress the intrusion of impurity ions, moisture and the like from the exposed portion of the fuse. Because you can
It is possible to suppress the corrosion, oxidation, peeling and the like of the fuse, and it is possible to improve the yield and reliability of the semiconductor integrated circuit device.

(6) According to the sixth invention, the photoresist pattern used as the etching mask when the fuse protection film portion on the underlying metal is removed by etching is used as the deposition mask at the time of bump formation.
The fuse protection film can be formed without increasing the number of photomasks and without significantly increasing the number of manufacturing steps. Therefore, it is possible to manufacture a highly reliable semiconductor integrated circuit device without causing a significant increase in manufacturing cost or manufacturing time.

[Brief description of drawings]

FIG. 1 is a sectional view of a fuse forming a part of a redundant circuit of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a partial cross-sectional view of a semiconductor integrated circuit device having the fuse of FIG.

FIG. 3 is an enlarged sectional view of a CCB bump and a base metal.

4 is an overall enlarged plan view of a semiconductor chip having the fuse of FIG.

5 is a circuit diagram showing a connection state of the fuse of FIG.

6 is an enlarged cross-sectional view of the fuse of FIG. 1 and a semiconductor substrate below the fuse.

7 is an overall enlarged plan view of the fuse of FIG.

8 is a perspective view of a main part for explaining an example of a method of forming the fuse of FIG.

FIG. 9 is a perspective view of a main part for explaining an example of a method of forming the fuse of FIG.

10 is a perspective view of a main part for explaining an example of a method of forming the fuse of FIG.

11 is a perspective view of relevant parts for explaining an example of a method of forming the fuse of FIG.

12 is a perspective view of a main part for explaining an example of a method of forming the fuse of FIG.

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate showing the fuse during the cutting process.

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate showing the fuse after the cutting process.

15 is an overall plan view of the fuse after the cutting process of FIG.

FIG. 16 is a cross-sectional view of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 17 is a cross-sectional view of a TAB bump and a TAB base metal.

18 is a sectional view of a fuse forming a part of a redundant circuit of the semiconductor integrated circuit device shown in FIG.

19 is an enlarged cross-sectional view of the fuse of FIG.

FIG. 20 is a plan view of the fuse shown in FIG.

FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate showing the fuse during the cutting process.

FIG. 22 is a fragmentary cross-sectional view of the semiconductor substrate showing the fuse after the cutting process.

FIG. 23 is an overall enlarged plan view of a fuse forming a part of a redundant circuit of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 24 is a cross-sectional view of the fuse shown in FIG.

FIG. 25 is an overall enlarged plan view of a fuse forming a part of a redundant circuit of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 26 is a cross-sectional view of essential parts of the fuse shown in FIG. 25.

FIG. 27 is a fragmentary cross-sectional view of a semiconductor integrated circuit device which is an embodiment of the present invention.

28 is an explanatory diagram of an example of a method for manufacturing the semiconductor integrated circuit device of FIG. 27.

FIG. 29 is an explanatory diagram of the manufacturing method example of the semiconductor integrated circuit device of FIG. 27;

30 is an explanatory diagram of the manufacturing method example of the semiconductor integrated circuit device of FIG. 27;

31 is an explanatory diagram of an example of a method for manufacturing the semiconductor integrated circuit device of FIG. 27.

32 is an explanatory diagram of an example of a method of cutting a fuse of the semiconductor integrated circuit device of FIG. 27.

33 is an explanatory diagram of an example of a method of cutting a fuse of the semiconductor integrated circuit device of FIG. 27.

34 is an explanatory diagram of an example of a method of cutting a fuse of the semiconductor integrated circuit device of FIG. 27.

FIG. 35 is an explanatory diagram of an example of a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 36 is an explanatory diagram of an example of a method for manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 37 is a fragmentary cross-sectional view of a semiconductor integrated circuit device which is another embodiment of the present invention.

38 is a plan view of relevant parts of the semiconductor integrated circuit device of FIG. 37. FIG.

FIG. 39 is an explanatory diagram of the manufacturing method example of the semiconductor integrated circuit device of FIG. 37;

FIG. 40 is a fragmentary cross-sectional view of a semiconductor integrated circuit device which is another embodiment of the present invention.

41 is an explanatory diagram of the manufacturing method example of the semiconductor integrated circuit device of FIG. 40;

42 is an explanatory diagram of the manufacturing method example of the semiconductor integrated circuit device of FIG. 40;

FIG. 43 is an overall enlarged plan view of a fuse forming a part of a redundant circuit of a semiconductor integrated circuit device which is another embodiment of the present invention.

44 is a cross-sectional view of essential parts of the fuse shown in FIG. 43.

FIG. 45 is an overall enlarged plan view of a fuse forming a part of a redundant circuit of a semiconductor integrated circuit device which is another embodiment of the present invention.

46 is a cross-sectional view of essential parts of the fuse shown in FIG. 45.

FIG. 47 is an overall enlarged plan view of a fuse forming a part of a redundant circuit of a semiconductor integrated circuit device which is another embodiment of the present invention.

48 is a fragmentary cross-sectional view of the fuse shown in FIG. 47. FIG.

FIG. 49 is an overall enlarged plan view of a fuse forming a part of a redundant circuit of a semiconductor integrated circuit device which is another embodiment of the present invention.

50 is a fragmentary cross-sectional view of the fuse shown in FIG. 49. FIG.

51 is a cross-sectional view of essential parts of a semiconductor integrated circuit device which is another embodiment of the present invention. FIG.

[Explanation of symbols]

1a Chip carrier (semiconductor integrated circuit device) 1b QFP (semiconductor integrated circuit device) 2 Package substrate 3a Electrode 3b Electrode 4 Internal wiring 5 CCB bump 6 CCB bump 7 Semiconductor chip 8a Metal layer 8b Metal layer 8c Metal layer 9 Surface protective film 10 Through hole 11 Lead-out electrode 12 Cap 13 Sealing solder 14 Joining metal layer 15 Heat transfer solder 16 Fuse 16a Cutting point 16b1 Non-cutting point 16b2 Non-cutting point 17 nMOS 18 Semiconductor substrate 19 Buried layer 20 Epitaxial layer 21 Leading diffusion layer 22a Resistance diffusion layer 22b Resistance diffusion layer 23 Separation groove 24 Field insulating film 25a Interlayer insulating film 25b Interlayer insulating film 25c Interlayer insulating film 25d Interlayer insulating film 25e Interlayer insulating film 26a1 First layer wiring 26a2 First layer wiring 26a3 First Stratification 26a4 First layer wiring 26b1 Second layer wiring 26b2 Second layer wiring 26c1 Third layer wiring (energy beam shield) 26c2 Third layer wiring 26d1 Fourth layer wiring (energy beam shield) 26d2 Fourth layer wiring 26e1 Fifth Layer wiring (energy beam shield) 26e2 Fifth layer wiring 26e3 Fifth layer wiring 26e4 Fifth layer wiring (energy beam shield) 27a1 through hole 27a2 through hole 27a3 through hole 27a4 through hole 27b1 through hole 27b2 through hole 27c1 through hole 27c2 through hole 27d1 through hole 27e1 through hole 27f1 through hole 27f2 through hole 27f3 through hole 27f4 through hole 28 resist film 28a resist pattern 28a1 pattern part 28a2 pattern part 28b Resist pattern 28c resist pattern 29 die pad 30 package body 31 bumps 32 TAB lead 33 lead 34 guard ring 35 laser shield (energy beam shield) 36 fuse protection film 36a Fused film 36b fuse protection film 36c fusing film 36c ₁ insulating film 36c ₂ Insulating film 36c ₃ Insulating film 37 Solder (metal for bump formation) BLM Base metal (base metal for CCB bump) IF Base metal (base metal for TAB bump) M Memory circuit block R ₁ resistance R ₂ resistance LB ₁ laser beam (Energy beam) LB ₂ Laser beam (Energy beam) FIB Focused ion beam (Energy beam) F region T terminal W1 width W2 width

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jun Hirokawa 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (20)

[Claims] 1. A fuse forming a part of a redundant circuit formed on a semiconductor chip is formed on an insulating film on an upper layer of the semiconductor chip, and an electrode conductor pattern formed on the insulating film on the upper layer is formed. A semiconductor integrated circuit device comprising at least a part of constituent materials. 2. The semiconductor integrated circuit device according to claim 1, wherein the upper insulating film is a surface protective film. 3. The semiconductor integrated circuit device according to claim 1, wherein the electrode conductor pattern is a base metal for CCB bumps or a base metal for TAB bumps. 4. The semiconductor integrated circuit device according to claim 1, wherein the fuse is made of a transition metal. 5. An energy beam shield that shields an energy beam for cutting a fuse is provided in a lower layer of the fuse.
Alternatively, the semiconductor integrated circuit device according to item 4. 6. The semiconductor integrated circuit device according to claim 5, wherein the energy beam shield is electrically connected to a wiring having a predetermined potential formed on the semiconductor chip. 7. A guard ring surrounding at least a part of the outer periphery of the fuse is provided, and the guard ring is electrically connected to a lower layer wiring through a connection hole formed in a surface protection film. 2, 3, 4, 5,
Or the semiconductor integrated circuit device according to item 6. 8. A semiconductor integrated circuit device, wherein a fuse forming a part of a redundant circuit formed on a semiconductor chip is made of a transition metal and provided on a surface protection film of the semiconductor chip. 9. A semiconductor integrated circuit device, wherein the fuse according to claim 8 is composed of at least a part of a constituent material of a base metal for CCB bumps. 10. On the main surface of the semiconductor chip,
10. The semiconductor integrated circuit device according to claim 1, wherein a fuse protection film for protecting the fuse is formed in at least a cut region of the fuse. 11. The fuse protective film material for protecting the fuse is injected into a package for encapsulating the semiconductor chip, according to claim 1. Integrated circuit device. 12. A method for manufacturing a semiconductor integrated circuit device, wherein when forming the electrode conductor pattern according to claim 1, the fuse is simultaneously formed. 13. A method of manufacturing a semiconductor integrated circuit device, wherein when the base metal for CCB bumps or the base metal for TAB bumps according to claim 3 is patterned, the fuse is patterned at the same time. 14. When manufacturing a semiconductor integrated circuit device according to claim 10, at least a cutting region of the fuse is irradiated with an energy beam in a predetermined reaction gas atmosphere to selectively perform CVD to form a fuse protection film. A method of manufacturing a semiconductor integrated circuit device, which comprises forming the semiconductor integrated circuit device. 15. A method of manufacturing a semiconductor integrated circuit device, wherein the energy beam according to claim 14 is a laser beam, a focused ion beam or an electron beam. 16. The step of cutting the fuse according to claim 10, wherein at least a part of the fuse protection film is removed by a focused ion beam to expose at least a part of the fuse, and an exposed part of the fuse is exposed. And a step of cutting a part of the semiconductor integrated circuit device with a focused ion beam. 17. After cutting the fuse according to claim 10 by a laser beam or a focused ion beam, the exposed region of the fuse exposed by the cutting process is irradiated with an energy beam in a predetermined reaction gas atmosphere, and C
A method for manufacturing a semiconductor integrated circuit device, which comprises performing VD to form a fuse protection film. 18. A method of manufacturing a semiconductor integrated circuit device, wherein the energy beam according to claim 17 is a laser beam, a focused ion beam or an electron beam. 19. When patterning an electrode conductor pattern on a surface protective film of a semiconductor substrate having a semiconductor chip,
A step of simultaneously patterning a fuse, which is a part of a redundant circuit of a semiconductor chip, on the surface protection film by using at least a part of the constituent material of the electrode conductor pattern; and on the semiconductor substrate on which the fuse is formed. A method of manufacturing a semiconductor integrated circuit device, comprising: a step of depositing a fuse protective film; and a step of removing at least a portion of the fuse protective film, which is not covered with a cut region of the fuse, covering the electrode conductor pattern. .. 20. When patterning a base metal for CCB bumps or a base metal for TAB on a surface protective film of a semiconductor substrate having a semiconductor chip, at least a part of the base metal for CCB bumps or the base metal for TAB. A step of simultaneously patterning a fuse, which is a part of a redundant circuit of a semiconductor chip, on the surface protective film using a material; a step of depositing a fuse protective film on the semiconductor substrate on which the fuse is formed; A step of forming a photoresist pattern on the fuse protection film, which exposes only the fuse protection film portion on the CCB bump base metal or the TAB bump base metal; and for the CCB bump using the photoresist pattern as an etching mask. Remove only the fuse protection film on the base metal or the base metal for TAB bumps And a step of depositing a bump forming metal for forming CCB bumps or TAB bumps on the semiconductor substrate by using the photoresist pattern as a deposition mask. Production method.