JPH05114543A - Manufacture of electronic component and reduction stepper, electron beam and x-ray lithographic equipments, and which are used for the same, and wafer - Google Patents

Abstract

PURPOSE:To obtain a manufacturing method of electronic component wherein alignment precision is improved, a demagnification projection aligner, an electron beam and an X-ray lithographic equipments, and which are used for said method, and a wafer which is used for them. CONSTITUTION:In the manufacturing process of electronic parts like a semiconductor device, alignment in the initial lithography process is performed by using an alignment mark 21 on the rear, and an alignment mark 22 is formed also on the surface at the same time as the pattern formation. In the later process, alignment is performed at least one time by using the alignment mark 22 on the surface. A reduction stepper, an electron beam and an X-ray lithograghic equipments have a rear position detection optical system for a wafer and a surface position detection system using light, an electron beam and an X-ray beam.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electronic component such as a semiconductor device and a thin film magnetic head, and a reduction projection exposure apparatus, an electron beam drawing apparatus, an X-ray exposure apparatus and a semiconductor apparatus suitable for use in the method. Wafers used for.

[0002]

2. Description of the Related Art The manufacturing of a semiconductor device has a step of transferring a mask pattern onto the surface of a wafer, and at that time, alignment of both (hereinafter referred to as alignment) is required.
This alignment is performed by forming a mark on the wafer surface and optically detecting this position. However, 0.2μ
Alignment accuracy higher than 0.03 μm is required to manufacture semiconductor devices after the m-rule, and this accuracy is a detection error due to uneven coating of resist or damage to marks in the method of detecting marks on the wafer surface. Made it difficult to achieve.

Therefore, as described in Japanese Patent Publication No. 55-46053, a method for detecting the backside mark of the wafer has been performed. This method is a method for detecting the position of a mark provided on the back surface of the wafer as a position detecting optical system that is not easily affected by the wafer process. When a semiconductor integrated circuit is manufactured by an exposure apparatus having a back surface detection alignment system, front surface detection is not used and only back surface detection is performed from the first step to the final step.

[0004]

When the above-mentioned conventional back mark detection method is used, the following problems occur. When actually manufacturing a semiconductor integrated circuit, it is conceivable to mix and use an existing conventional exposure apparatus. Conventionally, since the surface detection method is used as the alignment method, it becomes necessary to associate the positions of the front and back surfaces of the wafer.
It is not preferable to mix the back side detection and the front side detection without making correspondence between the front and back sides, which directly leads to deterioration of alignment accuracy. If this problem is not solved, it will hinder actual semiconductor manufacturing.

A first object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a fine pattern by using a combination of a front surface detection method and a back surface detection method without causing a decrease in alignment accuracy. A second object of the present invention is to provide a reduction projection exposure apparatus suitable for use in this manufacturing method. A third object of the present invention is to provide an electron beam drawing apparatus suitable for use in this manufacturing method. A fourth object of the present invention is to provide an X-ray exposure apparatus suitable for use in this manufacturing method. A fifth object of the present invention is to provide a wafer suitable for use in this manufacturing method.

[0006]

[Means for Solving the Problems] The first object is to:
(1) A first substrate provided with a desired pattern and a second substrate to which the pattern is transferred are set at predetermined positions, and the position of the second substrate is set by an alignment mark previously provided on the back surface thereof. Detecting, adjusting the relative position of the second substrate and the first substrate, transferring the pattern to the surface of the second substrate, and forming a second alignment mark on the surface of the second substrate. And a method of manufacturing an electronic component,
(2) In the method of manufacturing the electronic component described in the above-mentioned 1, the transfer of the pattern is performed by reduction projection exposure, (3) In the method of manufacturing the electronic component described in the above-mentioned 1, A method for manufacturing an electronic component, wherein the transfer of the pattern is performed by X-ray projection,
(4) A substrate on which a desired pattern is drawn is placed at a predetermined position, the position of the substrate is detected by an alignment mark provided on the back surface of the substrate, and the position of the substrate and the position where the pattern is formed. And (2) are relatively adjusted, the pattern is drawn on the substrate surface, and a second alignment mark is formed on the substrate surface. (5) Any of the above 1 to 4 (1) In the method of manufacturing an electronic component described in (1), the electronic component is a semiconductor device.
5. The method of manufacturing an electronic component as described in 5 above, wherein the semiconductor device is a semiconductor device having an insulated gate field effect transistor,
(7) In the method of manufacturing an electronic component according to the item 5, the semiconductor device is a semiconductor device having an insulated gate field effect transistor having an n-type channel and a p-type channel. , (8) 5 above
The method of manufacturing an electronic component described in claim 1, wherein the semiconductor device is a semiconductor device having a bipolar transistor and an insulated gate field effect transistor having an n-type channel and a p-type channel. To be done.

The second object is (9) means for holding the first substrate provided with a desired pattern, a light source for irradiating the first substrate, and reduction of the pattern of the irradiated first substrate. In a reduction projection exposure apparatus having a reduction projection lens for projecting and a means for holding the second substrate to which the pattern is transferred, alignment marks provided on the front and back of the second substrate are detected. A reduction projection exposure apparatus characterized by having at least two detection optical systems for

The third object is to use (10) an electron gun, a drawing data storage section for storing drawing data, a means for holding a substrate on which a pattern is drawn, and an electron beam emitted from the electron gun. In an electron beam drawing apparatus having an electron lens for drawing a pattern on a substrate according to drawing data, a detection optical system for detecting an alignment mark provided on the back of the substrate and a front surface of the substrate are provided. This is achieved by an electron beam drawing apparatus having a detection system for detecting the alignment mark.

The fourth object is (11) means for holding the first substrate having a desired pattern, an X-ray source for irradiating the first substrate, and a pattern of the irradiated first substrate. X having a reduction projection optical system for reducing and projecting the image and means for holding a second substrate to which the pattern is transferred.
The line exposure apparatus has a detection optical system for detecting an alignment mark provided on the back of the second substrate and a detection system for detecting an alignment mark provided on the front surface of the second substrate. And an X-ray exposure apparatus.

The fifth object is (12) a wafer having a desired pattern formed on the front surface thereof, wherein the wafer has alignment marks on the front surface and the back surface, respectively. (13) In the wafer described in the above 12, A wafer characterized in that the alignment mark on the surface is a mark that acts on light, (14) In the wafer described in (12) above, the alignment mark on the surface is a mark that acts on an electron beam. (15) The wafer according to the above 12, wherein:
The alignment mark on the surface is achieved by a wafer characterized in that it is a mark that acts on X-rays.

According to the method of manufacturing an electronic component of the present invention, the position of the second substrate is detected by the alignment mark provided on the back surface of the second substrate, and the pattern is transferred to the surface of the second substrate based on the detection. The second alignment mark is formed on the surface of the second substrate. In the following steps, the position is detected by the second alignment mark on the surface at least once to form a pattern. The second alignment mark on the surface may be used in all of the following steps. In addition, the alignment mark on the back surface may be used in some steps. In general, it is preferable to use the alignment mark on the back surface in a process that requires high precision in alignment.

The wafer of the present invention has the alignment marks on the front surface and the back surface, respectively, as described above. The alignment mark for light is composed of grooves, holes, protrusions, grid-shaped irregularities formed on the substrate, a metal having a reflectance different from that of the substrate, or the like. The alignment mark for the electron beam is made of the same concave or convex portion as described above, a material that generates secondary electrons, or the like. The alignment mark for X-rays is made up of recesses and protrusions similar to the above, X-ray absorbers or reflectors and the like.

[0013]

The operation of the present invention will be described in detail with reference to FIG.
FIG. 1 (a) is an example according to the present invention. An alignment mark 21 for detecting the back surface is formed on the back surface of the wafer 9 whose both surfaces are mirror surfaces. When performing the lithography process of the first layer of the wafer 9, the wafer 9 is installed in the exposure apparatus using the back surface detection alignment system, and the position of the wafer 9 is detected by the back surface detection alignment system. Then, when the wafer 9 is positioned at a predetermined position and a desired pattern is formed on the resist 23 on the surface of the wafer 9, an alignment mark 22 for surface detection is also formed at the same time, and both are transferred to the wafer 9. In the next lithographic process, alignment by the surface detection method becomes possible. in this case,
This is preferable because the positional relationship is uniquely determined on the front and back of the wafer. The error factors at this time are the detection error σ _r (about 0.05 μm (3σ)) of the back surface detection alignment system and the detection error σ _s (0.1 μm) of the front surface detection alignment system.
(About 3σ)) only. Therefore, the total alignment error σ _rt of the second layer is given by Expression 1.

[0014]

[Equation 1]

Next, a case where the surface detection method is used in the first lithography step as shown in FIG. 1B will be described below as an example. Generally, in the lithography process of the first layer, the pattern is transferred after the wafer 9 is positioned with mechanical accuracy based on the orientation flat (commonly called orientation flat) of the wafer 9. The error σ _m due to this mechanical positioning is about ± 5 μm (3σ). Since this error does not necessarily have any correlation with the back surface mark of the wafer, it directly becomes a position detection error. Therefore, the total alignment error σ _st of the second layer when the back surface alignment system is used in the next second lithography step is given by Expression 2.

[0016]

[Equation 2]

Further, the first layer as shown in FIG. 1 (c) is exposed after being positioned by orientation flat alignment by a surface detection system, an opening is formed in the surface, and a through hole is provided by anisotropic etching. When the back surface detection mark 21 is used to form the second layer, an asymmetrical processing error σ _e of anisotropic etching (about 20 μm (3σ) at a wafer thickness of 400 μm) is included. This error occurs depending on the crystal defect of the wafer 9. If it is an ideal crystal and has no defects, σ _e becomes 0, but in reality, most wafers 9 have defects, so that a processing error occurs. In this case, the total alignment accuracy σ _et of the second layer is given by Expression 3.

[0018]

[Equation 3]

As is clear from the equations (1), (2) and (3), when a semiconductor integrated circuit is manufactured by using a lithographic apparatus having a front surface detection system and a lithographic apparatus having a back surface detection system in a mixed manner, the first lithography step is performed. It can be seen that the method of performing the back surface detection alignment can realize excellent alignment accuracy.

[0020]

Example 1 First, a method of forming a pattern using a reduction projection exposure apparatus as a lithographic apparatus will be described. FIG. 5 is a schematic diagram of a reduction projection exposure apparatus. The reduction projection exposure apparatus is an apparatus that illuminates a reticle 4 on which a pattern of an integrated circuit is drawn by an illumination optical system 1 and reduces and transfers it onto a wafer 9 through a condenser lens 2 and a reduction projection lens 7. The exposure procedure is performed as follows. Focusing between the reduction projection lens 7 and the wafer 9 is performed by the gap sensors 8 and 18. The gap sensors 8 and 18 that use air differential pressure have a simple structure and can detect the position with high accuracy. Further, the wafer 9 is placed on the XYZθ tables 13, 14 and 15 on the table 16 and can be moved to a desired position. The positions of the XYZθ tables 13, 14, and 15 are measured by irradiating the mirror 10 with laser light by the laser length meter 11 and processed by the system control unit 19. The XYZθ tables 13, 14 and 15 are driven by drive units 17a, 17b and 17c.

The positions of the reticle 4 and the wafer 9 must be accurately and relatively aligned. The position of the reticle 4 is measured by the reticle position detection optical system 6 and a signal is sent to the system control unit 19. In the case of the illustrated apparatus, the position of the wafer 9 is measured by the back surface position detection optical system 12 and a signal is sent to the system control unit 19.
Of course, a conventional surface position detecting optical system (not shown) may be used.

When the back surface position detection optical system 12 is used, so-called off-axis alignment is performed in which the detection light does not pass through the reduction projection lens 7. Therefore, it is necessary to match the reference point of the reticle position detection optical system 6 and the reference point of the back surface position detection optical system 12. Therefore, a calibration means 24 for calibrating the two optical systems is provided. This calibration method will be described. First, the reticle 4a having the pattern 25 and the alignment mark 3 for position detection shown in FIG. 6 is installed in the reduction projection exposure apparatus. The reference point position of the reticle 4a is detected using the reticle position detection optical system 6.
Next, the calibration means 24 is moved to the XYZθ stages 13, 14, 1
5 is driven to move directly under the reduction projection exposure lens 7.
In this state, the reticle 4a is illuminated by the illumination light source 1 and the condenser lens 2, and the pattern 25 is laid on the calibration means 24.
Image. The calibrating means 24 is composed of a sensor 27 having sensitivity to the wavelength of the exposure light and can detect the position of the image forming pattern. As a result, the position of the reticle 4a can be detected as the image forming position of the reduction projection lens 7.
Further, on the back surface of the calibration means 24, the mark 2 for back surface detection is provided.
There is 6. At this time, if the back surface detection optical system 12 detects the position of the calibration means 24, the reference point positions of the reticle position detection optical system 6 and the back surface position detection optical system 12 can be calibrated. The thickness of the calibration means 24 is preferably set to be substantially equal to the thickness of the wafer 9 in order to avoid position detection errors.

After performing this calibration operation, the system control unit 19 calculates the relative positional deviation amount, and commands the XYZθ stage drive units 17a, 17b, 17c to move the wafer 9 to a desired position. Then reticle 4
Is installed in a reduction projection exposure apparatus, the alignment mark on the back surface of the wafer 9 is measured by the back surface detection optical system 12, the reticle 4 is illuminated, and a pattern is formed on the photosensitive film on the wafer 9. Transfer this to. The above is the description when the lithography process is performed using the reduction projection exposure apparatus. In FIG. 5, reference numeral 5 is a position adjusting table, and 20 is a driving means for moving the table.

Next, using this method, MOS (metal)
An example of manufacturing an oxide semiconductor type insulated gate type field effect transistor will be described with reference to FIG. First, on the surface of the p-type Si substrate 51, S with a film thickness of 35 nm is formed.
An iO ₂ oxide film 52 is formed and a 100 nm-thickness Si ₃ N ₄ film 53 is deposited thereon (FIG. 2A). Then, a photoresist film 54 is formed, and after positioning by the back surface detection alignment system described above, the photoresist film 54 is patterned. At this time, an alignment mark (not shown) for surface detection is formed. The Si ₃ N ₄ film 53 is patterned by dry etching, and further, about 10 ¹³ / cm ² of B is ion-implanted using the photoresist film 54 as a mask to form a channel stopper (FIG. 2B). Then, a field oxide film 55 of about 800 nm is formed by wet oxidation (FIG. 2C).

The Si ₃ N ₄ film 53 and the SiO ₂ oxide film 52 are removed, a gate oxide film 56 made of SiO ₂ is formed by dry oxidation, and B is ion-implanted at about 10 ¹² / cm ² (FIG. 2).
(D)). Next, polycrystalline silicon is deposited and P is 10 ²¹ /
cm ^{3 is} added, and a gate 57 is formed by dry etching using a photoresist film (not shown) as a mask. At this time, the pattern of the photoresist film is formed using the alignment mark for surface detection formed in the above step. To form a source and a drain, As is ion-implanted at about 10 ¹⁶ / cm ² using the gate 57 as a mask (FIG.
(E)).

SiO ₂ film 5 containing P as an interlayer insulating film
8 is formed to a thickness of about 500 nm by the chemical vapor deposition (CVD) method, and is heat treated to flatten the surface (FIG. 2 (f)).
Next, position with the alignment mark for back side detection,
A pattern of a photoresist film is formed, and a connection hole is formed by dry etching. After that, Al containing Si is vapor-deposited and positioned with an alignment mark for back surface detection.
A pattern of a photoresist film is formed and dry etching is performed to form a wiring pattern 59 (FIG. 2G). Hereinafter, an nMOS field effect transistor is manufactured as usual.

The last two positionings may be carried out by positioning with the alignment mark for surface detection.
Through the above process, n with good alignment accuracy
A semiconductor device having an integrated circuit of MOS structure can be manufactured.

<Embodiment 2> CMOS of double well structure
An example of manufacturing (Comlementary Metal Oxide Semiconductor; MOS having n-type channel and p-type channel) will be described with reference to FIG. First, an SiO ₂ film (not shown) is formed on the n-type substrate 60, and then a photoresist film (not shown).
Are formed and positioned by the back surface detection alignment system described above, and then the photoresist film is patterned. At this time, an alignment mark (not shown) for surface detection is formed. With this pattern, a SiO ₂ film is used as a pattern, and using this as a mask, the n well 61 and the p well 62 are formed by the self-alignment method (FIG. 3A).

Next, the field oxide film 55 is formed in the same manner as in Example 1, but at this time, the alignment mark for front surface detection is used for positioning (in this case, even if the alignment mark for rear surface detection is used, In this step, the surface may be positioned at least once with the alignment mark for surface detection). A gate oxide film (not shown) made of SiO ₂ is formed in the same manner as in Example 1 (FIG. 3B).

Polycrystalline Si is formed by a CVD method, the polycrystalline Si is made conductive by diffusion of n-type impurities, and the gate 57 is formed using this as a pattern. Using the gate 57 as a mask, As and then B are implanted to form a high-concentration n-type layer and a high-concentration p-type layer to be the source and drain (FIG. 3C).

After forming an interlayer insulating film 58 'made of SiO ₂ by a high temperature CVD method, a polycrystalline Si 63 is deposited,
It processes (FIG.3 (d)). A passivation film 64 is formed, positioned, and contact holes are formed (FIG. 3E),
Al is vapor-deposited and further positioned by a back surface detection alignment system to form a wiring pattern 59 (FIG. 3 (f)),
A semiconductor device having an integrated circuit of CMOS structure could be manufactured with good alignment accuracy.

<Third Embodiment> Next, an example of manufacturing a bipolar-CMOS (hereinafter abbreviated as Bi-CMOS) will be described with reference to FIG. FIG. 4A is a diagram for explaining the manufacturing process of the Bi-CMOS, and FIG. 4B is a sectional view of the manufactured Bi-CMOS. The Bi-CMOS has both advantages such as high-speed bipolar and CMOS with low power consumption.

Lithography is performed to form the high-concentration n-type buried layer 71 and the high-concentration p-type buried layer 72 on the p-type substrate 70. At this time, a pattern is formed using an exposure apparatus having a back surface detection alignment system. In this case as well, similar to the first and second embodiments, an alignment mark for surface detection is formed for the next lithography.

In the steps below, lithography was performed using alignment marks for surface detection, unless otherwise specified. First, a thin epitaxial layer is grown to form an n well 61 and a p well 62, and a field oxide film 55 is formed. A layer of polycrystalline silicon is deposited to form the gate 57 of the CMOS transistor as a pattern. The collector and base regions of the bipolar transistor are formed by ion implantation, and the emitter electrode 73 of the bipolar transistor is formed by depositing and patterning a polycrystalline silicon layer.

After the passivation film is formed, a contact hole is formed using the alignment mark for detecting the back surface,
l-wiring is formed, and Bi-CM with good alignment accuracy
An integrated circuit having an OS structure could be manufactured.

<Embodiment 4> Next, as shown in FIG. 7, a case in which a back surface detection optical system 12 is provided in an electron beam drawing apparatus will be described. The figures stored in the drawing data storage unit 36 are drawn on the wafer 9 by the electron gun 37 and the electron lenses 38a, 38b, 38c. The back surface detection optical system 1 is provided on the back surface of the wafer 9.
Install 2. The calibration means 24 is composed of a sensor 27 having sensitivity to an electron beam. The other parts are almost the same as those in the first embodiment, and the sample moving means 40 is composed of an XYZθ stage, but detailed drawings are omitted.

Using this electron beam drawing apparatus, the same semiconductor device as in Example 1 was manufactured. In the first step, the alignment mark on the back surface of the wafer 9 is detected by using the back surface detection optical system 12 to perform alignment, and when a pattern is formed on the front surface, the alignment mark is also formed on the front surface of the wafer 9. After that, the alignment is performed at least once using the alignment mark on the surface. In this way, the alignment could be performed with high accuracy.

<Embodiment 5> Next, as shown in FIG. 8, a case where a back surface detection optical system 12 is provided in an X-ray projection exposure apparatus will be described. The light generated from the exposure light source 28 is condensed by the illumination mirror 29 to illuminate the mask 30 on which the pattern is formed. The reflected light is reflected by the illumination mirrors 31, 32, 33, 3
The light is reflected by the projection optical mirror group 42 including 4 and forms an image on the wafer 9 to form a pattern. In the case of a reflection type optical system, since the entire surface of the mask 30 cannot be illuminated at one time, generally, as shown in FIG.
And perform synchronous scanning for exposure. Also, the mask 30 and the wafer 9
As for the relative alignment between them, the back surface detection optical system 12, the mask position detection optical system 35 and the calibration means 24 of the present invention are used as in the first embodiment. The alignment method is the same as in the first embodiment.

A semiconductor device similar to that of Example 1 was manufactured using the X-ray projection exposure apparatus. In the first step, the alignment mark on the back surface of the wafer 9 is detected by using the back surface detection optical system 12 to perform alignment, and when a pattern is formed on the front surface, the alignment mark is also formed on the front surface of the wafer 9. After that, the alignment is performed at least once using the alignment mark on the surface. In this way, the alignment could be performed with high accuracy.

Although the above-mentioned embodiments show examples of manufacturing a semiconductor device, a lithography technique is generally used for processing a thin film head of a magnetic disk, and the present invention is applicable to such a magnetic disk. It can also be applied to the processing of thin film heads.

[0041]

According to the method of manufacturing an electronic component of the present invention,
Since the back surface alignment mark of the wafer is detected to form the pattern of the first layer, even if the back surface alignment mark is detected and aligned in the subsequent superposition process, the front surface alignment mark is detected and aligned. Even in any case, high alignment accuracy can be obtained.

Further, the reduction projection exposure apparatus, the electron beam drawing apparatus and the X-ray exposure apparatus of the present invention detect the measurement system for detecting the reflection of light, electron beam and X-ray by the front surface alignment mark and the back surface alignment mark of the wafer. Has an optical system that
Suitable for carrying out the above method.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a wafer cross section for explaining the present invention.

FIG. 2 is a diagram showing a case where the present invention is applied to an nMOS manufacturing process.

FIG. 3 is a diagram showing a case where the present invention is applied to a CMOS manufacturing process.

FIG. 4 is a diagram showing a case where the present invention is applied to a Bi-CMOS manufacturing process.

FIG. 5 is a schematic view of an example of a reduction projection exposure apparatus of the present invention.

FIG. 6 is a diagram showing an example of a reticle pattern necessary for carrying out the present invention.

FIG. 7 is a schematic view of an example of an electron beam drawing apparatus of the present invention.

FIG. 8 is a schematic view of an example of an X-ray reduction projection exposure apparatus of the present invention.

[Explanation of symbols]

1 illuminating light source 2 condenser lens 3, 21, 22 alignment mark 4, 4a reticle 5 table 6 reticle position detection optical system 7 reduction projection lens 8, 18 gap sensor 9 wafer 10 mirror 11 laser length meter 12 back surface position detection optical system 13, 14, 15 XYZθ stage 16 units 17a, 17b, 17c drive unit 19 system control unit 20 drive means 23 resist 24 calibration means 25 pattern 26 mark 27 sensor 28 exposure light source 29, 31, 32, 33, 34 illumination mirror 30 mask 35 mask position detecting optical system 36 drawing data storage unit 37 electron gun 38a, 38b, 38c electron lens 40 sample moving means 41 control device 42 a projection optical mirror group 51 p-type Si substrate 52 SiO ₂ oxide film 53 Si ₃ N ₄ film 54 Torejisuto film 55 field oxide film 56 gate oxide film 57 gate 58 SiO ₂ film 58 'interlayer insulating film 59 wiring pattern 60 n-type substrate 61 n-well 62 p-well 63 polycrystalline Si 64 passivation film 70 p-type substrate 71 a high concentration n-type Buried layer 72 High-concentration p-type buried layer 73 Emitter electrode

Claims (15)

[Claims] 1. A first substrate provided with a desired pattern and a second substrate to which the pattern is transferred are set at predetermined positions,
The position of the second substrate is detected by an alignment mark provided in advance on the back surface of the second substrate, the relative position of the second substrate and the first substrate is adjusted, and the pattern is transferred onto the surface of the second substrate. A method for manufacturing an electronic component, comprising forming a second alignment mark on the surface of the second substrate. 2. The method of manufacturing an electronic component according to claim 1, wherein the transfer of the pattern is performed by reduction projection exposure. 3. The method of manufacturing an electronic component according to claim 1, wherein the transfer of the pattern is performed by X-ray projection. 4. A substrate on which a desired pattern is drawn is set at a predetermined position, the position of the substrate is detected by an alignment mark previously provided on the back surface of the substrate, and the position of the substrate and the pattern are formed. The relative position is adjusted relatively, the pattern is drawn on the substrate surface, and the second alignment mark is formed on the substrate surface. 5. The method of manufacturing an electronic component according to claim 1, wherein the electronic component is a semiconductor device. 6. The method of manufacturing an electronic component according to claim 5, wherein the semiconductor device is a semiconductor device having an insulated gate field effect transistor. 7. The method of manufacturing an electronic component according to claim 5, wherein the semiconductor device is a semiconductor device having an insulated gate field effect transistor having an n-type channel and a p-type channel. Manufacturing method. 8. The method of manufacturing an electronic component according to claim 5, wherein the semiconductor device is a bipolar transistor and n.
A method of manufacturing an electronic component, comprising a semiconductor device having an insulated gate field effect transistor having a p-type channel and a p-type channel. 9. A means for holding a first substrate having a desired pattern, a light source for irradiating the first substrate, a reduction projection lens for reducing and projecting the pattern of the irradiated first substrate, In a reduction projection exposure apparatus having means for holding a second substrate onto which the pattern is transferred,
A reduction projection exposure apparatus having at least two detection optical systems for detecting alignment marks respectively provided on the front and back sides of the substrate. 10. An electron gun, a drawing data storage unit for storing drawing data, a means for holding a substrate on which a pattern is drawn, and an electron beam emitted from the electron gun are used to draw on the substrate according to the drawing data. In an electron beam drawing apparatus having an electron lens for drawing a pattern, a detection optical system for detecting an alignment mark provided on the back of the substrate and an alignment mark provided on the front surface of the substrate An electron beam drawing apparatus having a detection system. 11. A means for holding a first substrate having a desired pattern, an X-ray source for irradiating the first substrate, and a reduced projection for reducing and projecting the pattern of the irradiated first substrate. In an X-ray exposure apparatus having an optical system and means for holding a second substrate to which the pattern is transferred,
An X-ray exposure apparatus having a detection optical system for detecting an alignment mark provided on the back side of the substrate and a detection system for detecting an alignment mark provided on the front side of the second substrate. 12. A wafer having a desired pattern formed on the front surface, wherein the wafer has alignment marks on the front surface and the back surface, respectively. 13. The wafer according to claim 12, wherein the alignment mark on the surface is a mark that acts on light. 14. The wafer according to claim 12, wherein the alignment mark on the surface is a mark which acts on an electron beam. 15. The wafer according to claim 12, wherein the alignment mark on the surface is a mark that acts on X-rays.