JPH05113885A - Parallel processing program developing device - Google Patents

Abstract

PURPOSE:To obtain a parallel processing program developing device capable of generating a program efficiently by extracting parallelism sufficiently. CONSTITUTION:A parallel processing program by language including a parallel execution text in which processing being executed simultaneously are unified is inputted to an input device 2. An analysis means 5 analyzes the parallel processing program inputted via the input device 2, and judges the required number of arithmetic means and processing with which each arithmetic means should charge. A conversion means 6 converts the parallel processing program to a program to operate each arithmetic means by receiving the decided number of arithmetic means and the processing with which each arithmetic means should charge via the input device 2 by referring to the judged result of the analysis means 5. A code generating means 7 converts the program converted by the conversion means 6 to an instruction code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing program developing apparatus for developing a program for operating a plurality of arithmetic means in a coordinated manner to perform one or a plurality of mutually related works.

[0002]

2. Description of the Related Art For example, VLIW (Very Long Instructio)
In the case of a processor having a plurality of arithmetic means such as a processor called (n Word) and controlling a plurality of arithmetic means via a network by a sequencer, there is a compiler for executing parallel processing. The effect is limited to parallel processing of the operation unit in the assignment statement,
The designer converts the parallel processing of the procedure, which is a unit of work, into the parallel processing of the operation unit, and the plurality of processors equipped with a single calculation means performs one work or a plurality of works associated with each other. In such a case, the designer has directly designed the programs for operating the arithmetic means and the processors separately.

[0003]

However, in the conventional program development method as described above, it is necessary for the designer to consider the load distribution of each arithmetic means or processor, the synchronization of processing, etc., and the optimum processing efficiency is obtained. However, it is difficult to make the system more efficient, and the designer is overloaded, resulting in poor development efficiency.

Therefore, by inputting a program in which parallelism is not taken into consideration (a program of the same format as that executed by one processor having a single arithmetic means), a plurality of arithmetic means are automatically operated. Although a program development apparatus for generating a program for causing parallelism is proposed, this type of program development apparatus analyzes a program that does not consider parallelism and generates a program for operating a plurality of arithmetic means, so Was difficult to analyze, and it was not possible to sufficiently extract parallelism and generate an efficient program.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a parallel processing program development apparatus capable of sufficiently extracting parallelism and generating an efficient program.

[0006]

According to the present invention, there is provided an input device for inputting a parallel processing program in a language including a parallel execution statement in which processes to be simultaneously executed are summarized, and the parallel input by the input device. Analyzing means for analyzing the processing program to determine the number of necessary calculating means and the processing to be carried by each calculating means, and the number of calculating means and each calculating means determined by referring to the determination result of this analyzing means. Conversion means for converting the parallel processing program into a program for operating each arithmetic means by instructing the processing to be borne by the input device, and a code for converting the program converted by the conversion means into an instruction code. And generating means.

[0007]

In the input device, a parallel processing program in a language including parallel execution statements in which processes to be executed at the same time are collected is input. The analysis means analyzes the parallel processing program input via the input device to determine the number of necessary calculation means and the processing to be carried by each calculation means. The conversion means is
The parallel processing program is converted into a program for operating each arithmetic means by instructing the number of arithmetic means determined with reference to the determination result of the analysis means and the processing to be borne by each arithmetic means via the input device. To do. The code generation means converts the program converted by the conversion means into an instruction code.

[0008]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is an overall configuration diagram of a parallel processing program development apparatus according to an embodiment of the present invention. The parallel processing program development apparatus includes a display device 1, an input device 2, a compiling device 3, and a simulator 4. Therefore, the compiling device 3 includes an analyzing unit 5 and a converting unit 6.
And code generation means 7. The display device 1 is
The information input via the input device 2, the analysis result of the analysis means 5, the simulation result by the simulator 4, etc. are displayed. An operator inputs to the input device 2 a parallel processing program in a language including a parallel execution statement in which processes to be executed at the same time, an instruction regarding the number of calculation means and processing to be carried by each calculation means, and the like. The analysis means 5 of the compiling device 3 analyzes the parallel processing program and determines the number of necessary calculation means and the processing to be borne by each calculation means. Conversion means 6 of the compiling device 3
Converts the parallel processing program into a program for operating each arithmetic means by the operator instructing the number of arithmetic means and the processing to be borne by each operator via the input device 2. The code generation means 7 of the compiling device 3 converts the program converted by the conversion means 6 into an instruction code. The simulator 4 executes the simulation of the program converted by the conversion means 6 based on the instruction of the operator. The display device 1 is configured using, for example, a cathode ray tube or liquid crystal. The input device 2 is composed of, for example, a keyboard and a mouse.
The compiling device 3 and the simulator 4 are composed of, for example, a personal computer or a workstation.

Next, the operation will be described. First, the operator
Design a parallel processing program in a language that includes parallel execution statements that summarize the processing to be executed simultaneously. For example, as shown in FIG. 2, when it is desired to execute the processes C, D, and E at the same time, a parallel processing program in which the processes C, D, and E are described as parallel execution statements is created. Here, the parallel processing program only needs to specify that the processes C, D, and E are to be processed in parallel, and does not need to consider load sharing of each processor or synchronization of processes between processors. Then, the operator operates the input device 2 to input the parallel processing program into the compiling device 3. As a result, the analysis means 5 of the compiling device 3 analyzes all the parallel execution statements included in the parallel processing program, determines the minimum number of calculation means and the processing to be carried by each calculation means,
It is displayed on the display device 1. Thereby, the operator refers to the judgment result of the analysis means 5 displayed on the display device 1 to finally determine the number of calculation means and the processing to be burdened to each calculation means, and to determine it by the input device 2. Instruct by operation. For example, as shown in FIG. 3, the processing A, B, C, and F are assigned to the first computing means, the processing D is assigned to the second computing means, and the processing E is assigned to the third computing means. Instruct. As a result, the conversion unit 6 converts the parallel processing program into a program for operating each arithmetic unit based on the instruction of the operator, and causes the display device 1 to display the end of the conversion work. As a result, the operator operates the input device 2 to activate the simulator 4 to simulate the program converted by the conversion means 6. Various instructions in this simulation are input to the input device 2 while the operator observes the display contents of the display device 1.
To operate. As a result of the simulation, the conversion means 6
If it is confirmed that the converted program operates normally, the operator operates the input device 2 to activate the code generation means 7. As a result, the code generator 7 converts the program converted by the converter 6 into an instruction code. As a result of the simulation, when the program converted by the conversion means 6 does not operate normally, the parallel processing program is inspected, and if there is an error, the parallel processing program is corrected and the work is redone from the input stage of the parallel processing program.

The instruction code thus obtained is, for example, VL.
By operating a processor having a plurality of calculation means called IW, it is possible to operate the plurality of calculation means in a coordinated manner to perform one or a plurality of interrelated works. In this way, by using a language that includes parallel execution statements that summarizes the processes to be executed simultaneously, the analysis unit analyzes the parallel processing program to determine the number of necessary calculation units and the processing that each calculation unit should bear. , The conversion means converts the parallel processing program into a program for operating each arithmetic means based on the number of arithmetic means determined with reference to the determination result of the analysis means and the processing to be borne by each arithmetic means. It is possible to sufficiently extract the characteristics and generate an efficient program. (Specific Example) A program for Hough transform, which is famous as a noise-resistant method for calculating an approximate equation of a line segment on a binarized image, was developed. This Hough transformation is
One point (x _i , y _i ) on the XY coordinates is mapped on the polar coordinate ρ-θ plane by the following formula 1, and the point (ρ ₀ , θ ₀ ) where the locus of the following formula 1 intersects most on this polar coordinate is It is used as a parameter of the approximate straight line to be obtained.

[0011]

[Equation 1]

First, in designing a parallel processing program, the input image is a 256 × 256 256 gradation grayscale image, and the resolution on the ρ-θ plane is ρ = 1 pixel, θ = 1 degree, and the sin used for calculation is used. And cos are given from the outside as a table. The calculation process is divided into a process of calculating the input image data imem and writing it on the ρ-θ plane (two-dimensional memory rtmem), and a process of determining ρ and θ having the maximum values on the ρ-θ plane. However, since the calculation of the former process is completed for each pixel of the input image, it is considered that the speed can be increased by dividing the input image into a plurality of areas and executing the calculation / writing in each of them. .. Therefore, a parallel processing program that can be expressed as shown in FIG. 4 and FIG. 5 was designed by dividing the input image into four and performing the calculation and writing in parallel. Of course, the actual parallel processing program is described in the form of a program list.

The designed parallel processing program is used as the input device 2
, The analysis means 5 of the compiling device 3 analyzes all the parallel execution statements included in the parallel processing program, the number of necessary calculation means is 4, and the processing that each calculation means should bear. And are displayed on the display device 1. Since all the four processes for performing the calculation / writing are the same process, it is more efficient to process them by one calculating means performing the same operation. Therefore, a total of five arithmetic means are used by separately using the arithmetic means for executing the processing for determining the maximum value, and the processing to be borne by each arithmetic means is determined as shown by the broken line in FIG.

When this decision is input by operating the input device 2, the conversion means 6 of the compiling device 3 creates a program that can be expressed as shown in FIGS. 7 and 8 based on the parallel processing program. This program is simulator 4
If there is no error in the program, the input device 2 is operated to activate the code generation means 7 of the compiling device 3. Thereby, the code generation means 7
Converts the program converted by the conversion means 6 into an instruction code.

The meaning of each symbol in FIGS. 4 to 8 is shown in FIG.

[0016]

As described above, according to the present invention, the number of arithmetic means required by analyzing the parallel processing program by the analyzing means by using a language including parallel execution statements in which the processing to be executed simultaneously is summarized. Then, the parallel processing program is determined based on the number of calculation means determined by the conversion means by referring to the determination result of the analysis means and the processing to be executed by each calculation means. Since the program is converted into a program for operating the arithmetic means, the excellent effect that the parallelism can be sufficiently extracted and an efficient program can be generated is exerted.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a parallel processing program development device in an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a processing procedure of a parallel processing program.

FIG. 3 is an explanatory diagram of an allocation state of processing to each arithmetic means.

FIG. 4 is an overall explanatory diagram of a parallel processing program.

FIG. 5 is an explanatory diagram of a part of a parallel processing program.

FIG. 6 is an explanatory diagram of a state of allocation of processing to each arithmetic unit.

FIG. 7 is an overall explanatory diagram of a converted program.

FIG. 8 is an explanatory diagram of a part of the converted program.

FIG. 9 is an explanatory diagram of symbols for expressing a program.

[Explanation of symbols]

 2 input device 5 analysis means 6 conversion means 7 code generation means

Claims (1)

[Claims] 1. An input device for inputting a parallel processing program in a language including a parallel execution statement in which processes to be executed simultaneously are summarized, and the parallel processing program input via this input device is analyzed and required. The input device includes an analysis unit that determines the number of calculation units and the processing that each calculation unit should bear, and the number of calculation units that is determined by referring to the determination result of this analysis unit and the processing that each calculation unit should bear. A conversion means for converting the parallel processing program into a program for operating each arithmetic means when instructed through the code processing means and a code generation means for converting the program converted by the conversion means into an instruction code. Characteristic parallel processing program development device.