JPH0511030A - Logic-circuit testing method - Google Patents

Abstract

PURPOSE:To decrease the testing man-hours for a high-speed logic integrated circuit device and the like on which many SPL circuits are mounted, and to enhance the reliability of the device, CONSTITUTION:Many SPL circuits are mounted on a high-speed logic integrated circuit device and the like as output buffers OB1-OBm which constitute the input/output parts of macro-cells. When the high-speed logic integrated circuit device and the like are made to be in an AC test mode and a test control signal TS is set at a high level, the output signals of logic networks LN1-LNm, which are provided at the front stages of the output buffers OB1-OB-m, are fixed at the low levels. The odd-number pieces of the output buffers are connected in a ring shape, and a ring oscillator is constituted. The frequency of the oscillator is monitored. Thus, the AC characteristics including the transfer- delay times of the plurality of the output buffers, i.e., the SPL circuits, constituting the ring oscillator can be identified efficiently and accurately.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of testing a logic circuit, for example, SMA (Super Macro-).
SPL (Super P) mounted in a macro cell of a high-speed logic integrated circuit device having a cell array structure
The present invention relates to a technique that is particularly effective when used for an AC (alternating current) test of a push-pull logic circuit.

[0002]

2. Description of the Related Art An NTL (Non Threshold) including a phase division circuit for receiving an input signal and an output emitter follower circuit for transmitting an inverted output signal of the phase division circuit.
Logic) circuit. There is also a so-called SPL circuit in which the output emitter follower circuit of the NTL circuit is replaced with a push-pull output circuit.

Regarding the NTL circuit, for example, Japanese Patent Laid-Open No.
It is described in JP-A-3-124615. Also, SP
The L circuit is described, for example, in JP-A-1-261024.

[0004]

Prior to the present invention, the inventors of the present invention have a so-called SMA structure and mount an NTL circuit as a basic logic gate of an internal logic section of a macro cell and use it as an output buffer of its input / output section. A high-speed logic integrated circuit device equipped with an SPL circuit has been developed.

The SPL circuit, as illustrated in FIG.
The totem-pole type output transistors T4 and T5 forming the push-pull output circuit, and the emitter potential of the input transistors T1 and T2, which are composed of the capacitor C1 and the resistor R5, that is, the level change of the non-inverted output signal of the phase dividing circuit, are output to the output transistor T5 And a differential circuit for transmitting to the base of the. The differentiating circuit constitutes, together with the output transistor T5, an active pull-down circuit for the output transistor T4. Further, in the above high-speed logic integrated circuit device, the SPL circuit is used as an output buffer for signal transmission between the logic networks formed by the internal logic section of each macro cell, and its output terminal OS has a relatively large load capacitance. Be combined. From these facts, in the high-speed logic integrated circuit device, it is essential to carry out an AC test for confirming the AC characteristics including the transmission delay time of the SPL circuit.

However, the conventional high-speed logic integrated circuit device does not include means for efficiently and accurately confirming the AC characteristics of these SPL circuits, even though a large number of SPL circuits are mounted. For this reason, as the scale of the high-speed logic integrated circuit device increases, the number of test steps increases, and the AC characteristics of the SPL circuit cannot be accurately determined, which reduces the reliability of the high-speed logic integrated circuit device. occured.

An object of the present invention is to provide a method for testing a logic circuit including an active pull-down circuit and capable of efficiently and accurately identifying AC characteristics of an SPL circuit or the like having a relatively large load capacitance coupled to its output terminal. To do. Another object of the present invention is to reduce the number of test steps for a high-speed logic integrated circuit device or the like having a large number of SPL circuits mounted therein and to enhance its reliability.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a high-speed logic integrated circuit device or the like having a large number of SPL circuits, when a predetermined test control signal is validated, an output signal of a logic network or the like provided in the preceding stage of the SPL circuit is fixed to a predetermined level. , An odd number of SPL circuits are coupled in a ring shape to form a ring oscillator.

[0009]

According to the above means, by monitoring the oscillation frequency of the ring oscillator, the AC characteristics including the transmission delay time of the plurality of SPL circuits forming the ring oscillator can be efficiently and accurately identified. As a result, it is possible to reduce the number of test steps for the high-speed logic integrated circuit device and improve the reliability.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a board layout diagram of one embodiment of a high speed logic integrated circuit device (LSI) to which the present invention is applied. 2 shows a connection diagram of an embodiment of a test system circuit prepared in the high speed logic integrated circuit device of FIG. 1, and FIG. 3 shows input / output units IO1 to IO1 of the macro cell MC.
A circuit diagram of an embodiment of an SPL circuit mounted on IO4 as an output buffer is shown. Based on these figures,
The structure and operation of the high-speed logic integrated circuit device of this embodiment, and the outline and characteristics of the test method will be described. Note that the transistor shown in FIG. 3 (in this specification, a bipolar transistor is simply referred to as a transistor)
Are all NPN-type bipolar transistors, although not particularly limited thereto.

In FIG. 1, the high-speed logic integrated circuit device of this embodiment has a so-called SMA structure and has a size of about 20 mm.
A large number of macro cells MC are arranged in a grid pattern on a (millimeter) square semiconductor substrate SUB surface. These macrocells MC have a size of about 1 mm square, and are arranged along the four sides of the semiconductor substrate SUB and an internal logic unit ILC arranged in the central portion of the plurality of NTL circuits NTL. A plurality of SPL circuits SPL are provided, for example, with input / output units IO1 to IO4 arranged in two columns. The NTL circuit is used as a basic logic gate of the internal logic unit ILC, and the SPL circuit is used as an output buffer OB1 or the like for transmitting a signal between the logic networks including these basic logic gates.

Here, the input / output unit IO1 of the macro cell MC
Each of the SPL circuits mounted in IO4 is provided with two input transistors T1 arranged in parallel and receiving the input signal IS1 or IS2 corresponding to the base thereof, as represented by the output buffer OB1 in FIG. And T2. The commonly coupled collectors of these input transistors are coupled to the ground potential of the circuit through resistor R1,
Its common-coupled emitter is coupled to power supply voltage VEE via resistor R2. Here, the power supply voltage VEE is
It is set to a negative power supply voltage such as -2V. The input signals IS1 and IS2 are digital signals having a relatively small amplitude. As a result, the input transistor T1
And T2 and resistors R1 and R2 form a so-called phase division circuit. The commonly coupled collectors of the input transistors T1 and T2 are the inverting output node n1 of the phase divider circuit, and their commonly coupled emitters are the non-inverting output node n2 of the phase divider circuit. In addition, NTL
Although not specifically described in detail, the circuit has a circuit configuration in which an output emitter follower circuit including a transistor and a resistor is added to the phase division circuit.

The output buffer OB1 further includes a pair of output transistors T4 and T5 provided in a totem pole configuration between the ground potential of the circuit and the power supply voltage VEE.
Of these, the base of the output transistor T4 is coupled to the commonly coupled collectors of the input transistors T1 and T2, that is, the inverting output node n1 of the phase division circuit, and the base of the output transistor T5 is coupled to the input transistor T1 via the capacitor C1. And T2 are commonly coupled emitters, ie, to the non-inverting output node n2 of the phase divider circuit. Base of output transistor T5 and power supply voltage VE
A resistor R5 that constitutes a differentiating circuit together with the capacitor C1 is provided between the resistor E and E. Also, the output transistor T
The co-coupled emitter and collector of 4 and T5 are
It is coupled to the output terminal OS of the output buffer OB1. As a result, the output transistors T4 and T5 form a so-called push-pull circuit, and the differentiation circuit including the output transistor T5 and the capacitor C1 and the resistor R5 acts as an active pull-down circuit for the output transistor T4.

A biasing transistor T3 is provided between the ground potential of the circuit and the base of the output transistor T5. At the base of the biasing transistor T3, a power supply voltage V is supplied from a voltage generating circuit including a resistor R3 and diodes D1 and D2 via a base resistor R4.
2 × VBE from EE (where VBE is diode D
1 and D2 forward voltage, which represents the base-emitter voltage of the bipolar transistor). As a result, the output transistor T5 is biased to the state immediately before it is turned on by applying a bias voltage higher than the power supply voltage VEE by VBE to its base. The bias transistor T3
The base of is coupled to the output terminal OS via the capacitor C2, although not particularly limited thereto. This capacitor C2
Indicates the level change of the output signal OS by the output transistor T5.
A feedback circuit for transmitting the signal to the base of the output circuit is constructed, whereby the falling change of the output signal OS is accelerated.

A clamp circuit composed of two diodes D3 and D4 is further provided between the ground potential of the circuit and the output terminal OS. Further, a resistor R having a relatively large resistance value is provided between the output terminal OS and the power supply voltage VEE.
6 is provided.

When either the input signal IS1 or IS2 is set to a high level such as the ground potential of the circuit, in the output buffer OB1, the corresponding input transistor T1 or T2 is turned on and the resistor R1 has a predetermined collector. A current Ic is passed. Therefore, the inverted output signal n1 of the phase division circuit is set to a predetermined low level VLn1 of VLn1 = −Ic × R1, and its non-inverted output signal n2 is a high level lower by VBE than the high level of the input signal IS1 or IS2. To be done.

The low level VLn1 of the inverted output signal n1 of the phase division circuit is transmitted as it is to the base of the output transistor T4, and the rising change of the non-inverted output signal n2 is output to the output transistor via the differentiation circuit composed of the capacitor C1 and the resistor R5. It is transmitted to the base of T5. Therefore, the output transistor T4 is turned off and the output transistor T5 is temporarily turned on. As a result, the output signal OS of the output buffer OB1 changes to the power supply voltage V
It drops rapidly towards EE. However, as described above, the clamp circuit including the diodes D3 and D4 is provided between the ground potential of the circuit and the output terminal OS.
However, the low level of the output signal OS is approximately −2 × V.
It is clamped at the level of BE, which causes the output signal O
Undershoot of S is suppressed.

On the other hand, when the input signals IS1 and IS2 are both set to low level, the input transistors T1 and T2 are input.
Are turned off at the same time. Therefore, the inverted output signal n1 of the phase division circuit is set to a high level such as the ground potential of the circuit, and the non-inverted output signal n2 thereof is set to a low level lower by VBE than the low level of the input signals IS1 and IS2. The high level of the inverted output signal n1 of the phase division circuit is directly transmitted to the base of the output transistor T4, and the falling change of the non-inverted output signal n2 is transmitted to the base of the output transistor T5 via the differentiating circuit. As a result, the output transistor T5 rapidly turns off, and instead the output transistor T4 turns on.
As a result, the output signal OS of the output buffer OB1 is -V.
It is a high level like BE.

From the above, the output buffer OB of FIG.
1 functions as a 2-input NOR gate for the input signals IS1 and IS2, and has a push-pull output circuit, so that its driving capability is relatively large, and it is an effective means for signal transmission between logic networks.

In the high-speed logic integrated circuit device of this embodiment, the m output buffers OB1 to OBm forming the input / output units IO1 to IO4 of each macrocell MC have one input as shown in FIG. Two corresponding logical networks LN1 and LN2 to LNm via terminals
And LN1 and contributes to signal transmission, and is selectively connected in series through the other input terminal to form a test system circuit of the high-speed logic integrated circuit device. That is, one input terminal of the output buffer OB1 is provided with the output signal of the corresponding logic network LN1 at the preceding stage, that is, the NOR gate NO11 provided at the final stage of the logic network LN1.
Is output, and the output signal of a NOR gate NO2m described later is supplied to the other input terminal. The output signal of the output buffer OB1 is supplied to the corresponding input terminal of the subsequent logic network LN2 and also to one input terminal of the corresponding NOR gate NO21. An inverted signal of the test control signal TS by the inverter N2, that is, an inverted test control signal TSB is supplied to the other input terminal of the NOR gate NO21, and its output signal is supplied to the other input terminal of the output buffer OB2 of the next stage. It Here, the test control signal TS is not particularly limited, but is set to a low level when the high-speed logic integrated circuit device is set to a normal operation mode, and is set to a high level when it is set to an AC test mode for confirming the AC characteristics of the SPL circuit. It is a level.

Next, the output signal of the corresponding preceding logic network LN2, that is, the output signal of the NOR gate NO12 provided in the final stage of the logic network LN2, is supplied to one input terminal of the output buffer OB2, and the other input terminal. The output signal of the NOR gate NO21 is supplied to the input terminal of. The output signal of the output buffer OB2 is supplied to the input terminal of the corresponding subsequent logic network LN3 and also to one input terminal of the NOR gate NO22. The inverted test control signal TSB is supplied to the other input terminal of the NOR gate NO22, and its output signal is supplied to the other input terminal of the output buffer OB3 at the next stage. Hereinafter, one of the input terminals of the output buffers OB3 to OBm is connected to the corresponding logical network L of the preceding stage.
The output signals of N3 to LNm are supplied to the other input terminals of the corresponding NOR gates NO22 to NO2m of the preceding stage.
An output signal of -1 is provided. Also, the output buffer OB
The output signals of 3 to OBm are supplied to the input terminals of the corresponding subsequent logic networks LN4 to LN1, and
It is supplied to one of the input terminals of the corresponding NOR gates NO23 to NO2m. These NOR gates NO23 to NO2
An inverted test control signal TSB is commonly supplied to the other input terminal of m, and its output signal is the output buffer O of the next stage.
It is supplied to the other input terminals of B4 to OB1.

When the high-speed logic integrated circuit device is set to the normal operation mode and the test control signal TS is set to the low level, the NOR gates NO11 to NO1m provided at the final stage of the logic networks LN1 to LNm are set to the so-called transmission state. The output signal of the logic network is inverted and transmitted to the corresponding output buffers OB1 to OBm. At this time, the NOR gates NO21 to NO2m have the inverted test control signal TS.
By setting B to high level, a so-called non-transmission state is set, and the output signal is fixed to low level. As a result, the output buffers OB1 to OBm are in the transmission state,
The output signal of the corresponding preceding logic network is inverted and transmitted to the corresponding succeeding logic network.

On the other hand, when the high speed logic integrated circuit device is set to the AC test mode and the test control signal TS is set to the high level, the NOR gates NO11 to NO1m provided at the final stage of the logic networks LN1 to LNm are set to the non-transmission state, The output signal is fixed at low level. Therefore, output buffers OB1 to OBm are brought into a transmission state by inverting and transmitting the output signals of corresponding NOR gates NO2m to NO2m-1 in the preceding stage. At this time, the NOR gates NO21 to NO2m are brought into the transmission state by setting the inverted test control signal TSB to the low level, and the output signals of the corresponding output buffers OB1 to OBm are inverted and transmitted to the output buffers OB2 to OB1 of the next stage. To do. As a result, the output buffers OB1 to OBm have the NOR gates NO21 to NO21.
It is connected in a so-called ring shape via 2 m.

In this embodiment, the number m of output buffers connected in a ring is an odd number. Therefore, when the output buffers OB1 to OBm form a so-called ring oscillator with m units provided in each macro cell MC as a unit and the transmission delay time is tpd1 to tpdm, f = 1 / (tpd1 + tpd2 + ... tpdm) ) Is oscillated at a frequency f. The values of the transmission delay times tpd1 to tpdm of the output buffers OB1 to OBm can be estimated with a predetermined accuracy in advance. However, for example, as shown in FIG.
The output signal of 2 m is output to the outside of the high-speed logic integrated circuit device as a test output signal TO via the inverter N1, and the frequency f is monitored by the test device, so that the m output buffers OB1 to OBm are normally transmitted. It is possible to efficiently and accurately identify the delay time, that is, whether or not it has an AC characteristic. As a result, the number of test steps for the high-speed logic integrated circuit device can be reduced and its reliability can be improved.

As shown in the above embodiment, the present invention is applied to the AC test of the SPL circuit or the like mounted as the output buffer in the high speed logic integrated circuit device or the like having the SMA structure. Various operational effects can be obtained. That is, (1) In a high-speed logic integrated circuit device having a large number of SPL circuits, when a predetermined test control signal is validated, the output signal of the logic network provided in the preceding stage of the SPL circuit is fixed to a predetermined level. In addition, an odd number of SPL circuits are connected in a ring shape to form a ring oscillator, and its oscillation frequency is monitored, so that the AC characteristics including the transmission delay time of the plurality of SPL circuits forming the ring oscillator can be efficiently obtained. In addition, it is possible to obtain an effect that the identification can be accurately performed. (2) According to the above item (1), it is possible to reduce the number of test steps for the high-speed logic integrated circuit device and improve the reliability.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the high-speed logic integrated circuit device is
The structure and the layout of the semiconductor substrate and the macrocell MC are not required, and the shape and layout are arbitrary. In FIG. 2, the number of output buffers coupled in a ring shape in the AC test mode does not need to be the number provided in the input / output section of each macro cell MC as a unit, and is arbitrarily set on the condition that it is an odd number. it can. Also, it goes without saying that the number of these output buffers does not necessarily match the number of logical networks. Various methods of fixing the output signal levels of the logic networks LN1 to LNm and methods of coupling the output buffers OB1 to OBm in a ring shape may be considered. In FIG. 3, the SPL circuit, that is, the output buffer OB1 and the like can have an arbitrary number of inputs and a logical function by changing the number of input transistors and the connection form. Further, a voltage generating circuit for applying a predetermined bias voltage to the bias transistor T3 can be provided commonly to a plurality of SPL circuits. Further, various embodiments can be adopted for the specific circuit configuration of the test system circuit and the SPL circuit of the high-speed logic integrated circuit device, the polarity and absolute value of the power supply voltage and the input signal, and the conductivity type of the transistor.

In the above description, the SP which is mounted as an output buffer in the high-speed logic integrated circuit device which is the field of application which was the background of the invention mainly made by the present inventor.
Although the case where it is applied to the AC test of the L circuit has been described, the present invention is not limited to this, and it is also applicable to the AC test of the similar SPL circuit or various logic circuits mounted in a general-purpose gate array integrated circuit or the like. . INDUSTRIAL APPLICABILITY The present invention can be widely applied as a test method for a logic circuit requiring at least an AC test and a digital integrated circuit device equipped with such a logic circuit.

[0028]

In a high-speed logic integrated circuit device having a large number of SPL circuits, when a predetermined test control signal is validated, an output signal of a logic network or the like provided in the preceding stage of the SPL circuit is set to a predetermined level. While fixing
By combining an odd number of SPL circuits in a ring shape to form a ring oscillator and monitoring the oscillation frequency thereof, the AC characteristics including the transmission delay time of the plurality of SPL circuits forming the ring oscillator can be efficiently and accurately generated. Can be identified. As a result, it is possible to reduce the number of test steps for the high-speed logic integrated circuit device and improve the reliability.

[Brief description of drawings]

FIG. 1 is a board layout diagram showing an embodiment of a high-speed logic integrated circuit device to which the present invention is applied.

2 is a connection diagram showing an embodiment of a test system circuit prepared in the high-speed logic integrated circuit device of FIG.

3 is a circuit diagram showing an embodiment of an SPL circuit mounted as an output buffer in an input / output unit of a macro cell of the high speed logic integrated circuit device of FIG.

[Explanation of symbols]

LSI ... High-speed logic integrated circuit device, SUB ... Semiconductor substrate, MC ... Macro cell, ILC ... Internal logic section, IO1 to IO4 ... Input / output section, SPL ... SP
L circuit, NTL ... NTL circuit. OB1 to OBm ... Output buffer (SPL circuit), L
N1 to LNm ... Logical network, NO11 to NO
1m, NO21 to NO2m ... NOR gate, N1 to N
2 ... Inverter. T1 to T5 ... NPN type bipolar transistor, D
1-D4 ... Diode, C1-C2 ... Capacitor, R1-R6 ... Resistor.

Claims (4)

[Claims] 1. A ring oscillator having an odd number of stages is configured by selectively connecting predetermined logic circuits in accordance with a test control signal.
A method of testing a logic circuit, characterized in that the AC characteristic of the logic circuit is identified by monitoring the oscillation frequency. 2. The logic circuit is an SPL circuit,
The AC characteristic is a transmission delay time of an output signal of the SPL circuit with respect to an input signal.
Method for testing logic circuits. 3. The SPL circuit is included in an input / output unit of a macro cell of a high speed logic integrated circuit device having an SMA structure, and is used as an output buffer for signal transmission between logic networks. The logic circuit test method according to claim 1 or 2. 4. The ring oscillator according to claim 1, wherein a plurality of SPL circuits included in the input / output unit of one macro cell are used as a unit. Method 3 for testing logic circuits.