JPH0511012A - Semiconductor evaluating device - Google Patents

Abstract

PURPOSE:To easily and accurately evaluate the propriety of the operating timing of a semiconductor integrated logic circuit without forming any opening through the surface protective film of the circuit. CONSTITUTION:After the aimed contact position of a probe electrode 21 maintained at a grounding potential is calculated from the layout information of a data base 30, the probe electrode 21 is moved to the aimed contact position by means of each moving means 25, 27, and 29. By bringing the electrode 21 into contact with a surface protective film on the signal line layer of the D-input terminal of the flip-flop 2 of a semiconductor chip 1, it is checked that whether or not the logical value of the Q-output becomes a normal value when the timing of the D-input is forcibly delayed. Therefore, the probe electrode 21 can be accurately brought into contact with a prescribed position and the propriety of the D-input timing of the flip-flop 2 can be easily and accurately evaluated without forming any opening through the surface protective film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor evaluation device used for functional inspection of a semiconductor integrated logic circuit, for example, for investigating the cause of a malfunction of the semiconductor integrated logic circuit which has been manufactured by trial manufacture.

[0002]

2. Description of the Related Art FIG. 11 is a schematic diagram of a semiconductor integrated logic circuit formed by using MOS transistors.

As shown in FIG. 11, a flip-flop 2 to be inspected is arranged in the central portion of a semiconductor chip 1, a peripheral circuit 3 is arranged around the flip-flop 2, and the flip-flop 2 has a D circuit. , T input terminals are connected to the peripheral circuit 3, and the peripheral circuit 3 has a plurality of input terminals 4a, 4
b, 4c, ..., 4k and output terminals 5a, 5b, 5c,
..., connected to 5k.

When the functional test of the semiconductor chip 1 of which the trial manufacture is completed is not performed normally, a possible cause thereof is a timing failure of the flip-flop 2. In such a case, The timing of the flip-flop 2 is observed, but the input signal of the flip-flop 2 and the output signal of the flip-flop 2 are conventionally observed as shown in FIG.

That is, as shown in FIG. 12, in the peripheral circuit 3, the probe electrodes 6a, 6b, and 6b are provided on the wirings between the D input terminal, the T input terminal, and the Q output terminal of the flip-flop 2, respectively.
6c are brought into contact with each other, and the input signals of the D input terminal and the T input terminal of the flip-flop 2 from the peripheral circuit 3 are taken into the observation device (not shown) from the peripheral circuit 3 via the probe electrodes 6a and 6b. The output signal from the Q output terminal of 2 to the peripheral circuit 3 is taken in by the observation device,
It is determined whether the logical value of the output signal with respect to the input signal is normal or abnormal, and the operation timing of the flip-flop 2 is observed.

By the way, when the probe electrodes 6a to 6c are brought into contact with the respective wirings as shown in FIG. 12, the wiring layer 9 laminated on the interlayer insulating film 8 on the semiconductor substrate 7 is conventionally formed as shown in FIG. An opening 11 is formed in the e surface protective film 10 on the wiring layer 9 so as to be exposed, and the probe electrodes 6a, 6b, 6c are brought into contact with the exposed wiring layer 9.

At this time, in order to maintain the insulation between the wiring layer 9 and the substrate 7 having a different potential, the contact pressure of the probe electrodes 6a to 6c is adjusted so that the interlayer insulating film 8 is not destroyed.

[0008]

In the conventional case, in order to contact the probe electrodes 6a to 6c with a predetermined wiring layer of the semiconductor chip 1, the opening 1 is formed in the surface protective film 10 of the semiconductor chip 1.
1 has to be formed, which is very complicated.

During observation, the probe electrodes 6a to 6c are used.
Also, the electrostatic capacity of the observing device is added in a circuit manner, and the electrostatic capacity causes a shift in the signal phase, so that the operation timing of the flip-flop 2 cannot be observed normally and correct evaluation can be performed. There is a problem that you cannot do it.

The present invention has been made to solve the above-mentioned problems, and it is not necessary to form an opening in the surface protective film as in the conventional case, and it is easy to determine the operation timing of the semiconductor integrated logic circuit. The purpose is to be able to evaluate personality and personality.

[0011]

A semiconductor evaluation device according to the present invention is a semiconductor evaluation device used for investigating the cause of an operation defect of a semiconductor integrated logic circuit, and a predetermined signal wiring of the semiconductor integrated logic circuit is maintained at a ground potential. A probe electrode in contact with a surface protective film on a layer; an input signal generation circuit for applying an inspection input signal to the semiconductor integrated logic circuit when the probe electrode is in contact; An output logic value comparison circuit for determining whether or not the logic value of the output signal of the semiconductor integrated logic circuit is normal; and a control circuit for controlling the operations of the input signal generation circuit and the output logic value comparison circuit. It has a feature.

Further, the target contact position of the probe electrode is calculated by the calculating means based on the layout information of the semiconductor integrated logic circuit, the probe electrode is held by the moving means, and the target contact position calculated by the calculating means. It is also effective to move the probe electrode.

[0013]

According to the present invention, with the probe electrode in contact with the surface protection film on the predetermined signal wiring of the semiconductor integrated logic circuit, the semiconductor integrated logic circuit is tested by the input signal generation circuit under the control of the control circuit. Given an input signal,
The output logic value comparison circuit compares whether or not the output logic value of the semiconductor integrated logic circuit becomes a normal logic value when the timing of this input signal is forcibly delayed by the electrostatic capacitance due to the contact of the probe electrode. Therefore, it is not necessary to form an opening in the surface protective film as in the conventional case, and the quality of the operation timing of the semiconductor integrated logic circuit can be easily and accurately evaluated.

Further, the calculation means calculates the target contact position of the probe electrode based on the layout information of the semiconductor integrated logic circuit, and the moving means moves the probe electrode to the calculated target contact position. Is accurately moved to the target contact position and brought into contact with a predetermined contact position.

[0015]

1 is a block diagram of an embodiment of a semiconductor evaluation apparatus of the present invention.

FIG. 2 is a schematic view of a part of FIG.
In FIG. 1 and FIG. 2, while the probe electrode 21 held at the ground potential is in contact with the surface protection film on a predetermined signal wiring layer of the semiconductor chip 1, the input signal generation circuit 22 causes the D input of the flip-flop 2 to be input. An inspection input signal having a predetermined pattern is applied to the terminal, the Q output signal of the flip-flop 2 by the input of the inspection input signal is input to the output logical value comparison circuit 23, and the output logical value comparison circuit 23 outputs the logic of the Q output signal. The value is compared with a normal logic value, and whether the operation timing of the flip-flop 2 is good or not is evaluated based on the comparison result.

At this time, the control circuit 24 controls the input time of the signal to the flip-flop 2 of the input signal generation circuit 22 and the timing of comparison by the output logical value comparison circuit 23.

By the way, as shown in FIG. 1, the probe electrode 21 is supported by the Z-direction moving means 25 so as to be movable in the Z-direction. The Z-direction moving means 25 extends along the rail 26 in the Y-direction orthogonal to the Z-direction. Is moved by the Y-direction moving means 27, and the Y-direction moving means 27 is further moved by the X-direction moving means 29 along the rail 28 in the X-direction orthogonal to the Y-direction.

As shown in FIG. 1, the semiconductor chip 1
From the database 30 where the layout information of
The layout information of the semiconductor chip 1 to be inspected is read by the calculation means 31, the target contact position at which the probe electrode 21 should be contacted is calculated by the calculation means 31, and the probe electrode 21 is positioned at the calculated target contact position. ,
Each moving means 29, 27, 2 by the system control means 32
The amount of movement in each direction of X, Y, Z by 5 is calculated, and X
The Y direction moving means 27 is moved in the X direction by the direction moving means 29, and the Z direction moving means 2 is moved by the Y direction moving means 27.
5 is moved in the Y direction, the probe electrode 21 is moved in the Z direction by the Z direction moving means 25, and the probe electrode 21 is brought into contact with the surface protective film on the predetermined signal wiring layer of the semiconductor chip 1.

Next, the principle of the present invention will be described.

Now, as shown in FIG. 3, the probe electrode 2
1 is brought close to the wiring to the D input terminal of the flip-flop 2 of the semiconductor chip 1, and as shown in FIG.
When 1 is brought into contact with the surface protection film 10 on the predetermined signal wiring layer 9, as shown in FIG. 5, between the drive elements 3a and 3b forming the peripheral circuit 3 and the D and T input terminals of the flip-flop 2. This is equivalent to inserting a capacitor 33 having the surface protective film 10 as an insulator in a circuit manner between the wiring to the D input terminal and the ground among the signal lines, and the driving element 3a of the peripheral circuit 3 is The load capacity increases.

Then, with the capacitor 33 being equivalently inserted by the contact of the probe electrode 21 as described above,
When an input signal for inspection having a predetermined pattern is given by the input signal generation circuit 22, the drive elements 3a and 3b of the peripheral circuit 3 are
6A and 6B, the drive element is driven at the timing shown by the solid line in FIG. 6A if the probe electrode 21 is not in contact with the surface protective film 10. When the output signal of 3a changes, the load capacitance increases due to the contact of the probe electrode 21.
As shown by the broken line in (a), the change timing of the output signal of the drive element 3a is delayed.

On the other hand, as shown in FIG. 6B, the output signal of the driving element 3b of the peripheral circuit 3, which is a signal to the T input terminal of the flip-flop 2, makes contact with the surface protective film 10 of the probe electrode 21, The timing of rising does not change regardless of non-contact.

However, H and L in FIGS. 6A and 6B represent high level and low level.

Therefore, if the change timing of the signal to the D input terminal of the flip-flop 2 before contacting the probe electrode 21 does not satisfy the hold time with respect to the signal to the T input terminal, the flip-flop 2 becomes The output signal of the flip-flop 2 does not become a normal logic value (“0” or “1”) without operating normally, and the probe electrode 2
If the change timing of the signal to the D input terminal is delayed by bringing 1 into contact, and as a result, the flip-flop 2 operates normally and has a normal logical value, a timing failure of the D input of the flip-flop 2 occurs. Will be.

Next, the flow of the actual evaluation operation will be described with reference to FIG.

When the semiconductor chip 1 having a large number of flip-flops 2 does not operate normally due to the timing failure of one flip-flop 2, when identifying the flip-flop 2 having the timing failure,
As shown in FIG. 7, under the control of the system control unit 32, the layout information of the target semiconductor chip 1 is read from the database 30 by the calculation unit 31, and the target contact position at which the probe electrode 21 should be contacted is calculated. Together with this, the amount of movement of the probe electrode 21 to the target contact position is derived (step S1), and the system control means 3
By the control of 2, the moving means 25, 27, 29 are driven, the probe electrode 21 is moved to the target contact position (step S2), and the probe electrode 21 is moved to the surface protective film 10 on the predetermined signal wiring layer of the semiconductor chip 1. (Step S3).

The control circuit 24, the input signal generating circuit 22, and the output logical value comparing circuit 23 are driven by the control of the system control means 32, and the semiconductor chip 1 is driven by the input signal generating circuit 22 while the probe electrodes 21 are in contact with each other. The inspection input signal is given to the inspection device and the inspection is executed (step S
4) The output logical value comparison circuit 23 causes the semiconductor chip 1
The logical value of the output signal is compared with the normal logical value, and the change timing of the D input signal is forcibly delayed to determine whether the D input timing of the flip-flop 2 is normal or not. It is determined from the comparison result of the comparison circuit 23 (step S5), and if normal, as described above, it is determined that the flip-flop 2 on the semiconductor chip 1 has the D input timing failure of the flip-flop 2 concerned. Is specified (step S6), after which the inspection ends.

On the other hand, if the decision result in the step S5 is NO, it is decided whether or not the inspection of all the flip-flops 2 on the semiconductor chip 1 is completed (step S).
7) If the inspection of all flip-flops 2 is not completed, the process returns to step S1 again, and if completed, the inspection is completed.

Therefore, the probe electrode 21 is connected to the D input terminal of the flip-flop 2 on the surface protection film 1 on the signal wiring layer 9.
The timing of the D input of the flip-flop 2 depends on whether or not the logical value of the Q output of the flip-flop 2 becomes a normal value when the timing of the D input signal of the flip-flop 2 is forcibly delayed by touching 0. Since the presence / absence of the defect is inspected, it is not necessary to form an opening in the surface protection film of the semiconductor chip as in the conventional case, and the presence / absence of the timing defect of the D input of the flip-flop 2 can be easily and accurately evaluated. It will be possible.

Further, the target contact position to be brought into contact with the probe electrode 21 is calculated from the layout information of the semiconductor chip 1 stored in the database 30, and each moving means 25, 2 is moved.
Since the probe electrode 21 is moved to the target contact position by 7, 29, the probe electrode 21 can be accurately brought into contact with the predetermined position, and it is possible to deal with semiconductor chips having various patterns.

Next, FIG. 8, FIG. 9 and FIG. 10 are operation explanatory views of another embodiment of the present invention.

As shown in FIGS. 8 and 9, the probe electrode 21 shown in FIG. 1 is brought into contact with the surface protective film on the signal wiring layer between the T input terminal of the flip-flop 2 and the driving element 3b of the peripheral circuit 3. The capacitor 33 is equivalently inserted between the signal input to the T input terminal and the ground.

Then, with the capacitor 33 being equivalently inserted by the contact of the probe electrode 21 as described above,
When an input signal for inspection having a predetermined pattern is given by the input signal generation circuit 22, the drive elements 3a and 3b of the peripheral circuit 3 are
10 (a) and 10 (b) respectively, the output signal waveforms of the drive elements 3b are not driven by the drive element 3b at the timing shown by the solid line in FIG. 10 (b).
Of the output signal changes, the change timing of the output signal of the drive element 3b is delayed as shown by the broken line in FIG. 10B due to the increase of the load capacitance due to the contact of the probe electrode 21.

On the other hand, as shown in FIG. 10A, the output signal of the driving element 3a of the peripheral circuit 3 which is a signal to the D input terminal of the flip-flop 2 has a timing regardless of whether the probe electrode 21 is in contact or not. It does not change.

Therefore, if the change timing of the signal to the D input terminal of the flip-flop 2 before contacting the probe electrode 21 does not satisfy the setup time with respect to the signal to the T input terminal, the flip-flop 2 becomes The output signal of the flip-flop 2 does not operate normally and does not become a normal logical value (“0” or “1”), and the probe electrode 21 is brought into contact with the output signal, so that the timing of changing the signal to the D input terminal is delayed. As a result, if the flip-flop 2 operates normally and the output signal of the flip-flop 2 has a normal logical value, it means that the timing error of the T input of the flip-flop 2 has occurred.

As described above, by bringing the probe electrode 21 into contact with the surface protective film on the signal wiring to the T input terminal of the flip-flop 2, the same effect as that of the previous embodiment can be obtained.

[0038]

As described above, according to the semiconductor evaluation apparatus of the present invention, the probe electrode at the ground potential is brought into contact with the surface protective film on the predetermined signal wiring layer of the semiconductor integrated logic circuit to bring the probe electrode into contact. The output logic value comparison circuit compares whether the output logic value of the semiconductor integrated logic circuit becomes a normal logic value when it is forcedly delayed by the electrostatic capacitance due to Since it is not necessary to form an opening, it is possible to easily and accurately evaluate the quality of the operation timing of the semiconductor integrated logic circuit, and it is possible to perform a faster analysis.

Further, the calculation means calculates the target contact position of the probe electrode based on the layout information of the semiconductor integrated logic circuit, and the moving means moves the probe electrode to the calculated target contact position. Can be moved to the target contact position with high accuracy, and can be brought into contact with a predetermined contact position with high accuracy, and the reliability of evaluation can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a semiconductor evaluation device of the present invention.

FIG. 2 is a schematic view of a portion of FIG.

FIG. 3 is an operation explanatory diagram of FIG. 1.

FIG. 4 is an operation explanatory diagram of FIG. 1.

5 is an operation explanatory diagram of FIG. 1. FIG.

6 is a signal waveform diagram for explaining FIG. 1. FIG.

FIG. 7 is a flowchart for explaining the operation of FIG.

FIG. 8 is an operation explanatory diagram of another embodiment of the present invention.

9 is an equivalent circuit diagram of FIG.

FIG. 10 is a signal waveform diagram for explaining FIG. 8;

FIG. 11 is a schematic diagram of a general semiconductor integrated logic circuit.

FIG. 12 is an explanatory diagram of a conventional inspection method.

FIG. 13 is an explanatory diagram of a conventional inspection method.

[Explanation of symbols]

1 Semiconductor integrated logic circuit 9 Signal wiring layer 10 Surface protection film 21 probe electrode 22 Input signal generation circuit 23 Output logical value comparison circuit 24 Control circuit 25 Z-direction moving means 27 Y-direction moving means 29 X-direction moving means 31 computing means

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[Procedure amendment]

[Submission date] November 14, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

As shown in FIG. 11, a flip-flop 2 to be inspected is arranged in the central portion of a semiconductor chip 1, a peripheral circuit 3 is arranged around the flip-flop 2, and the flip-flop 2 has a D circuit. , T input terminal and Q output
The terminals are connected to the peripheral circuit 3, and the peripheral circuit 3 has a plurality of input terminals 4a, 4b, 4c, ..., 4k and output terminals 5a, 5
, b, 5c, ..., 5k.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

That is, as shown in FIG. 12, probe electrodes 6a, 6b, and 6b are provided on the wirings between the peripheral circuit 3 and the D input terminal, T input terminal, and Q output terminal of the flip-flop 2, respectively.
6c are brought into contact with each other, and the input signals of the D input terminal and the T input terminal of the flip-flop 2 from the peripheral circuit 3 are taken into the observation device (not shown) from the peripheral circuit 3 via the probe electrodes 6a and 6b. The output signal from the Q output terminal of 2 to the peripheral circuit 3 is taken in by the observation device,
It is determined whether the logical value of the output signal with respect to the input signal is normal or abnormal, and the operation timing of the flip-flop 2 is observed.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

By the way, when the probe electrodes 6a to 6c are brought into contact with the respective wirings as shown in FIG. 12, the wiring layer 9 laminated on the interlayer insulating film 8 on the semiconductor substrate 7 is conventionally formed as shown in FIG. A surface protective film on the wiring layer 9 so as to be exposed
An opening 11 is formed in 10 and the exposed wiring layer 9 is brought into contact with the probe electrodes 6a, 6b and 6c.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

FIG. 2 is a schematic view of a part of FIG.
In FIG. 1 and FIG. 2, while the probe electrode 21 held at the ground potential is in contact with the surface protection film on a predetermined signal wiring layer of the semiconductor chip 1, the input signal generation circuit 22 causes the D input of the flip-flop 2 to be input. An inspection input signal having a predetermined pattern is applied to the terminal, and the Q output signal of the flip-flop 2 in response to the input of the inspection input signal passes through the peripheral circuit 3.
It is input to the output logic value comparison circuit 23 Te, and the logical value and the normal logic value of the Q output signal by the output logic value comparison circuit 23
The comparison is performed indirectly, and the quality of the operation timing of the flip-flop 2 is evaluated based on the comparison result.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction content]

Further, the probe electrode 21 is connected from the layout information of the semiconductor chip 1 stored in the database 30.
The target contact position to be touched is calculated, and each moving means 25,
Since the probe electrode 21 is moved to the target contact position by 27 and 29, the probe electrode 21 can be accurately brought into contact with a predetermined position, and it is possible to deal with semiconductor chips having various patterns.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0033

[Correction method] Change

[Correction content]

As shown in FIGS. 8 and 9, the probe electrode 21 shown in FIG. 1 is brought into contact with the surface protective film on the signal wiring layer between the T input terminal of the flip-flop 2 and the driving element 3b of the peripheral circuit 3. The capacitor 33 is equivalently inserted between the signal line to the T input terminal and the ground .

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0034

[Correction method] Change

[Correction content]

Then, with the capacitor 33 being equivalently inserted by the contact of the probe electrode 21 as described above,
When an input signal for inspection having a predetermined pattern is given by the input signal generation circuit 22, the drive elements 3a and 3b of the peripheral circuit 3 are
10 (a) and 10 (b), the drive element 3b is driven at the timing shown by the solid line in FIG. 10 (b) unless the probe electrodes 21 are in contact with each other.
Of the output signal changes, the change timing of the output signal of the drive element 3b is delayed as shown by the broken line in FIG. 10B due to the increase of the load capacitance due to the contact of the probe electrode 21.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

Therefore, if the change timing of the signal to the D input terminal of the flip-flop 2 before contacting the probe electrode 21 does not satisfy the setup time with respect to the signal to the T input terminal, the flip-flop 2 becomes The output signal of the flip-flop 2 does not operate normally and does not have a normal logical value (“0” or “1”), and the contact of the probe electrode 21 delays the change timing of the signal to the D input terminal. As a result, if the flip-flop 2 operates normally and the output signal of the flip-flop 2 has a normal logical value, it means that the timing error of the T input of the flip-flop 2 has occurred.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be corrected] 0037

[Correction method] Change

[Correction content]

As described above , by bringing the probe electrode 21 into contact with the surface protection film on the signal wiring layer for the T input terminal of the flip-flop 2, the same effect as that of the previous embodiment can be obtained.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction content]

[0038]

As described above, according to the semiconductor evaluation apparatus of the present invention, the probe electrode at the ground potential is brought into contact with the surface protective film on the predetermined signal wiring layer of the semiconductor integrated logic circuit to bring the probe electrode into contact. Signal by capacitance
Since the output logic value comparison circuit compares whether or not the output logic value of the semiconductor integrated logic circuit becomes a normal logic value when the propagation is forcibly delayed, an opening is formed in the surface protection film as in the conventional case. Therefore, it is possible to easily and accurately evaluate the quality of the operation timing of the semiconductor integrated logic circuit, and it is possible to analyze at higher speed.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

FIG. 5 is an equivalent circuit diagram of FIG.

Claims (2)

[Claims] 1. A semiconductor evaluation device used for investigating the cause of a malfunction of a semiconductor integrated logic circuit, the probe electrode being held at a ground potential and being in contact with a surface protection film on a predetermined signal wiring layer of the semiconductor integrated logic circuit. An input signal generation circuit for providing a test input signal to the semiconductor integrated logic circuit when the probe electrodes are in contact, and a logic value of an output signal of the semiconductor integrated logic circuit is normal when the test input signal is input. A semiconductor evaluation device comprising: an output logical value comparison circuit that determines whether or not to perform a comparison; and a control circuit that controls operations of the input signal generation circuit and the output logical value comparison circuit. 2. The semiconductor evaluation device according to claim 1, wherein a target contact position of the probe electrode is calculated by a computing unit based on layout information of the semiconductor integrated logic circuit, and the probe electrode is held by a moving unit. A semiconductor evaluation device, wherein the probe electrode is moved to the target contact position calculated by a calculation means.