JPH0510991A - Digital signal processor - Google Patents

Abstract

PURPOSE:To realize analysis in an arbitrary band by converting an input analog signal to digital signal, eliminating the high frequency component in the signal converted to digital signal and decimating the data using a decimation filter provided with a sine interporation circuit. CONSTITUTION:A sine interporation circuit 30 has a decimator 31 for set values and a cut-off frequency variable filter 32. A decimation filter 20 thins out the data after A/D conversion at the rate of the power of 2 and has a function of cutting high frequency. The thinned data FDATA and a data clock FCLK are input to the decimator 31 for decimating according to the set value. In the filter 32, output data DCDATA further thinned by the decimator 31 are input and data limited by a set band are output. By providing a sine interporation circuit 30 including a simple data decimation circuit, the analysis in arbitrary band becomes possible without changing much of the hardware constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device, and more particularly to an FFT (Fast Fourier Transform) analyzer with improved degree of freedom in selecting an analysis frequency band.

[0002]

2. Description of the Related Art Digital signal processing measuring instruments (for example, F
As shown in FIG. 6, the FT analyzer) converts the input analog data into a digital signal by an oversampling A / D converter, cuts high frequency components by a filter 20, and thins out the data, and the DSP 40 makes an FFT. The analysis is performed and the analysis result is displayed on the display 50.

In a device for performing signal analysis using such an FFT, the filter 20 often thins out two because of the ease of hardware and software.

[0004]

If the filter is a decimation filter of 2 as described above, only the analysis can be performed in a band that is a power of 2 of the basic band, and if decimation increases, a fractional band frequency occurs. There is a problem. For example,
With the resolution shown on the upper side of FIG. 4, band division is poor, and it is difficult to recognize during analysis. The conventional technology cannot change the band even in such a case.

The present invention has been made in view of such a problem, and an object thereof is to enable analysis in an arbitrary band by using a configuration that is easy to realize and to provide a clear band. It is to realize the analysis.

[0006]

The present invention achieves the above object by providing a dedicated band changing circuit. The band changing circuit is a sine interpolation circuit (a circuit that selects an arbitrary frequency point in the Nyquist band), and this sine interpolation circuit is composed of a decimator and a cutoff frequency variable filter for performing simple decimation.

[0007]

[Action] Generally, the analysis frequency band K and the reference frequency band and S ^{is, K = S / 2 N ×} (2 M / L) = S / 2 N-M × (1 / L) ··· (1) Is expressed as In equation (1), the term S / 2 ^NM is 2
This represents thinning-out, and the 1 / L term represents an arbitrary setting term. Conventionally, only the term of decimation of 2 was used, but in the present invention, band adjustment is possible by an arbitrary setting term using sine interpolation. This allows analysis in any band.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a diagram showing the configuration of an embodiment of the FFT analyzer of the present invention. The feature of this embodiment is that a sine interpolation circuit 30 is added to the conventional example of FIG.

As shown in FIG. 2, the sine interpolation circuit 30 includes a decimator 31 for a set value and a variable cutoff frequency filter 32.
And have. The thinning filter 20 has a function of thinning out the data after A / D conversion with a power of 2 and cutting the high frequency band, and uses the same one as the conventional configuration. The data FDATA after the decimation of 2 and the data clock FCLK thereof are input to the decimation device 31 which performs decimation according to the set value. Variable filter 32 with variable cutoff frequency
The output data DCDATA further thinned out by the thinning-out device 31 of the set value is input to, and the data limited in the set band is output. As the variable filter 32, a general hardware or software filter can be used.

A more specific configuration of the setpoint decimation device 31 is shown in FIG. This decimator compares the register 33 for setting the decimating number, the counter 34 for counting the number of output data of the decimating filter 20 of 2 and both outputs (SETD, CNTD) of the register 33 and the counter 34 to detect the coincidence. Signal EQ
The comparator 35 that outputs U, the differentiator 36 that receives the coincidence detection signal EQU of the comparator 35 and creates the timing pulse DIFEQ, and the data FDATA is captured (sampled) at the input timing of the timing pulse DIFEQ, and the captured data is acquired. , And a register 37 for outputting as thinned data DCDATA.

The operation of the sine interpolation circuit 31 will be specifically described below. FIG. 4 shows an example of the analysis frequency band when the sine interpolation circuit 31 is used (lower figure) and when it is not (upper figure). In both cases, the thinning filter 20
It is used as a thinning filter of 2. In this case, the frequency resolution when using sine interpolation (lower side) is better than that when not using sine interpolation (upper side), and is suitable for analysis.

FIG. 5 is a timing chart showing the operation of the decimator 31 of FIG. 3 in the case where such a band analysis is realized (a sine interpolation circuit is used on the upper side in order to make a comparison with the conventional one. When the analysis is performed in a band close to the desired band (1/2 ³ decimation) without doing so, the clock timing is shown as proportional.

[0013] As described above, the analysis frequency band K and the reference frequency band and S ^{is, K = S / 2 N ×} (2 M / L) = S / 2 N-M × (1 / L) ··· It is expressed as (1). In equation (1), the term S / 2 ^NM is 2
This represents thinning-out, which corresponds to thinning-out by the thinning-out filter 20, the term of 1 / L represents an arbitrary setting term, and corresponds to thinning-out by the thinning-out device 31. In this case, since the thinning filter 20 has a wide band, the variable filter 32 accurately limits the band.

The decimation filter 20 sets the input data DATA to 1
FDATA is output by thinning out to / 2 ^N-M, and a clock FCLK having a frequency of 1/2 ^N-M of the input reference clock CLK is output. FDATA and FCLK are input to the decimator 31.

The set value of the register 33 is "4", the counter 34 counts the number of clocks FCLK, and outputs the count output CNTD. The counter 35 compares the set value SETD (= “4”) of the register 33 with the count output CNTD, and at the timing when SETD = CNTD, the match detection signal EQU.
Is output, and based on this, the differentiator 36 outputs the timing pulse DI
Create FEQ. Register 37 uses this timing pulse DI
Capture the input data FDATA at the FEQ input timing.
As a ^{result, 1 / (2 N-M} × L) in the decimated data DC
DATA (data A, F, K, P ...) Is output. The timing pulse DIFEQ also serves to reset the counter 34.

The analysis band K shown on the lower side of FIG. 4 is S = 200K.
In the case of Hz, it can be realized by setting N = 3, M = 2, L = 5, and the analysis band K is K = (200K / 8) × (4 /
5) = 25KHz x (4/5) = 100KHz x (1/5) = 20KH
It becomes z.

In this example, as in the conventional case, the thinning filter 20
Decimate 1/2 by 1 and 1 by decimator 31
By decimating / 5, the variable filter 32 limits the band to 20 KHz.

As described above, according to the present invention, by appropriately selecting the set value of the register 33 in the sine interpolation circuit 31 (or the number of bits of the counter 34, etc.), a thinning-out device having an optimum configuration can be constructed.

[0019]

As described above, according to the present invention, by providing a sine interpolation circuit including a simple data thinning circuit, it is possible to analyze in any band without significantly changing the hardware configuration. is there. This gives F
It is possible to improve the performance of a digital signal processing measuring device such as an FT analyzer.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment (FFT analyzer) of a digital signal processing device of the present invention.

FIG. 2 is a diagram for explaining a basic configuration of a sine interpolation circuit 30.

FIG. 3 is a diagram showing a specific configuration of a decimator 31 that constitutes a sine interpolation circuit 30.

[Fig. 4] When the sine interpolation circuit 31 is used (lower figure)
FIG. 4 is a diagram showing an example of an analysis frequency band in the case of not performing the above (upper diagram) in comparison.

5 is a timing chart showing the operation of the decimator 31 of FIG. 3 when realizing the band analysis as shown in FIG. 4 (in order to make a comparison with the conventional case, a sine interpolation circuit is provided on the upper side). In the case where analysis is performed in a band close to a desired band without being used (1/2 ³ thinning), clock timings are shown as proportional).

FIG. 6 is a diagram showing a general configuration of a digital signal processing measuring instrument (for example, an FFT analyzer).

[Explanation of symbols]

 10 A / D converter 20 Thinning filter 30 Sine interpolation circuit 40 DSP (FFT) 50 Display 31 Thinning machine 32 Variable filter 33 Register 34 Counter 35 Comparator 36 Differentiator 37 register

Claims (1)

Claim: What is claimed is: 1. An analog input signal is converted into a digital signal by an A / D converter, and this A / D signal is converted by using a filter.
A digital signal processing device for removing a high frequency component of a D-converted signal and thinning out data to perform digital signal processing, wherein the filter is a filter (20) for thinning out 2, The band changing circuit (30) is provided after the filter (20) that performs
Decimator (31) that decimates the set value for input data
And a variable filter (32) capable of changing the cut-off frequency. The thinning-out device (31) for thinning out the set value is a register (33) for storing the set value, and the thinning-out device 2 described above. Counter (34) that counts the number of output data of the filter that performs the above, the count value of this counter (34) and the register (33)
The comparator (35) that compares the set value stored in the memory with the set value stored in the memory, and the latch circuit (37) that captures the output data of the filter (20) that performs the thinning out of 2 at the matching detection timing. A digital signal processing device comprising: