JPH05109912A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten access time and prevent malfunction of a device by forming a taper on the side of arrayed wiring such as bit line and word line. CONSTITUTION:The wiring 1 of an integrated circuit is provided with a taper. The width of the bottom of the wiring 1 is approximately 10mum and the angle of the taper is 40 deg.-50 deg.. A parasitic capacity 2 is generated between the wiring 1 and the wiring 1. When the taper is formed at the side of the wiring 1, the parasitic capacity 2 generated between the wiring 1 and wiring 1 is reduced. Thus, the sense margin of the integrated circuit is increased, and not only sense speed is increased but also malfunctions are prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a bit line (hereinafter referred to as BL, such as DRAM).
,) And word lines (hereinafter referred to as WL) in shape.

[0002]

2. Description of the Related Art FIG. 8 is a wiring diagram of an array of a conventional semiconductor integrated circuit device. In the figure, reference numeral 1 is a wiring formed of, for example, polysilicon, and its width and height are, for example, 1.
0 μm and 0.5 μm. 2 is a line capacitance between wirings, and its value is, for example, 15 fF. FIG. 9 is a sectional view of this conventional array wiring. The conventional BL and WL are shaped such that the side surfaces of adjacent wirings run in parallel and face each other (see FIGS. 8 and 9). For this reason, in the conventional technique, the parasitic capacitance is likely to be parasitic between the lines of adjacent BL and WL (see FIGS. 8 and 9).

[0003]

B of the conventional DRAM etc.
Since L and WL are configured as described above, parasitic capacitance is liable to be generated between the lines, an access time is delayed, and when the level of one wiring is changed, the parasitic capacitance is changed. Becomes a coupling capacitance, which affects the wiring running on the side surface of the device, causing the device to malfunction.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor integrated circuit device capable of speeding up the access time and preventing malfunction of the device. And

[0005]

A semiconductor integrated circuit device according to the present invention includes a bit line and a word line (hereinafter, BL, WL).
(Referred to as)) and the like are formed by forming a taper on the side surface of the wiring arranged in an array.

[0006]

In the semiconductor integrated circuit device according to the present invention, the line capacitance can be reduced by forming the taper on the side surface of the wiring.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an array wiring diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. In the figure, reference numeral 1 denotes a wiring having a tapered side surface, the width of the wiring bottom is, for example, 1.0 μm, and the taper angle is, for example, 40 to 50 °. 2 is a parasitic capacitance between the wirings. FIG. 2 is a sectional view of the array wiring shown in FIG.

Next, the operation of the embodiment of the present invention when applied to the BL of DRAM will be described. FIG. 3 shows a memory cell. Reference numeral 3 indicates a BL capacitance C _B , 4 indicates a memory cell capacitance C _S , and 5 indicates BL.

FIG. 4 is a sectional view of BL, showing the capacitance C of BL.
_It represents the contents of _B. Reference numeral 6 represents a line capacitance C ₁ between BLs, 7 represents a parasitic capacitance C ₂ between the BL and the upper wiring, and 8 represents a parasitic capacitance C ₃ between the BL and the substrate. C _B = C ₁ + C ₂ + C ₃

C ₁ is, for example, 15 fF, C ₂ is about 10 to ₃₀ fF, and C ₃ is, for example, 10 fF. The value of C _{2 has} a range because the current LSI is a multi-layered wiring, and a plurality of wirings run in the upper and lower portions, and the capacitance for each one varies.

FIG. 5 shows the movement of BL during sensing of a DRAM having a normal wiring shape. Reference numeral 12 indicates the level ΔV at which BL varies with C _s after the memory cell is selected. Reference numeral 13 indicates a time t _{S at} which the 12 levels are amplified by the sense amplifier. ΔV, t _S is, for example, 2
It is 00 mV and 5 nS.

FIG. 6 shows the movement of the BL when the present invention is applied. It can be seen that ΔV is larger than that in FIG. This is because by tapering BL, C ₁ is lowered, and as a result, C _B is surely decreased, and ΔV is certainly increased.

As a result, the sense margin is increased, and the sensitivity of the sense amplifier can be reduced. As a result, the sense speed is increased and the device speed is increased.

Next, the effect of the embodiment when the present invention is applied to the WL of DRAM will be described.

FIG. 7 shows an array portion of memory cells of DRAM. 21 is a selected WL, 22 is a selected memory cell,
23 and 24 are unselected WLs, 25 and 26 are unselected memory cells, 27 and 28 are line capacitances, 29 is BL, and 30 is / BL.
Indicates. When WL is tapered and the line capacitance is reduced, the selected WL21 is activated, and when the selected memory cell 22 is selected, the line capacitances 27 and 28 become decoupling capacitances and the non-selected WLs 23 and 24 are activated. It is possible to prevent the non-selected memory cells 25 and 26 from being erroneously selected.

At the same time, as another effect, the transistor length of the transfer gate of the memory cell can be shortened to shorten the transfer time between the memory cell and BL, and as a result, the speed of the device can be increased.

Further, although BL and WL of the DRAM are described in the present invention, similar effects can be obtained also in other integrated circuits in a place where parasitic capacitance between wirings becomes a problem.

[0018]

As described above, according to the semiconductor integrated circuit device of the present invention, since the taper is formed on the side surface of the wiring at the required location, by applying it to the WL and BL of the DRAM or the like, It is possible to obtain the effect of speeding up the device or suppressing malfunction.

[Brief description of drawings]

FIG. 1 is a wiring diagram of an array to which an embodiment of the present invention is applied.

FIG. 2 is a sectional view of array wiring to which an embodiment of the present invention is applied.

FIG. 3 is an equivalent circuit diagram of a memory cell.

FIG. 4 is a cross-sectional view showing a parasitic capacitance of BL.

FIG. 5 is a diagram showing a movement of BL when a DRAM is selected.

FIG. 6B at the time of selecting a DRAM when the present invention is applied
It is a figure which shows the movement of L.

FIG. 7 is an equivalent circuit diagram of a memory cell array.

FIG. 8 is a conventional array wiring diagram.

FIG. 9 is a cross-sectional view of a conventional array wiring.

[Explanation of symbols]

 1 wiring 2 parasitic capacitance

Claims (1)

[Claims] 1. The semiconductor integrated circuit device according to claim 1, wherein the wiring at a required position has a wiring shape having a taper on a side surface thereof.