JPH05109843A - Device for reducing landing error of primary electron in electron beam tester - Google Patents

Abstract

PURPOSE:To reduce the landing error which is caused by a primary electron beam being bent by the ripple of the potential in the space on a sample, in electron beam testing. CONSTITUTION:This is one where the chip is covered with a metallic foil or a metallic plate 6 provided with an opening, excluding the section where primary electrons reach the pattern or its vicinity. Hereby, the potential distribution in the space on a chip becomes approximately parallel with the chip, and the electron beam 4 reach the objective position on the pattern accurately without being bent, and the landing error can be removed. Moreover, the metallic foil 6 is constituted of two sheets of L-shaped parts, and the aperture area can be changed by shifting it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a primary electron landing error reducing device in an electron beam testing device.

[0002]

2. Description of the Related Art A strobe S is used for electron beam testing.
EM (scanning electron microscope) includes potential contrast image observation and voltage waveform measurement by non-contact probing.
In image observation as a normal SEM, the landing point of primary electrons is affected by an electric field or a magnetic field. However, in the case of a constant electric field or magnetic field, if the amount is sufficiently small, the correction can be made and there is almost no problem. LSI (Large scale integrated circuit)
When the potential of the sample changes, such as when observing an image during operation, the trajectories of the primary electrons are bent under the influence of the potential change on the sample surface, and the potential changes with time. May not be uniformly determined. This is called a primary electron landing error.

In the case of an LSI, the pattern potential inside the chip has an inversion potential (H / L), and the electric field created by the pattern affects only a small area on the upper surface of the sample in many cases. However, when the area is large, such as the bonding pad, which is far from the probing point, the electric field created affects the orbits of the primary electrons in a region of a few millimeters. The influence of a lateral electric field having a constant electric field strength on the electron orbit increases in proportion to almost the square of the time taken for the primary electrons to pass through the electric field. That is, even if it is far from the probing point, the primary electrons are greatly affected by the electric field due to the biased potential distribution over a large area. Further, even in the case of a logic circuit, if the potential distribution inside the chip changes at one time, its influence becomes large.

Referring to FIG. 1, which shows a top view of an LSI,
The bonding pad (2) provided on the chip (1) and the external terminal are connected by a bonding wire (3). Referring to FIG. 2, for example, 5V is applied to the left bonding pad and 0V is applied to the right bonding pad, the pattern of the chip is irradiated with an electron beam (4), and the pattern is inspected by secondary electrons emitted therefrom. In doing so, the potential distribution (5) is formed as shown by the fluctuation of the internal potential due to the test signal input to the pattern and the input / output. Therefore, the primary electrons are bent by the electric field created by this potential distribution and cannot reach the target position accurately. For this reason, the occurrence of landing error of primary electrons is unavoidable.

Moreover, at some point, 0 V is applied to the left bonding pad and 5 V is applied to the right bonding pad, so that the electron beam sways left and right, and it is difficult to improve landing accuracy. In recent years, as the integration of LSIs has increased, the patterns have become finer and finer, so even a slight bending of the electron beam results in a large measurement error, and the primary electron landing error becomes an even greater problem. There is.

Conventionally, as a method of correcting the primary electron landing error, (1) the LSM (Logic St
ate Mapping) A method of adding correction signals created from images,
(2) Method of placing the extraction electrode near the sample surface, (3)
Method of placing strong extraction electric field near the sample surface, (4) L
When the SI is manufactured, the chip surface is masked in advance,
There is a method of diagnosing a failure location from outside of the package by some method (X-ray etc.), making a hole at the location and exposing the chip surface to inspect.

The method (1) includes a strobe method in which a pulse beam synchronized with a trigger signal is generated to obtain an image, and an LSM method in which the strobe method is obtained by shifting the phase in a certain vertical section of the frame. .. With these methods, correction by image recognition is possible, but since correction signals are created and then processed, real-time correction is impossible. Also SEM
In the case of image observation as above, it is impossible unless the frame scan coil operates at a high speed of about the trigger frequency (the frequency of the correction signal is sufficiently low in the strobe method and the LSM method).

In the method (2), the setting range of the working distance (distance from the lower surface of the pole piece of the objective lens of the scanning electron microscope to the sample position) becomes small, which makes it difficult to set the LSI. If the working distance becomes long due to the measurement, the primary electrons are affected and the effect is reduced. In the method of (3), in addition to the problem of (2) above, there is a case where an adverse effect on the surface of the sample, such as perivation, occurs.

Further, in (4), it is necessary to process the sample in advance, and it cannot be applied to a general LSI.

[0010]

SUMMARY OF THE INVENTION It is therefore an object of the present invention, with a simple structure, to reduce the landing error caused by the bending of the primary electron beam due to the fluctuation of the potential in the space above the sample.

[0011]

Therefore, according to the present invention, a metal foil having an opening (a material for shielding an electric field, such as a conductive plate, a net, etc., except for a portion where a primary electron reaches a pattern and the vicinity thereof) is provided. It becomes possible to make the potential distribution generated in the space above the sample close to parallel to the sample by covering the chip with (including). As a result, the electric field component orthogonal to the traveling direction of the electron beam is extremely reduced, and the electron beam can accurately reach the target position on the sample without being bent.

Further, according to the present invention, by changing the opening area of the metal foil, it is possible to suppress the fluctuation of the potential distribution which affects the electron beam with the necessary minimum opening.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The parts common to the present invention and the prior art are designated by the same reference numerals. In FIGS. 3 and 4, the present invention provides a metal foil (6) having an opening (7) in parallel with the chip and covering the chip with the metal foil (6) except for a portion to be tested of a pattern and its vicinity. Is. As a result, the potential distribution formed in the space on the chip becomes parallel to the chip, and the electric field component in the direction orthogonal to the traveling direction of the electron beam almost disappears. Therefore, the electron beam can accurately reach the target position on the chip without being bent, and the landing error is greatly improved.

On the upper side of the metal foil, the opening (7) of the metal foil (6) is necessary in order to reduce the influence of the electric field due to the voltage applied to the chip (1) or the bonding pad (2) on the electron beam. It should be minimal. For that purpose, it is possible to use a metal foil (6) having a different opening (7) area depending on the size of the chip to be tested and the type of pattern, but it is desirable to make the opening (7) area variable. ..

When measuring a fine pattern, the SEM image is enlarged. For example, when measuring a pattern potential having a width of 1 μm, the range of the image is 10 times the width of the pattern, 10 μm × 1.
It may be about 0 μm. Therefore, if the portion outside this range is covered with metal foil, the potential distribution (H /
Even if L) changes, it is hardly affected. Therefore, according to the present invention, as shown in FIG. 5, two L-shaped metal foils are used in combination, and the opening area can be increased or decreased by moving in the direction of the arrow. I am doing it.

Of course, instead of these two L-shaped metal foils, for example, a camera diaphragm structure can be used. It is desirable that the metal foil (6) be arranged close to the chip, and if the metal foil (6) can be moved relative to the chip in the height direction or the lateral direction, the measuring range is limited. It is possible to reduce the landing error without doing so.

[0017]

According to the present invention, by providing a metal foil on the upper surface of the sample and keeping it at a constant potential, the section given to the primary electron trajectory of the surface potential of the sample can be shortened, and the primary electron landing error can be significantly reduced. Further, by making it possible to change the opening area formed by the metal foil or changing the relative position with respect to the chip, the landing error can be reduced without limiting the measurement range. Furthermore,
End face of chip (may include bonding pad)
By covering only the outer side, the entire chip image can be seen in the SEM image observation.

[Brief description of drawings]

FIG. 1 is a top view of an LSI.

FIG. 2 is a diagram for explaining potential distribution and bending of an electron beam in conventional EB testing.

FIG. 3 is a top view in which the metal foil of the present invention is arranged on an LSI.

FIG. 4 is a diagram showing a potential distribution and a bending of an electron beam when a metal foil of the present invention is arranged on an LSI.

5A and 5B are configuration diagrams for making the opening variable in the metal foil of the present invention, in which FIG. 5A is an enlarged view and FIG. 5B is a narrowed view.

[Explanation of symbols]

 1 Chip 2 Bonding Pad 3 Bonding Wire 4 Electron Beam 5 Potential Distribution 6 Metal Foil or Metal Plate 7 Opening

Claims (3)

[Claims] 1. In an electron beam testing apparatus,
A primary-electron landing error reduction device, characterized in that a metal foil having an opening is provided above the sample. 2. The primary electron landing error reduction device according to claim 1, wherein the opening area of the metal foil is variable. 3. The primary electron landing error reduction device according to claim 1, wherein the position of the metal foil is variable relative to the sample.