JPH05109641A - Ion-implantation method - Google Patents

Abstract

PURPOSE:To enable ion implantation to be made without any need for a troublesome maintenance and causing reverse electrification by providing a conductive channel for dissipating electric charge at a scribe region of a semiconductor substrate and performing ion implantation by connecting it to a ground potential. CONSTITUTION:A poly Si layer where impurities are doped is deposited on a surface of a wafer 3, a poly Si layer which is 10-20 mum wide is left at a center of a scribe region between chips 1 by photolithography, and then the rest is eliminated by etching. An obtained lattice-shaped poly Si layer becomes 2 discharge channel 2. The poly Si discharge channel 2 is higher than the chip region 1. When this wafer 3 is fitted to a substrate-retention device of an ion- implantation device, the discharge channel 2 contacts a metal of a tool for fixing; the wafer 3 and the discharge channel is connected to a ground potential, thus enabling an electric charge which is on the wafer surface by ion implantation to be discharged and hence electrostatic breakdown due to accumulation of electric charge to be avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ion implantation method, and more particularly to a technique for preventing electrostatic breakdown when performing ion implantation on a substrate covered with an insulating material.

Utilization of an ion implantation method for manufacturing a semiconductor device has become a normal condition today, and the implantation device is being improved in the direction of increasing the current and expanding the implantation area. Since a large amount of charges are sent to the substrate to be injected in a short time in the high current injection, if the discharge capability of the substrate is low, the retention time and accumulated amount of the charges are increased, and troubles such as dielectric breakdown easily occur.

Ion implantation is carried out at various stages in the process of manufacturing a semiconductor device. However, if element formation progresses to a certain degree, conductors and insulators will be intricately present on the substrate surface. The dielectric strength against the electrostatic field generated by the ion implantation becomes non-uniform, and the breakdown voltage becomes lower than that in the case where the charges are evenly distributed.

Further, when an insulator such as a resist pattern is used as a mask in the selective ion implantation, the electric charge accumulated in the resist causes polarization of the electric charge of the conductor, and an electrostatic field is generated in a portion beyond the ion implantation depth. May occur.

For example, in the case of a MOS type integrated circuit (IC),
When the gate electrode is formed but is not connected and is electrically floating, dielectric breakdown of the gate oxide film is likely to occur, and also dielectric breakdown is likely to occur at the boundary between the S / D region and the field oxide film. . It is considered that these phenomena occur because the injected charges are concentrated in a specific place.

Under these circumstances, one technical problem is how to reduce the accumulation of electric charges when performing ion implantation.

[0007]

2. Description of the Related Art One of the techniques for eliminating static charge in ion implantation is to use an electron shower. In this method, since the implanted ions have a positive charge, electron beam irradiation is performed at the same time as the ion irradiation to neutralize the ion beam and inject it into the substrate.

[0008]

The electron shower neutralization method has a drawback in that the apparatus is complicated and the maintenance time of the injection apparatus is long, so that the operating rate of the injection apparatus cannot be increased. In addition, it is difficult to control the shower current for neutralization, and a problem of so-called reverse charging, in which the electron shower is too strong and the substrate is negatively charged, newly occurs.

An object of the present invention is to provide an ion implantation method in which maintenance is not troublesome and the problem of reverse charging does not occur.

[0010]

In order to achieve the above object, according to the ion implantation method of the present invention, when ion implantation is performed on a semiconductor substrate in which a plurality of chip regions are arranged, scribes provided between the chip regions are provided. A band-shaped conductor is deposited on the region, the conductor is held in a state of being electrically connected to the substrate holding device of the ion implantation apparatus, and ions are irradiated.

Further, in a preferred embodiment of the present invention, the strip conductor provided in the scribe region is formed of a poly-Si layer having a high impurity concentration.

[0012]

[Function] In the ion implantation apparatus currently in practical use,
As shown in FIG. 2, the irradiation area (beam spot 4) of the ion beam is as wide as 4 to 5 cm square, and several tens of IC chips of normal size are implanted at one time. When the charged beam is irradiated to such a wide area at once, not only the diffusion of the charges generated on the insulator is delayed, but also the charges move to the adjacent chip to cause electrostatic breakdown in a specific chip. It will also happen.

Explaining in more detail, due to a slight non-uniformity of the condition of element formation, there is a slight difference in the easiness of accumulating charges in each chip, and the easiness of accumulating due to the movement of charges from an adjacent chip. The concentration of electric charges on the chip facilitates electrostatic breakdown. That is, even if the current densities are the same, the electrostatic withstand voltage is more likely to decrease when a thick ion beam is used rather than a thin ion beam.

As described above, the generated electrostatic field has a higher voltage as the ion current is larger. However, if the dissipation of the charge is rapid, it will not be so high. Therefore, if a conductive path is provided around the chip region and is connected to the ground potential as in the present invention, the injected charge is scribed. Not only will it not move across the area, but the tendency of the charge sent into each chip area to dissipate will be prioritized over the tendency to concentrate, and the concentration of charge that will cause a high-voltage electrostatic field will also be suppressed. .

[0015]

EXAMPLE A poly-Si layer doped with impurities is deposited to a thickness of about 3 μm by the CVD method on the surface of a wafer which has been processed up to the stage of performing ion implantation. By a normal photolithography process, a poly-Si layer having a width of 10 to 20 μm is left in the center of the scribe region between the chips, and the others are removed by etching. This state is schematically shown in FIG. In the figure, (a) is a plan view and (b) is a sectional view. The lattice-shaped poly-Si layer is the discharge path 2, 1 is a chip region, and 3 is a wafer.

As can be seen from FIG. 1B, the poly-Si discharge path is formed so as to be higher than the chip area. When this wafer is mounted on the substrate holding device of the ion implantation apparatus, the discharge path is used for fixing the wafer. It will come into contact with the jig. Since this kind of jig is usually made of metal, the discharge path is connected to the ground potential, and the charges generated on the wafer surface by the ion implantation are discharged as shown by the arrow.

Irregularities are generated on the surface of the wafer after the wafer process has progressed to some extent, and the chip area is usually slightly higher than the scribe area. As described above, if the thickness of the poly-Si layer is 3 μm, the upper surface of the discharge path formed in the scribe area is higher than the chip area, and the discharge path can be grounded only by mounting it on the substrate holding device. become.

This poly-Si discharge path is usually removed in a subsequent step, but it may be left. Also,
It may be formed of a metal such as Al instead of poly. Al
In many cases, the film is formed by vapor deposition. At this time, if it is set so as to wrap around the back surface of the wafer and leave it when patterning the discharge path, it can be grounded simply by mounting it on a holding device. The simplicity of potentials remains.

[0019]

As described above, if a conductive path for dissipating charges is provided in the scribe region of the semiconductor substrate and this is connected to a stable potential such as ground potential for ion implantation, the charge retention on the surface of the substrate will be reduced. It is significantly reduced, and electrostatic breakdown due to charge accumulation can be avoided. As a result, not only the manufacturing yield is improved, but also a high current implanter can be used, and the throughput of the ion implantation process is also improved.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a beam spot and a chip area.

[Explanation of symbols]

 1 chip area 2 discharge path 3 wafer 4 beam spot

Claims (2)

[Claims] 1. When a semiconductor substrate (3) having a plurality of chip regions (1) arranged therein is ion-implanted, a band-shaped conductor (2) is formed on a scribe region provided between the chip regions. And irradiating the ion beam with the conductor electrically connected to the substrate holding device of the ion implantation device. 2. The ion implantation method according to claim 1, wherein the strip-shaped conductor provided in the scribe region is made of a polycrystalline silicon layer having a high impurity concentration.