JPH05108483A - Cache circuit - Google Patents

Abstract

PURPOSE:To lower busy-rate when read-accesses to the same address converge by reducing the number of requests actually outputted to the bus. CONSTITUTION:When a processor 101 could not acquire a bus use right a command decoder circuit 117 monitors the state of a command bus 103 when its own read-request is pending. If it is recognized to be the read-request outputted by other processor 102, an address comparator 116 compares the content of an another system request-address register 115 with that of the request address register 112. If coincidence is found by the address comparison, the processor 101 stores the data in its own reading data register 114, reading operation thus completes. At this time, an arbitration circuit 118 rejects a bus use right request.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache circuit, and more particularly to a cache read operation control circuit in a bus coupled multiprocessor system.

[0002]

2. Description of the Related Art A conventional cache circuit is shown in FIG.
As shown in FIG.
3, read / write access of data to the memory 107 is performed using the address bus 104 and the data bus 105. Similarly, the processor 102 also has buses 103 to 105.
The memory 107 is accessed via the via. Processor 1
Although 01 and 102 do not have to have the same configuration, it is assumed that the processors 101 and 102 have the same configuration in the following description.

Now, when the processors 101 and 102 output a data read request, the arbitration circuit 118 first outputs a bus use right request to the arbitration bus 106. Figure 2
In the above configuration, the distributed arbitration method is taken as an example, but the central arbitration method may be used here.

The arbitration circuit 118 of each processor determines the usage right according to the contents of the arbitration bus 106, and the processor that has acquired the bus usage right changes the contents of the request command register (RCR) 111 and the request address register (RAR) 112. Memory 1 that outputs to command bus 103 and address bus 104, respectively, and receives it
07 outputs the response data to the data bus 105.

Further, the processor which has acquired the right to use the bus first arbitrates for the next bus cycle after lowering the request for the right to use, and the processor which newly acquired the right to use the bus 103 to 105 Data is transferred within a range in which the use timings do not overlap.

[0006]

In this conventional cache circuit, when the read request of the self processor is waiting for the acquisition of the bus use right, the response data according to the read request of the other processor is transferred on the bus. , Even if the transfer data matches with its own read request address,
It cannot be taken in as read data of its own processor.

Therefore, in a multiprocessor system, when broadcasting between processors is performed,
When multiple processors try to perform read access to the same data at the same time, bus contention occurs. Further, there is a problem in that the data transfer on the bus is performed by the number of processors, and the busy period of the bus increases.

[0008]

In the cache circuit according to the present invention, a circuit for decoding a read request output from another processor on the shared bus while the read request of the own processor is suspended, and a cache circuit of the own processor A circuit for comparing the read request address with the request address on the shared bus is provided, and when the read request addresses of the two match, control for fetching response data to another processor is performed.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a more detailed description will be given with reference to the drawings showing an embodiment of the present invention.

Referring to FIG. 1, in one embodiment of the present invention, processors 101 and 102 are connected to memory 107 by a shared bus of command bus 103, address bus 104, data bus 105 and arbitration bus 106. That is, it has a multiprocessor configuration.

Now, it is assumed that the processors 101 and 102 are about to output a data read request to the bus at the same timing. As in the case of the conventional example described with reference to FIG. 2, the arbitration circuit 118 arbitrates the usage right among a plurality of processors using the arbitration bus 106.

Assume that the processor 102 has acquired the bus use right as a result of the arbitration of the bus use right in the processors 101 and 102. The contents of the request command register (RCR) 121 and the request address register (RAR) 122 are respectively the command bus 10
3 and the address bus 104, and the memory 107 receiving the data returns response data to the data bus 105. A simple example of this timing relationship is shown in FIG. Reference numeral 301 shows the timing of the arbitration bus, 302 shows the timing of the command bus and address bus, and 303 shows the timing of the data bus.

In the bus cycle, arbitration is performed at timing 311, command and address transfer is performed at timing 312, and data transfer from the memory is performed at timing 313. The data put on the data bus 105 is stored in the read data register (RD) of the processor 102.
R) 124, the data read operation is completed.

Next, the operation of the processor 101 which cannot acquire the bus use right will be described. The processor 101 is
When its own read request is suspended, the state of the command bus 103 is monitored by the command decoder circuit 117, and this is monitored by another processor (processor 10 in FIG. 1).
When recognizing the read request output by 2), the contents of the other system request address register (other system RAR) 115 that fetches the information of the address bus and the request address register that holds the address of its own read request (RAR) 112 and address comparator 1
Compare with 16.

These operations are performed at timing 312. If the result of this address comparison does not match, the processor 1 is executed in the bus cycle following the bus cycle.
Arbitration of the read request of 01 is executed again. This operation is the same as in the conventional example.

If the results of the address comparisons match, the data to be fetched by the read request of the processor 101 is response data to the read request of the processor 102, and at timing 313, the data is transferred from the memory 107 to the processor 102 on the data bus 105. Since it is transferred, the processor 101 stores the data in its own read data register 114 at timing 313 and completes the read operation. At that point, the arbitration circuit 118 withdraws the bus right request.

[0017]

As described above, according to the present invention,
The read request address held by the local processor is compared with the read request address of another processor on the shared bus. If the two match, the response data to the request from the other processor on the latter is fetched into the local processor and is held. When read accesses to the same address are concentrated, such as during broadcast communication in a multiprocessor system, the number of requests actually output to the bus is reduced and the bus busy rate is reduced by completing the above requests. You can

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

FIG. 3 is a timing chart showing bus timing in the embodiment shown in FIG.

[Explanation of symbols]

101, 102 Processor 103 Command Bus 104 Address Bus 105 Data Bus 106 Arbitration Bus 107 Memory 111, 121 Request Command Register (RC
R) 112, 122 Request address register (RA
R) 113 write data register (WDR) 114, 124 read data register (RDR) 115 other system request address register (other system RA
R) 116 address comparator 117 command decoder 118 arbitration circuit

Claims (3)

[Claims] 1. In a cache circuit of a processor of a multiprocessor system in which a plurality of processors are connected to a shared memory via a bus, the output of another processor is output on the shared bus in a state where a read request of the own processor is suspended. A circuit that decodes the read request that has been made and a circuit that compares the read request address of its own processor with the request address on the shared bus, and if both read request addresses match, control that fetches response data to another processor A cache circuit characterized by performing. 2. A cache circuit of a processor of a multiprocessor system in which a plurality of processors are connected to a shared memory via a bus, wherein the bus has a command bus, an address bus, a data bus, and an arbitration bus. Each of the processors decodes a read request output from another processor on the bus while the request command register, the request address register, the write data register, the read data register, the arbitration circuit, and the read request of its own processor are held. A command decoder circuit for controlling the read request address of its own processor and an address comparator for comparing the request address on the shared bus with the address comparator, and the arbitration circuit uses the arbitration bus to control the usage right between the plurality of processors. Mediation of In the processor that could not be won the right to use,
When the command decoder circuit monitors the status of the command bus and determines that the read request is output from another processor, the address comparator compares the addresses. If the addresses match in the address comparison, the read data is read. A cache circuit characterized by storing data in a register. 3. In the processor which has acquired the bus use right by the arbitration, the contents of the request command register and the request address register are output to the command bus and the address bus, and the shared memory receiving them outputs the data bus. 3. The cache circuit according to claim 2, wherein the response data is returned to the cache circuit.