JPH0510408Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a circuit that limits an input signal whose amplitude varies to a predetermined amplitude. In particular, the present invention relates to an amplitude limiting circuit having means for suppressing the amount of phase fluctuation.

〔overview〕

This invention uses two sets of transistor circuits to limit the amplitude on both the positive and negative sides in an amplitude limiting circuit that maintains the output signal at a constant value regardless of amplitude fluctuations in the input signal, resulting in less waveform distortion over a wide frequency range. This makes it possible to obtain an output signal with good phase characteristics.

[Conventional technology]

The conventional amplitude limiting circuit is as shown in FIG.
It was a current switching type configuration that utilized the amplitude limiting characteristics of the transistor's saturation region and cutoff region.

[Problem that the invention attempts to solve]

However, in such a conventional amplitude limiting circuit,
Due to the accumulation effect of fractional carriers in the saturation region of the transistor, the speed of transition from the saturation region to the cutoff region cannot be ignored when the frequency of the input signal is high, on the order of several hundred MHz, which has the disadvantage of causing waveform distortion.

Furthermore, since the accumulation time of the fractional carrier changes with fluctuations in the amplitude of the input signal, the output of the amplitude limiting circuit causes phase fluctuations that depend on the input amplitude. There was a drawback that phase characteristics could not be obtained.

The present invention eliminates these drawbacks,
It is an object of the present invention to provide an amplitude limiting circuit that can provide an output with little waveform distortion and little phase fluctuation even if the frequency of an input signal is high.

[Means for solving problems]

The present invention provides a first grounded collector type amplifier including a first transistor whose operating region for a positive amplitude of an input signal is an active region, and whose operating region for a negative amplitude of the input signal is a cutoff region;
a negative phase output type linear amplifier including a second transistor having a control electrode connected to the output of the first collector grounded type amplifier; a control electrode connected to the output of the negative phase output type linear amplifier via a capacitor;
a second grounded collector amplifier including a third transistor whose operating region for the positive amplitude of the signal related to the output is an active region and whose operating region for the negative amplitude of the signal is a cutoff region; It is characterized by

[Effect]

The amplitude of the signal is limited by using the cutoff characteristics of the transistor. This eliminates the influence of the accumulation time of the decimal carrier. Further, the limit amounts of the positive amplitude and the negative amplitude are changed and the amount of phase change is adjusted.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit connection diagram showing the configuration of a circuit according to an embodiment of the present invention. The first transistor 5 includes bias resistors 3 and 4 and an emitter resistor 6 to form a common collector amplifier. Here, transistor 5 operates in the active region of the transistor for the positive amplitude of waveform 20, and when a certain level on the negative side of waveform 20 is reached, transistor 5 is biased to be cut off. . Therefore, a waveform 21 whose amplitude is limited below a certain level on the negative side of the waveform 20 is obtained. Continuing, the second transistor 7 constitutes a grounded emitter amplifier with an emitter resistor 8 and a load resistor 10, and has a waveform 2.
2 is output from the collector. Here, a waveform 22 having an opposite phase to the waveform 21 of the transistor 7 can be obtained. A third transistor 13 that operates in the same way as the first transistor 5 is connected in cascade via a capacitor 9, and a fourth transistor 15 is connected in a linear narrow band so that the gain reaches its maximum value at the input signal frequency. It constitutes an amplifier circuit and is DC-coupled with the third transistor 13. The output signal of this transistor 15 is outputted via a capacitor 18 to obtain a waveform 24.

Now, if the amount of amplitude restriction performed by the first transistor 5 and the third transistor 13 is adjusted for each transistor, the waveforms 21 and 23 will fluctuate up and down with respect to the data fluctuation and the reference potential.
This variation appears as a phase change. Therefore,
This variation is intentionally created by bias adjustment of transistor 5 and transistor 13 to adjust the amount of phase variation. Subsequently, by passing through a linear narrowband amplifier circuit having a maximum gain at the input signal frequency, phase fluctuations due to waveform distortion are eliminated and the amount of phase fluctuation can be easily adjusted.

[Effect of idea]

As explained above, the present invention limits the amplitude based on the cutoff characteristics of the transistor, and therefore has the effect of reducing the influence of the accumulation time of fractional carriers. Furthermore, since the amount of restriction of the signal amplitude due to the cutoff characteristics is variable, there is an effect that the amount of phase change can be adjusted.

[Brief explanation of drawings]

FIG. 1 is a circuit connection diagram and waveform diagram of each part showing the configuration of a circuit according to an embodiment of the present invention. FIG. 2 is a circuit connection diagram showing the configuration of a conventional circuit. 1, 25...input terminal, 2, 9, 18, 26...
...Capacitor, 3, 4, 11, 12, 27, 28
...Bias resistance, 5, 7, 13, 15, 29,
32...Transistor, 6, 8, 14, 16, 3
3... Emitter resistance, 10, 30, 31... Load resistance, 17... Tuning circuit, 19, 34... Output terminal, V _cc ... Power supply voltage, V _ref ... Reference voltage.

Claims (1)

[Claims for Utility Model Registration] A first collector contact including a first transistor whose operating region for the positive amplitude of an input signal is an active region and whose operating region for the negative amplitude of the input signal is a cutoff region. a topography amplifier; a second transistor with a control electrode connected to the output of the first collector-grounded topography amplifier; a second collector grounded-plane amplifier including a third transistor connected to the output transistor, the operating region for the positive amplitude of the signal related to the output being an active region, and the operating region for the negative amplitude of the signal being a cutoff region; An amplitude limiting circuit comprising: