JPH05103328A - Satellite broadcast receiving system - Google Patents

Abstract

PURPOSE:To prevent sound signals resulting from a TV-side bit stream from being outputted to a VTR by switching the sound signals by using a control signal indicating the presence of scramble and another control signal which is delayed by a prescribed period of time from the control signal indicating the presence of scramble. CONSTITUTION:A switch SW1 which supplies TV- and VTR-side bit streams to a scramble decoder 5 by switching them to each other is provided. In addition, another switch SW2 which switches VTR-side analog sound signals and the analog sound signals of the decoder 5 to each other is also proved. Then a control signal S1 indicating the presence of scramble discriminated on the VTR side and another control signal S2 which is delayed by a prescribed period of time from the signal S1 is generated. As a result, the occurrence of mismatching in switching timing between the switches SW1 and SW2 can be eliminated by inputting the VTR-side bit stream to the decoder 5 by switching the switch SW1 to the VTR-side bit stream with the control signal S1 and switching the switch SW2 to the analog sound signals from the decoder 5 with the control signal S2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a satellite broadcasting receiving system, for example, a television receiver with a built-in BS tuner (hereinafter referred to as a TV with a built-in BS) and a V receiver with a built-in BS tuner.
When one scramble decoder is shared with TR, when the receiving channel is switched from a scramble channel other than the scramble channel by the BS tuner on the VTR side, the audio signal of the TV with built-in BS is momentarily VT.
The present invention relates to a satellite broadcast receiving system capable of preventing output to the R side.

[0002]

2. Description of the Related Art FIG. 4 shows an audio demodulation system in a conventional satellite broadcast receiving system. In the audio demodulation system shown in this figure, for example, when one scramble decoder is shared by a TV with a built-in BS and a VTR with a built-in BS tuner, whether the received channel is other than the scrambled channel or the scrambled channel The BS tuner demodulates a BS format audio signal and can supply it to a recording / recording circuit.

In FIG. 4, reference numeral 1 is a BS antenna, 2
Is a BS converter, 3 is a television receiver with a built-in BS tuner (hereinafter referred to as a TV with built-in BS), 4 is a VT
The BS tuner 5 on the R side is a scramble decoder. In the built-in BS TV 3, the BS from the BS converter 2
The IF signal is channel selected and FM demodulated by the channel selection / FM demodulation circuit 31, and the FM demodulated baseband signal is input to a video processing unit (not shown) and a QPSK demodulation circuit 33. Q
In the PSK demodulation circuit 33, a QPSK demodulated signal QPSK-demodulated (a signal composed of a digital signal for scrambling and a voice signal, which will be referred to as a bit stream hereinafter).
Are supplied to the bit stream output terminal and the PCM decoder 34. This bit stream is a PCM decoder 35.
Is decoded into a PCM voice signal, converted into an analog voice signal by the D / A converter 36, and output. Switching circuit 36
Is switched by the output of a microcomputer (not shown). When the scrambled broadcast is received by the TV alone and when the BS tuner 4 is used (other than the scramble channel), the audio output from the audio terminal of the TV is selected to scramble the TV alone. D / when receiving a broadcast other than the channel
The audio output of the A converter 35 is selected.

On the other hand, in the BS tuner 4 on the VTR side, the BS-IF signal is tuned to the F / F demodulation circuit 41 and F
The M-demodulated and FM-demodulated baseband signal is input to a video processing unit (not shown) and a QPSK demodulation circuit 43. In the QPSK demodulation circuit 43, the QPSK demodulated bit stream is supplied to the input terminal b of the switch SW1 and the PCM decoder 44. The switch SW1 is composed of, for example, a mechanical relay, is connected to the terminal b by a control signal from the microcomputer 46 indicating the presence of scramble, and is other than the scramble channel (and when the power of the BS tuner 4 is off).
Is connected to the terminal a. The bit stream output of the TV is supplied to the terminal a. The bit stream output from SW1 is supplied to the scramble decoder 5. The PCM audio signal from the PCM decoder 44 becomes an analog audio signal in the D / A converter 45 and is supplied to the input end a of the switch SW2. The switch SW2 is composed of, for example, a semiconductor switch, is connected to the terminal b by a scrambled control signal from the microcomputer 46, and is connected to the terminal a except for the scrambled channel. Decoder output of the scramble decoder 5 (analog audio signal) at terminal b
Are being supplied. The scramble decoder 5 descrambles and PCM-decodes the bit stream output from the switch SW1 by the circuit 51,
The D / A converter 52 converts the decoded PCM signal into an analog audio signal and outputs the analog audio signal.

In the above structure, when the BS tuner 4 is turned off, the TV 3 with built-in BS can independently receive a scramble channel and a channel other than the scramble channel. That is, since the switch SW1 in the BS tuner 4 is made up of a relay, the bit stream output from the QPSK demodulation circuit 33 passes through the switch SW1 when the scrambled channel is received, and is demodulated into an analog audio signal by the scramble decoder 5 to produce a TV signal. Is output inside. Further, when a signal other than the scrambled channel is being received, the bit stream from the QPSK demodulation circuit 33 is demodulated through the PCM decoder 35 and the D / A converter 36 and output as audio in the TV.

On the other hand, when the BS tuner 4 on the VTR side is powered on and operating, if the BS tuner 4 is receiving a signal other than the scrambled channel, the audio signal of the BS tuner 4 is QPSK demodulated at 43 to 45. , PCM decoding, D / A conversion, audio output through the terminal a of the switch SW2, and supplied to a recording / recording circuit (not shown). Normally, the switches SW1 and SW2 are on the terminal a side, and the bit stream output of the TV is input to the scramble decoder 5, and the decoded audio output is input into the TV through the audio terminal of the TV.

Next, when the BS tuner receives the scrambled channel, the audio signal of the BS tuner 4 is transmitted to the PC.
The M decoder 44 determines that it is a scrambled channel, sends this information to the microcomputer 46, creates a high (H) level control signal indicating the presence of scramble, and switches the switches SW1 and SW2 to the terminal b side. As a result, the bit stream on the BS tuner 4 side is input to the scramble decoder 5. The analog audio signal decoded by the scramble decoder 5 is output as audio through the terminal b of SW2 and supplied to a recording / recording circuit (not shown).

As described above, in FIG. 4, the BS tuner 4
In order to allow the bit stream on the TV side to pass through even if the power is turned off, SW1 is configured with a relay and SW2 is configured with a semiconductor switch. However, as shown in Fig. 5 (a), scramble channels other than the scramble channel are used. Control signal with the same scramble (H
Since the switches SW1 and SW2 are switched by the level signal) and the relay is used for SW1, the switching time of SW1 is delayed from the switching time of SW2 as shown in FIG. 5 (c) (scrambling from the microcomputer 46). The signal is delayed by several msec with respect to the existing signal), and as shown in FIG. 5 (d), the scramble decoder 5 has a time delay due to descrambling and D / A conversion.
It takes time for the audio signal by the bitstream on the BS tuner side from SW2 to be output from SW2, as shown in FIG.
As shown in, there is a problem in that the audio by the bit stream from the TV is momentarily output and output to the video / audio recording circuit of the VTR.

[0009]

As described above, in the BS tuner on the VTR side, when the switches SW1 and SW2 are switched by the same control signal with scramble at the time of transition from the scramble channel to the scramble channel, the switch of SW1 Due to the switching time, the decoding time in the scramble decoder, the time delay due to D / A conversion, and the like, it takes time for the scramble decoder 5 to output the audio signal in the bit stream on the BS tuner side, and it depends on the bit stream from the TV side. There is a problem that the voice is output momentarily and is recorded and output to the VTR side.

Therefore, the present invention is to solve the above-mentioned problem, and when the VTR side BS tuner shifts from a channel other than the scramble channel to a scramble channel, the sound by the bit stream on the TV side is output. It is intended to provide a satellite broadcasting receiving system which does not exist.

[0011]

A satellite broadcasting receiving system according to the present invention as set forth in claim 1 includes first demodulating means for demodulating an audio signal from a received satellite broadcasting signal to obtain a first bit stream, and A first PCM decoder for converting the first bit stream into a digital audio signal, and a first D / A conversion means for converting the digital audio signal from the first PCM decoder into an analog audio signal No. 1 satellite broadcast receiving device, second demodulation means for demodulating an audio signal from the received satellite broadcast signal to obtain a second bit stream, and second demodulating means for converting the second bit stream into a digital audio signal. Based on the scramble presence / absence data from the PCM decoder and the second PCM decoder, the first control signal indicating that scramble is present and the first control signal is delayed by a predetermined time. A control signal generating means for generating a second control signal, a second D for converting the digital audio signal from the second PCM decoder into an analog audio signal
A second satellite broadcast receiving device having an A / A conversion means, and selectively outputting the first bit stream and the second bit stream using the first control signal, The second bit stream is output when the second demodulating means is receiving a scrambled channel, and the second bit stream is output when the second demodulating means is in the inactive state or is receiving a channel other than the scrambled channel. A first switch that outputs a first bit stream, a scramble decoder that decodes the bit stream output from the first switch and converts it into an analog audio signal, an analog audio signal from the scramble decoder, and the second audio signal. For selectively outputting the analog audio signal from the D / A conversion means of the second control signal using the second control signal. When the second demodulation means receives a scrambled channel, it outputs the analog audio signal from the scramble decoder, and when the second demodulation means receives a channel other than the scrambled channel, the second demodulation means outputs the analog audio signal. And a second switch for outputting an analog audio signal from the D / A conversion means of.

A satellite broadcasting receiving system according to a second aspect of the present invention is the system according to the first aspect, wherein the first switch is a relay and the second switch is a semiconductor switch. A delay time of the second control signal with respect to the first control signal is a time corresponding to a switching time of the first switch and a signal processing time of the scramble decoder.

[0013]

According to the present invention, the control signal supplied to the second switch is delayed by the switching operation time of the first switch and the signal processing time of the scramble decoder, so that the first switch and the second switch are delayed. The switching timings can be matched, and even if the channel is switched from a non-scrambled channel to a scrambled channel, the TV
It is possible to solve the problem that the audio is output momentarily by the bit stream from the side.

[0014]

EXAMPLES Examples will be described with reference to the drawings. FIG. 1 is a block diagram showing a satellite broadcast receiving system according to an embodiment of the present invention.

In FIG. 1, the same parts as those in FIG. 4 are designated by the same reference numerals. Reference numeral 1 is a BS antenna, 2 is a BS converter, 3 is a TV with a built-in BS, 4 is a BS tuner on the VTR side, and 5 is a scramble decoder. TV with built-in BS3
Then, the BS-IF signal from the BS converter 2 is selected.
The FM demodulation circuit 31 performs channel selection and FM demodulation, and the FM demodulated baseband signal is transmitted to a video processing unit (not shown) and QP.
It is input to the SK demodulation circuit 33. QPSK demodulation circuit 33
Then, a QPSK demodulated signal (a signal composed of a digital signal for descrambling and a voice signal, which will be referred to as a bit stream hereinafter) subjected to QPSK demodulation is supplied to a bit stream output terminal and the PCM decoder 34. This bit stream is decoded into a PCM audio signal by the PCM decoder 35, converted into an analog audio signal by the D / A converter 36, and output. The switching circuit 36 is switched by the output of a microcomputer (not shown), and selects the audio output from the audio terminal of the TV when the TV alone receives the scrambled broadcast and when the BS tuner 4 is used (other than the scramble channel), When the broadcast other than the scramble channel is received by itself, the audio output of the D / A converter 35 is selected.

On the other hand, in the BS tuner 4 on the VTR side, the BS-IF signal is tuned in the channel selection / FM demodulation circuit 41 and F
The M-demodulated and FM-demodulated baseband signal is input to a video processing unit (not shown) and a QPSK demodulation circuit 43. In the QPSK demodulation circuit 43, the QPSK demodulated bit stream is supplied to the input terminal b of the switch SW1 and the PCM decoder 44. The switch SW1 is composed of, for example, a mechanical relay, and is connected to the terminal b by the control signal S1 from the microcomputer 46 indicating that scramble is present, and is connected to the terminal a except for the scramble channel (and when the power of the BS tuner 4 is off). It is like this. Terminal a
Is supplied with the bit stream output of the TV. The bit stream output from SW1 is supplied to the scramble decoder 5. The PCM decoder 4
The PCM audio signal from 4 is converted into an analog audio signal by the D / A converter 45 and supplied to the input end a of the switch SW2. The switch SW2 is composed of, for example, a semiconductor switch, and is connected to the terminal b by a signal obtained by delaying the scrambled control signal S1 from the microcomputer 46 by the delay circuit 47 for a predetermined time, and is connected to the terminal a except for the scrambled channel. ing. The delay circuit 47 delays the control signal S1 by a predetermined time corresponding to the switching time of the switch SW1 and the signal processing time of the scramble decoder 5 so as to match the switching timings of the switches SW1 and SW2. It is output. The decoder output (analog audio signal) of the scramble decoder 5 is supplied to the terminal b. The scramble decoder 5 is configured to descramble and PCM-decode the bit stream output from the switch SW1 by the circuit 51, convert the decoded PCM signal into an analog audio signal by the D / A converter 52, and output the analog audio signal. .

A circuit of an embodiment of the delay circuit 47 is shown in FIG.
Shown in. In FIG. 2, the control signal S1 from the switch SW1 is supplied to the base of the transistor Q1 via a time constant circuit. The time constant circuit is configured so that a resistor r1 and a capacitor C1 are connected in series between the input end and the reference potential point, and the base output is obtained from the connection point. The emitter of the transistor Q1 is connected to the reference potential point, and the collector is connected to the DC power source Vcc via the resistor R2. Further, the collector of the transistor Q1 is connected to the base of the transistor Q2 in the next stage, the emitter thereof is connected to the reference potential point, and the collector is connected to the DC power supply Vcc via the resistor R3.

In the circuit of FIG. 2, when a high-level control signal S1 indicating the presence of scrambling is input to the time constant circuit, the capacitor C1 is charged, and the charging voltage thereof reaches a predetermined value (the base-emitter of the transistor Q1). Voltage), transistor Q1 turns on and transistor Q2
Is turned off and a high level control signal S2 is output to the collector of the transistor Q2. The control signal S2 is delayed from the control signal S1 by a predetermined time based on the charging.

In the above arrangement, when the power of the BS tuner 4 is off, the TV 3 with built-in BS can independently receive the scramble channel and a channel other than the scramble channel. That is, since the switch SW1 in the BS tuner 4 is made up of a relay, the bit stream output from the QPSK demodulation circuit 33 passes through the switch SW1 when the scrambled channel is received, and is demodulated into an analog audio signal by the scramble decoder 5 to produce a TV signal. Is output inside. Further, when a signal other than the scrambled channel is being received, the bit stream from the QPSK demodulation circuit 33 is demodulated through the PCM decoder 35 and the D / A converter 36 and output as audio in the TV.

On the other hand, when the BS tuner 4 on the VTR side is powered on and operating, if the BS tuner 4 is receiving a signal other than the scrambled channel, the audio signal of the BS tuner 4 is QPSK demodulated at 43 to 45. , PCM decoding, D / A conversion, audio output through the terminal a of the switch SW2, and supplied to a recording / recording circuit (not shown). Normally, the switches SW1 and SW2 are on the terminal a side, and the bit stream output of the TV is input to the scramble decoder 5, and the decoded audio output is input into the TV through the audio terminal of the TV.

Next, when the BS tuner receives the scrambled channel, the audio signal of the BS tuner 4 is PC.
The M decoder 44 determines that it is a scrambled channel, sends this information to the microcomputer 46, creates a high (H) level control signal S1 indicating the presence of scramble, and switches the switch SW1 to the terminal b side, and at the same time, outputs the control signal. Control signal S2 obtained by delaying S1 by delay circuit 47 for a predetermined time
And switch SW2 to the terminal b side. As a result, the bit stream on the BS tuner 4 side is input to the scramble decoder 5. The analog audio signal decoded by the scramble decoder 5 is output as audio through the terminal b of SW2 and supplied to a video recording / recording circuit (not shown).

As described above, in the VTR side BS tuner 4, when the channel other than the scramble channel is changed to the scramble channel, the control signal S with scramble is provided.
1 is output from the microcomputer 46, and switches SW1 and SW
2 is switched to the terminal b side, but the control signal S2 with scramble of the switch SW2 is controlled by the switch S1 of the switch SW1.
As described above, by delaying the time from the scramble decoder 5 until the audio from the bitstream on the BS tuner side is output, the problem that the audio from the bitstream on the TV side is output from the audio output can be solved.

FIG. 3 is a circuit diagram showing another embodiment of the present invention. In the embodiment of the present invention shown in this figure, instead of providing the delay circuit 47 as shown in the embodiment of FIG. 1, the control signal S1 indicating the presence of scramble is output from the microcomputer 46, and the microcomputer 46 outputs a predetermined signal. The control signal S2 indicating the time-delayed scramble is output. The control signal S2 is a signal delayed from the control signal S1 by a predetermined time corresponding to the switching time of the switch SW1 and the signal processing time of the scramble decoder 51 so as to match the switching timings of the switches SW1 and SW2. Other configurations are the same as those in FIG. 1, and the effects are the same as those in FIG.

In the embodiment shown in FIGS. 1 and 2, the switch S
Although a relay is used as W1, the switch SW is used in the present invention.
1 is not limited to a relay, but may be another switch (for example, a semiconductor switch). That is, the switch SW1 may be any switch as long as it can pass the signal on the TV 3 side even when the power of the BS tuner 4 is off.

[0025]

As described above, according to the present invention, the VT
When the R-side BS tuner shifts from a channel other than the scramble channel to a scramble channel, it is possible to solve the problem that the audio by the bit stream on the TV side is momentarily output to the VTR side.

[Brief description of drawings]

FIG. 1 is a block diagram showing an audio demodulation system in a satellite broadcast receiving system according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the delay circuit in FIG.

FIG. 3 is a block diagram showing another embodiment of the present invention.

FIG. 4 is a block diagram showing an audio demodulation system in a conventional satellite broadcast receiving system.

FIG. 5 is a diagram illustrating a conventional defect.

[Explanation of symbols]

 3 TV with built-in BS (first satellite broadcast receiving device) 4 VTR side BS tuner 5 Scramble decoder 31, 41 Channel selection / FM demodulation circuit 33, 43 QPSK demodulation circuit 34, 44 PCM decoder 35, 45 D / A converter 46 Microcomputer 47 Delay Circuit 51 Descramble and PCM Decode Circuit 52 D / A Converter SW1 Switch SW2 Switch

Claims (2)

[Claims] 1. A first demodulation means for demodulating an audio signal from a received satellite broadcast signal to obtain a first bit stream,
A first PCM decoder for converting the first bit stream into a digital audio signal, and a first D / A conversion means for converting the digital audio signal from the first PCM decoder into an analog audio signal are provided. A first satellite broadcast receiving device, a second demodulation means for demodulating an audio signal from the received satellite broadcast signal to obtain a second bit stream, and a second demodulating means for converting the second bit stream into a digital audio signal. And a control signal generating means for generating a first control signal indicating the presence of scramble and a second control signal obtained by delaying the first control signal for a predetermined time based on the scramble presence / absence data from the second PCM decoder. The second P
A second satellite broadcast receiving device including a second D / A conversion means for converting a digital audio signal from a CM decoder into an analog audio signal, and the first bit stream and the second bit stream. The second demodulation means outputs the second bit stream when the second demodulation means is receiving a scrambled channel and selectively outputs the second bit stream by using the first control signal. Is in an inactive state or is receiving a channel other than a scrambled channel, a first switch that outputs the first bitstream, and a bitstream output from the first switch are decoded into an analog audio signal. A scramble decoder for converting, an analog audio signal from this scramble decoder and the second D / A converting means. An analog audio signal from the scramble decoder when the second demodulating means is receiving a scrambled channel. The analog audio signal and the analog audio signal are selectively output using the second control signal. A second switch for outputting the analog audio signal from the second D / A conversion means when the second demodulation means is receiving a channel other than a scrambled channel. Satellite broadcasting receiving system. 2. The first switch comprises a relay,
The second switch is composed of a semiconductor switch, and the delay time of the second control signal with respect to the first control signal corresponds to the switching time of the first switch and the signal processing time of the scramble decoder. The satellite broadcasting receiving system according to claim 1, wherein the satellite broadcasting receiving system is a time when the satellite broadcasting is received.