JPH05103253A - Video camera - Google Patents

Video camera

Info

Publication number
JPH05103253A
JPH05103253A JP3262459A JP26245991A JPH05103253A JP H05103253 A JPH05103253 A JP H05103253A JP 3262459 A JP3262459 A JP 3262459A JP 26245991 A JP26245991 A JP 26245991A JP H05103253 A JPH05103253 A JP H05103253A
Authority
JP
Japan
Prior art keywords
video
seconds
converter
digital video
memories
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3262459A
Other languages
Japanese (ja)
Inventor
Ichiro Noborikawa
一郎 登川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3262459A priority Critical patent/JPH05103253A/en
Publication of JPH05103253A publication Critical patent/JPH05103253A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To set a shutter speed to be longer than 1/60 seconds, and to obtain a smooth video. CONSTITUTION:At the time of setting the shutter speed of an image pickup element 1 to be longer than 1/60 seconds, the shutter speed is fixed to be 1/60 seconds, and transmitted to an A/D converter 2 at every 1/60 seconds. A digital video signal obtained by the A/D converter 2 is transmitted through (n) pieces of adders 3-1 to 3-n in parallel to (n) pieces of video memories 4-1 to 4-n, and added to the digital video signal held at present in each video memory 4-1 to 4-n. On the other hand. it is necessary to transmit the digital video from an output video switching circuit 5 to a D/A converter 6 at every 1/60 seconds, and the digital video signal is successively read out from each video memory 4-1 to 4-n at 1/60 second interval, and simultaneously the data in the video memories 4-1 to 4-n after the read out are erased.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、シャッタースピードを
1/60秒より長く設定できるビデオカメラに関するもので
ある。
The present invention relates to a shutter speed
It relates to a video camera that can be set longer than 1/60 seconds.

【0002】[0002]

【従来の技術】従来のビデオカメラでは、図4に示すよ
うにビデオカメラ内の撮像素子11のシャッタースピード
を1/60秒よりも長くし、得られた映像信号はA/Dコン
バータ12によりデジタル信号に変換された後、映像メモ
リ14に記憶される。このとき出力映像切替回路15の制御
信号により撮像素子11から映像信号が送られる回数は毎
秒60回よりも少ないため、その分は映像メモリ14に記憶
された信号を出力映像切替回路15の別の制御信号により
1/60秒毎に繰り返しD/Aコンバータ16を通してビデオ
テープレコーダへ送る。
2. Description of the Related Art In a conventional video camera, as shown in FIG. 4, the shutter speed of an image pickup device 11 in the video camera is set longer than 1/60 seconds, and the obtained video signal is digitalized by an A / D converter 12. After being converted into a signal, it is stored in the video memory 14. At this time, the number of times that the image signal is sent from the image pickup device 11 by the control signal of the output video switching circuit 15 is less than 60 times per second, and thus the signal stored in the video memory 14 is different from that of the output video switching circuit 15. By control signal
It is repeatedly sent to the video tape recorder through the D / A converter 16 every 1/60 seconds.

【0003】[0003]

【発明が解決しようとする課題】このような従来の構成
では、撮像素子11から得られる映像信号が毎秒60画面分
より少なくなるために、同じ画面を複数回連続して出力
することになる。そのため、動きの早い映像では得られ
る画像が滑らかでなくなる。
In such a conventional structure, since the image signal obtained from the image pickup device 11 is less than 60 screens per second, the same screen is continuously output a plurality of times. Therefore, an image obtained with a fast moving image is not smooth.

【0004】本発明は上記問題を解決するもので、ビデ
オカメラのシャッタースピードを1/60秒よりも長く設定
でき、なおかつ得られる映像の動きをなめらかにするこ
とのできるビデオカメラを提供することを目的としてい
る。
The present invention solves the above problems and provides a video camera in which the shutter speed of the video camera can be set longer than 1/60 seconds, and the movement of the obtained image can be smoothed. Has a purpose.

【0005】[0005]

【課題を解決するための手段】上記課題を解決するため
に、本発明のビデオカメラは、撮像素子と、前記撮像素
子からの映像信号をデジタル映像信号に変換するA/D
コンバータと、デジタル映像信号を記憶する複数の映像
メモリと、前記映像メモリのデジタル映像信号と前記A
/Dコンバータからのデジタル映像信号を足し合わせる
複数の加算器と、前記複数の映像メモリに対し1つずつ
順次選択し選択された1つの映像メモリのデータをデジ
タル映像信号として出力しその直後に前記1つの映像メ
モリのデータを消去する出力映像切り替え回路と、前記
出力映像切り替え回路からのデジタル映像信号を映像信
号に変換するD/Aコンバータを備えたものである。
In order to solve the above problems, a video camera of the present invention comprises an image pickup device and an A / D for converting a video signal from the image pickup device into a digital video signal.
A converter, a plurality of video memories for storing digital video signals, a digital video signal of the video memory and the A
A plurality of adders for adding the digital video signals from the D / D converter and one by one to the plurality of video memories are sequentially selected, and the data of one selected video memory is output as a digital video signal, and immediately after that An output video switching circuit for erasing data in one video memory and a D / A converter for converting a digital video signal from the output video switching circuit into a video signal are provided.

【0006】[0006]

【作用】上記構成により、複数画面分の映像信号を記憶
できる映像メモリを使用し、各々の映像メモリにデジタ
ル映像信号の加算器を付加することにより、ビデオカメ
ラのシャッタースピードを1/60秒の整数倍に長く設定で
き、なおかつ得られる映像の動きをなめらかにすること
ができる。
With the above structure, a video memory capable of storing video signals for a plurality of screens is used, and a digital video signal adder is added to each video memory, thereby reducing the shutter speed of the video camera to 1/60 second. It can be set to an integral multiple, and the motion of the resulting image can be smoothed.

【0007】[0007]

【実施例】以下本発明の一実施例を図面に基づいて説明
する。図1は本発明のビデオカメラの一実施例を示す概
要ブロック図である。図1において、撮像素子1のシャ
ッタースピードは、1/60秒より長くしたい場合において
も1/60秒に固定し、1/60秒毎にA/Dコンバータ2に送
られる。A/Dコンバータ2により得られたデジタル映
像信号は並行してn個の加算器3−1〜3−nを通して
映像メモリ4−1〜4−nにそれぞれ送られ、それぞれ
の映像メモリ4−1〜4−nは現在保持しているデジタ
ル映像信号にA/Dコンバータ2の信号が加算され記憶
される。一方出力映像切り替え回路5からは、D/Aコ
ンバータ6に1/60秒ごとにデジタル映像を送る必要があ
るため、それぞれの映像メモリ4−1〜4−nから1/60
秒間隔で順次デジタル映像信号を読み出すと同時に読み
だしたあとの映像メモリ4−1〜4−n内のデータを消
去する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic block diagram showing an embodiment of a video camera of the present invention. In FIG. 1, the shutter speed of the image sensor 1 is fixed to 1/60 second even when it is desired to be longer than 1/60 second, and is sent to the A / D converter 2 every 1/60 second. The digital video signals obtained by the A / D converter 2 are sent in parallel to the video memories 4-1 to 4-n through the n adders 3-1 to 3-n, respectively, and the respective video memories 4-1 are sent. For signals 4-n, the signal of the A / D converter 2 is added to the currently held digital video signal and stored. On the other hand, since it is necessary to send a digital image from the output image switching circuit 5 to the D / A converter 6 every 1/60 seconds, 1/60 from each of the image memories 4-1 to 4-n.
At the same time, the digital video signals are sequentially read out at a time interval, and at the same time, the data in the video memories 4-1 to 4-n after the reading are erased.

【0008】この動作の概要を図2に示す。横軸に1/60
秒単位の時刻を取り、各々の時刻における撮像素子の撮
影した映像を便宜上……,t−n+1,……,t−2,
t−1,t,t+1,t+2,……,t+n−1,t+
n,t+n+1,……とする。それぞれの時刻におい
て、それぞれの映像メモリ4−1〜4−nの映像、出力
映像切り替え回路5が選択した映像メモリおよび選択し
た映像信号を合わせて示す。
An outline of this operation is shown in FIG. 1/60 on the horizontal axis
Taking the time in seconds, the images taken by the image pickup device at each time are conveniently ..., t-n + 1, ..., t-2,
t-1, t, t + 1, t + 2, ..., t + n-1, t +
n, t + n + 1, ... At each time, the images of the respective image memories 4-1 to 4-n, the image memory selected by the output image switching circuit 5 and the selected image signal are also shown.

【0009】このような動作により、読みだしたデジタ
ル映像信号は常にn/60秒の映像となり、n/60秒のス
ローシャッターの映像が得られる。しかもあるコマとそ
の次のコマを比較すると、図2からも明らかなように
(n−1)/60秒は同じ時刻の映像信号であり、異なる
時刻の映像信号は1/60秒しかないため、各々のコマの違
いが少なくなり、滑らかな動きのある映像が得られる。
また、このときのビデオカメラとしての最低照度は1/60
秒のときの1/nとなり、高感度撮影も可能である。
By such an operation, the read digital video signal is always a video of n / 60 seconds, and a slow shutter video of n / 60 seconds can be obtained. Moreover, when comparing one frame and the next frame, as is clear from FIG. 2, (n-1) / 60 seconds are video signals at the same time, and video signals at different times are only 1/60 seconds. , The difference between each frame is reduced, and smooth moving images can be obtained.
Also, the minimum illuminance as a video camera at this time is 1/60
It is 1 / n of a second, and high-sensitivity shooting is possible.

【0010】図3は本発明の具体的な一実施例を示す概
要ブロック図である。加算器31, 32,33, 34, 35, 36に
より加算可能な6画面分の映像メモリ41, 42, 43, 44,
45,46を用意することにより、1/10(6/60)秒のスロ
ーシャッターが実現でき、なおかつ滑らかな動きが得ら
れる。また、このときのビデオカメラとしての最低照度
は1/60秒のときの1/6となり、高感度撮影も可能で
ある。
FIG. 3 is a schematic block diagram showing a concrete embodiment of the present invention. 6 screens of video memory 41, 42, 43, 44 that can be added by adders 31, 32, 33, 34, 35, 36
By preparing 45 and 46, a slow shutter of 1/10 (6/60) seconds can be realized and smooth movement can be obtained. In addition, the minimum illuminance of the video camera at this time is ⅙ of the 1/60 second, and high-sensitivity shooting is possible.

【0011】[0011]

【発明の効果】以上のように、本発明によれば、ビデオ
カメラのシャッタースピードを1/60秒よりも長く設定
でき、なおかつ得られる映像の動きをなめらかにするこ
とが可能となる。
As described above, according to the present invention, the shutter speed of the video camera can be set to be longer than 1/60 second, and the motion of the obtained image can be smoothed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のビデオカメラの一実施例を示す概要ブ
ロック図である。
FIG. 1 is a schematic block diagram showing an embodiment of a video camera of the present invention.

【図2】本発明のビデオカメラの動作時の各部の処理映
像を示す概要図である。
FIG. 2 is a schematic diagram showing a processed image of each unit during operation of the video camera of the present invention.

【図3】本発明のビデオカメラの具体的な実施例を示す
概要ブロック図である。
FIG. 3 is a schematic block diagram showing a specific embodiment of the video camera of the present invention.

【図4】従来のビデオカメラを示す概要図である。FIG. 4 is a schematic diagram showing a conventional video camera.

【符号の説明】[Explanation of symbols]

1 撮像素子 2 A/Dコンバータ 3−1〜3−n 加算器 4−1〜4−n 映像メモリ 5 出力映像切り替え回路 6 D/Aコンバータ 1 Image sensor 2 A / D converter 3-1 to 3-n Adder 4-1 to 4-n Video memory 5 Output video switching circuit 6 D / A converter

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 撮像素子と、前記撮像素子からの映像信
号をデジタル映像信号に変換するA/Dコンバータと、
デジタル映像信号を記憶する複数の映像メモリと、前記
映像メモリのデジタル映像信号と前記A/Dコンバータ
からのデジタル映像信号を足し合わせる複数の加算器
と、前記複数の映像メモリに対し1つずつ順次選択し選
択された1つの映像メモリのデータをデジタル映像信号
として出力しその直後に前記1つの映像メモリのデータ
を消去する出力映像切り替え回路と、前記出力映像切り
替え回路からのデジタル映像信号を映像信号に変換する
D/Aコンバータを備えたビデオカメラ。
1. An image sensor, and an A / D converter for converting a video signal from the image sensor into a digital video signal,
A plurality of video memories for storing digital video signals, a plurality of adders for adding the digital video signals of the video memories and the digital video signals from the A / D converter, and one for each of the plurality of video memories An output video switching circuit for outputting data of the selected one selected video memory as a digital video signal and immediately thereafter deleting the data of the one video memory, and a digital video signal from the output video switching circuit Video camera equipped with a D / A converter to convert to.
JP3262459A 1991-10-11 1991-10-11 Video camera Pending JPH05103253A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3262459A JPH05103253A (en) 1991-10-11 1991-10-11 Video camera

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3262459A JPH05103253A (en) 1991-10-11 1991-10-11 Video camera

Publications (1)

Publication Number Publication Date
JPH05103253A true JPH05103253A (en) 1993-04-23

Family

ID=17376083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3262459A Pending JPH05103253A (en) 1991-10-11 1991-10-11 Video camera

Country Status (1)

Country Link
JP (1) JPH05103253A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7623153B2 (en) 2004-08-31 2009-11-24 Sanyo Electric Co., Ltd. Unintentional hand movement canceling device and imaging apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7623153B2 (en) 2004-08-31 2009-11-24 Sanyo Electric Co., Ltd. Unintentional hand movement canceling device and imaging apparatus
US7633525B2 (en) 2004-08-31 2009-12-15 Sanyo Electric Co., Ltd. Unintentional hand movement canceling device and imaging apparatus

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